Lines Matching +full:0 +full:x1e0
46 uint32 corecontrol; /* 0x0 */
47 uint32 corestatus; /* 0x4 */
49 uint32 biststatus; /* 0xc */
50 uint32 nmiisrst; /* 0x10 */
51 uint32 nmimask; /* 0x14 */
52 uint32 isrmask; /* 0x18 */
54 uint32 resetlog; /* 0x20 */
55 uint32 gpioselect; /* 0x24 */
56 uint32 gpioenable; /* 0x28 */
58 uint32 bpaddrlo; /* 0x30 */
59 uint32 bpaddrhi; /* 0x34 */
60 uint32 bpdata; /* 0x38 */
61 uint32 bpindaccess; /* 0x3c */
62 uint32 ovlidx; /* 0x40 */
63 uint32 ovlmatch; /* 0x44 */
64 uint32 ovladdr; /* 0x48 */
66 uint32 bwalloc; /* 0x80 */
68 uint32 cyclecnt; /* 0x90 */
69 uint32 inttimer; /* 0x94 */
70 uint32 intmask; /* 0x98 */
71 uint32 intstatus; /* 0x9c */
73 uint32 clk_ctl_st; /* 0x1e0 */
75 uint32 powerctl; /* 0x1e8 */
81 uint32 corecontrol; /* 0x0 */
82 uint32 corecapabilities; /* 0x4 */
83 uint32 corestatus; /* 0x8 */
84 uint32 biststatus; /* 0xc */
85 uint32 nmiisrst; /* 0x10 */
86 uint32 nmimask; /* 0x14 */
87 uint32 isrmask; /* 0x18 */
88 uint32 swintreg; /* 0x1C */
89 uint32 intstatus; /* 0x20 */
90 uint32 intmask; /* 0x24 */
91 uint32 cyclecnt; /* 0x28 */
92 uint32 inttimer; /* 0x2c */
93 uint32 gpioselect; /* 0x30 */
94 uint32 gpioenable; /* 0x34 */
96 uint32 bankidx; /* 0x40 */
97 uint32 bankinfo; /* 0x44 */
98 uint32 bankstbyctl; /* 0x48 */
99 uint32 bankpda; /* 0x4c */
101 uint32 tcampatchctrl; /* 0x68 */
102 uint32 tcampatchtblbaseaddr; /* 0x6c */
103 uint32 tcamcmdreg; /* 0x70 */
104 uint32 tcamdatareg; /* 0x74 */
105 uint32 tcambankxmaskreg; /* 0x78 */
107 uint32 clk_ctl_st; /* 0x1e0 */
109 uint32 powerctl; /* 0x1e8 */
115 uint32 corecontrol; /* 0x0 */
116 uint32 corecapabilities; /* 0x4 */
117 uint32 corestatus; /* 0x8 */
118 uint32 tracecontrol; /* 0xc */
120 uint32 gpioselect; /* 0x30 */
121 uint32 gpioenable; /* 0x34 */
123 uint32 clk_ctl_st; /* 0x1e0 */
125 uint32 powerctl; /* 0x1e8 */