Lines Matching +full:0 +full:x25c
48 #define GCI_CORE_IDX(sih) (AOB_ENAB(sih) ? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
51 uint32 gci_corecaps0; /* 0x000 */
52 uint32 gci_corecaps1; /* 0x004 */
53 uint32 gci_corecaps2; /* 0x008 */
54 uint32 gci_corectrl; /* 0x00c */
55 uint32 gci_corestat; /* 0x010 */
56 uint32 gci_intstat; /* 0x014 */
57 uint32 gci_intmask; /* 0x018 */
58 uint32 gci_wakemask; /* 0x01c */
59 uint32 gci_levelintstat; /* 0x020 */
60 uint32 gci_eventintstat; /* 0x024 */
61 uint32 gci_wakelevelintstat; /* 0x028 */
62 uint32 gci_wakeeventintstat; /* 0x02c */
63 uint32 semaphoreintstatus; /* 0x030 */
64 uint32 semaphoreintmask; /* 0x034 */
65 uint32 semaphorerequest; /* 0x038 */
66 uint32 semaphorereserve; /* 0x03c */
67 uint32 gci_indirect_addr; /* 0x040 */
68 uint32 gci_gpioctl; /* 0x044 */
69 uint32 gci_gpiostatus; /* 0x048 */
70 uint32 gci_gpiomask; /* 0x04c */
71 uint32 gci_eventsummary; /* 0x050 */
72 uint32 gci_miscctl; /* 0x054 */
73 uint32 gci_gpiointmask; /* 0x058 */
74 uint32 gci_gpiowakemask; /* 0x05c */
75 uint32 gci_input[32]; /* 0x060 */
76 uint32 gci_event[32]; /* 0x0e0 */
77 uint32 gci_output[4]; /* 0x160 */
78 uint32 gci_control_0; /* 0x170 */
79 uint32 gci_control_1; /* 0x174 */
80 uint32 gci_intpolreg; /* 0x178 */
81 uint32 gci_levelintmask; /* 0x17c */
82 uint32 gci_eventintmask; /* 0x180 */
83 uint32 wakelevelintmask; /* 0x184 */
84 uint32 wakeeventintmask; /* 0x188 */
85 uint32 hwmask; /* 0x18c */
87 uint32 gci_inbandeventintmask; /* 0x194 */
89 uint32 gci_inbandeventstatus; /* 0x19c */
90 uint32 gci_seciauxtx; /* 0x1a0 */
91 uint32 gci_seciauxrx; /* 0x1a4 */
92 uint32 gci_secitx_datatag; /* 0x1a8 */
93 uint32 gci_secirx_datatag; /* 0x1ac */
94 uint32 gci_secitx_datamask; /* 0x1b0 */
95 uint32 gci_seciusef0tx_reg; /* 0x1b4 */
96 uint32 gci_secif0tx_offset; /* 0x1b8 */
97 uint32 gci_secif0rx_offset; /* 0x1bc */
98 uint32 gci_secif1tx_offset; /* 0x1c0 */
99 uint32 gci_rxfifo_common_ctrl; /* 0x1c4 */
100 uint32 gci_rxfifoctrl; /* 0x1c8 */
101 uint32 gci_hw_sema_status; /* 0x1cc */
102 uint32 gci_seciuartescval; /* 0x1d0 */
103 uint32 gic_seciuartautobaudctr; /* 0x1d4 */
104 uint32 gci_secififolevel; /* 0x1d8 */
105 uint32 gci_seciuartdata; /* 0x1dc */
106 uint32 gci_secibauddiv; /* 0x1e0 */
107 uint32 gci_secifcr; /* 0x1e4 */
108 uint32 gci_secilcr; /* 0x1e8 */
109 uint32 gci_secimcr; /* 0x1ec */
110 uint32 gci_secilsr; /* 0x1f0 */
111 uint32 gci_secimsr; /* 0x1f4 */
112 uint32 gci_baudadj; /* 0x1f8 */
113 uint32 gci_inbandintmask; /* 0x1fc */
114 uint32 gci_chipctrl; /* 0x200 */
115 uint32 gci_chipsts; /* 0x204 */
116 uint32 gci_gpioout; /* 0x208 */
117 uint32 gci_gpioout_read; /* 0x20C */
118 uint32 gci_mpwaketx; /* 0x210 */
119 uint32 gci_mpwakedetect; /* 0x214 */
120 uint32 gci_seciin_ctrl; /* 0x218 */
121 uint32 gci_seciout_ctrl; /* 0x21C */
122 uint32 gci_seciin_auxfifo_en; /* 0x220 */
123 uint32 gci_seciout_txen_txbr; /* 0x224 */
124 uint32 gci_seciin_rxbrstatus; /* 0x228 */
125 uint32 gci_seciin_rxerrstatus; /* 0x22C */
126 uint32 gci_seciin_fcstatus; /* 0x230 */
127 uint32 gci_seciout_txstatus; /* 0x234 */
128 uint32 gci_seciout_txbrstatus; /* 0x238 */
129 uint32 wlan_mem_info; /* 0x23C */
130 uint32 wlan_bankxinfo; /* 0x240 */
131 uint32 bt_smem_select; /* 0x244 */
132 uint32 bt_smem_stby; /* 0x248 */
133 uint32 bt_smem_status; /* 0x24C */
134 uint32 wlan_bankxactivepda; /* 0x250 */
135 uint32 wlan_bankxsleeppda; /* 0x254 */
136 uint32 wlan_bankxkill; /* 0x258 */
137 uint32 PAD[PADSZ(0x25c, 0x268)]; /* 0x25c-0x268 */
138 uint32 bt_smem_control0; /* 0x26C */
139 uint32 bt_smem_control1; /* 0x270 */
140 uint32 PAD[PADSZ(0x274, 0x2fc)]; /* 0x274-0x2fc */
141 uint32 gci_chipid; /* 0x300 */
142 uint32 PAD[PADSZ(0x304, 0x30c)]; /* 0x304-0x30c */
143 uint32 otpstatus; /* 0x310 */
144 uint32 otpcontrol; /* 0x314 */
145 uint32 otpprog; /* 0x318 */
146 uint32 otplayout; /* 0x31c */
147 uint32 otplayoutextension; /* 0x320 */
148 uint32 otpcontrol1; /* 0x324 */
149 uint32 otpprogdata; /* 0x328 */
150 uint32 PAD[PADSZ(0x32c, 0x3f8)]; /* 0x32c-0x3f8 */
151 uint32 otpECCstatus; /* 0x3FC */
152 uint32 PAD[PADSZ(0x400, 0x6fc)]; /* 0x400-0x6fc */
153 uint32 ctss_clk_ctrl_status; /* 0x700 */
154 uint32 PAD[PADSZ(0x704, 0xbfc)]; /* 0x704-0xbfc */
155 uint32 lhl_core_capab_adr; /* 0xC00 */
156 uint32 lhl_main_ctl_adr; /* 0xC04 */
157 uint32 lhl_pmu_ctl_adr; /* 0xC08 */
158 uint32 lhl_extlpo_ctl_adr; /* 0xC0C */
159 uint32 lpo_ctl_adr; /* 0xC10 */
160 uint32 lhl_lpo2_ctl_adr; /* 0xC14 */
161 uint32 lhl_osc32k_ctl_adr; /* 0xC18 */
162 uint32 lhl_clk_status_adr; /* 0xC1C */
163 uint32 lhl_clk_det_ctl_adr; /* 0xC20 */
164 uint32 lhl_clk_sel_adr; /* 0xC24 */
165 uint32 hidoff_cnt_adr[2]; /* 0xC28-0xC2C */
166 uint32 lhl_autoclk_ctl_adr; /* 0xC30 */
168 uint32 lhl_hibtim_adr; /* 0xC38 */
169 uint32 lhl_wl_ilp_val_adr; /* 0xC3C */
170 uint32 lhl_wl_armtim0_intrp_adr; /* 0xC40 */
171 uint32 lhl_wl_armtim0_st_adr; /* 0xC44 */
172 uint32 lhl_wl_armtim0_adr; /* 0xC48 */
173 uint32 PAD[PADSZ(0xc4c, 0xc6c)]; /* 0xC4C-0xC6C */
174 uint32 lhl_wl_mactim0_intrp_adr; /* 0xC70 */
175 uint32 lhl_wl_mactim0_st_adr; /* 0xC74 */
176 uint32 lhl_wl_mactim_int0_adr; /* 0xC78 */
177 uint32 lhl_wl_mactim_frac0_adr; /* 0xC7C */
178 uint32 lhl_wl_mactim1_intrp_adr; /* 0xC80 */
179 uint32 lhl_wl_mactim1_st_adr; /* 0xC84 */
180 uint32 lhl_wl_mactim_int1_adr; /* 0xC88 */
181 uint32 lhl_wl_mactim_frac1_adr; /* 0xC8C */
182 uint32 PAD[PADSZ(0xc90, 0xcac)]; /* 0xC90-0xCAC */
183 uint32 gpio_int_en_port_adr[4]; /* 0xCB0-0xCBC */
184 uint32 gpio_int_st_port_adr[4]; /* 0xCC0-0xCCC */
185 uint32 gpio_ctrl_iocfg_p_adr[40]; /* 0xCD0-0xD6C */
186 uint32 lhl_lp_up_ctl1_adr; /* 0xd70 */
187 uint32 lhl_lp_dn_ctl1_adr; /* 0xd74 */
188 uint32 PAD[PADSZ(0xd78, 0xdb4)]; /* 0xd78-0xdb4 */
189 uint32 lhl_sleep_timer_adr; /* 0xDB8 */
190 uint32 lhl_sleep_timer_ctl_adr; /* 0xDBC */
191 uint32 lhl_sleep_timer_load_val_adr; /* 0xDC0 */
192 uint32 lhl_lp_main_ctl_adr; /* 0xDC4 */
193 uint32 lhl_lp_up_ctl_adr; /* 0xDC8 */
194 uint32 lhl_lp_dn_ctl_adr; /* 0xDCC */
195 uint32 gpio_gctrl_iocfg_p0_p39_adr; /* 0xDD0 */
196 uint32 gpio_gdsctrl_iocfg_p0_p25_p30_p39_adr; /* 0xDD4 */
197 uint32 gpio_gdsctrl_iocfg_p26_p29_adr; /* 0xDD8 */
198 uint32 PAD[PADSZ(0xddc, 0xdf8)]; /* 0xDDC-0xDF8 */
199 uint32 lhl_gpio_din0_adr; /* 0xDFC */
200 uint32 lhl_gpio_din1_adr; /* 0xE00 */
201 uint32 lhl_wkup_status_adr; /* 0xE04 */
202 uint32 lhl_ctl_adr; /* 0xE08 */
203 uint32 lhl_adc_ctl_adr; /* 0xE0C */
204 uint32 lhl_qdxyz_in_dly_adr; /* 0xE10 */
205 uint32 lhl_optctl_adr; /* 0xE14 */
206 uint32 lhl_optct2_adr; /* 0xE18 */
207 uint32 lhl_scanp_cntr_init_val_adr; /* 0xE1C */
208 uint32 lhl_opt_togg_val_adr[6]; /* 0xE20-0xE34 */
209 uint32 lhl_optx_smp_val_adr; /* 0xE38 */
210 uint32 lhl_opty_smp_val_adr; /* 0xE3C */
211 uint32 lhl_optz_smp_val_adr; /* 0xE40 */
212 uint32 lhl_hidoff_keepstate_adr[3]; /* 0xE44-0xE4C */
213 uint32 lhl_bt_slmboot_ctl0_adr[4]; /* 0xE50-0xE5C */
214 uint32 lhl_wl_fw_ctl; /* 0xE60 */
215 uint32 lhl_wl_hw_ctl_adr[2]; /* 0xE64-0xE68 */
216 uint32 lhl_bt_hw_ctl_adr; /* 0xE6C */
217 uint32 lhl_top_pwrseq_en_adr; /* 0xE70 */
218 uint32 lhl_top_pwrdn_ctl_adr; /* 0xE74 */
219 uint32 lhl_top_pwrup_ctl_adr; /* 0xE78 */
220 uint32 lhl_top_pwrseq_ctl_adr; /* 0xE7C */
221 uint32 lhl_top_pwrdn2_ctl_adr; /* 0xE80 */
222 uint32 lhl_top_pwrup2_ctl_adr; /* 0xE84 */
223 uint32 wpt_regon_intrp_cfg_adr; /* 0xE88 */
224 uint32 bt_regon_intrp_cfg_adr; /* 0xE8C */
225 uint32 wl_regon_intrp_cfg_adr; /* 0xE90 */
226 uint32 regon_intrp_st_adr; /* 0xE94 */
227 uint32 regon_intrp_en_adr; /* 0xE98 */
228 uint32 PAD[PADSZ(0xe9c, 0xeb4)]; /* 0xe9c-0xeb4 */
229 uint32 lhl_lp_main_ctl1_adr; /* 0xeb8 */
230 uint32 lhl_lp_up_ctl2_adr; /* 0xebc */
231 uint32 lhl_lp_dn_ctl2_adr; /* 0xec0 */
232 uint32 lhl_lp_up_ctl3_adr; /* 0xec4 */
233 uint32 lhl_lp_dn_ctl3_adr; /* 0xec8 */
234 uint32 PAD[PADSZ(0xecc, 0xed8)]; /* 0xecc-0xed8 */
235 uint32 lhl_lp_main_ctl2_adr; /* 0xedc */
236 uint32 lhl_lp_up_ctl4_adr; /* 0xee0 */
237 uint32 lhl_lp_dn_ctl4_adr; /* 0xee4 */
238 uint32 lhl_lp_up_ctl5_adr; /* 0xee8 */
239 uint32 lhl_lp_dn_ctl5_adr; /* 0xeec */
243 #define GCI_CAP0_REV_MASK 0x000000ff
246 #define GCI_CORE_CAP_0_COREREV_MASK 0xFF
247 #define GCI_CORE_CAP_0_COREREV_SHIFT 0
249 #define GCI_INDIRECT_ADDRESS_REG_REGINDEX_MASK 0x3F
250 #define GCI_INDIRECT_ADDRESS_REG_REGINDEX_SHIFT 0
251 #define GCI_INDIRECT_ADDRESS_REG_GPIOINDEX_MASK 0xF
254 #define WLAN_BANKX_SLEEPPDA_REG_SLEEPPDA_MASK 0xFFFF
256 #define WLAN_BANKX_PKILL_REG_SLEEPPDA_MASK 0x1
259 #define WLAN_BANKXINFO_BANK_SIZE_MASK 0x00FFF000
263 #define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_MASK 0x000000FF
264 #define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_SHIFT 0
266 #define WLAN_MEM_INFO_REG_NUMD11MACBM_MASK 0x0000FF00
269 #define WLAN_MEM_INFO_REG_NUMD11MACUCM_MASK 0x00FF0000
272 #define WLAN_MEM_INFO_REG_NUMD11MACSHM_MASK 0xFF000000