Lines Matching +full:strobe +full:- +full:sel
8 * $Id: sbchipc.h 701163 2017-05-23 22:21:03Z $
12 * Copyright (C) 1999-2017, Broadcom Corporation
33 * <<Broadcom-WL-IPTag/Open:>>
48 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
54 * be assigned their respective chipc-specific address space and connected to the Always On
112 uint32 PAD[3]; /* 0x754-0x75C */
115 uint32 PAD[2]; /* 0x768-0x76C */
116 uint32 extwakereqmask[2]; /* 0x770-0x774 */
117 uint32 PAD[2]; /* 0x778-0x77C */
215 /* gpio - cleared only by power-on-reset */
419 uint32 PAD[2]; /* 0x768-0x76C */
420 uint32 extwakereqmask[2]; /* 0x770-0x774 */
421 uint32 PAD[2]; /* 0x778-0x77C */
423 uint32 PAD[3]; /* 0x784 - 0x78c */
755 #define CC_CAP_MIPSEB 0x00000004 /**< MIPS is in big-endian mode */
771 #define CC_CAP_BKPLN64 0x08000000 /**< 64-bit backplane */
788 /* WL Channel Info to BT via GCI - bits 40 - 47 */
790 /* WL indication of MCHAN enabled/disabled to BT in awdl mode- bit 36 */
794 /* WL indication of SWDIV enabled/disabled to BT - bit 33 */
800 /* WL Strobe to BT */
802 /* bits [51:48] - reserved for wlan TX pwr index */
821 /* ALP clock on pre-PMU chips */
1021 #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */
1022 #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */
1028 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */
1031 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */
1048 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */
1049 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */
1130 /* WL sub-system reset */
1132 /* BT sub-system reset */
1135 /* Both WL and BT sub-system reset */
1307 #define CC_F6_3 0x03 /**< 6-bit fields like */
1313 #define CC_F5_BIAS 5 /**< 5-bit fields get this added */
1401 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */
1404 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */
1409 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */
1454 /* GCI UART Function sel related */
1483 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */
1484 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */
1588 /* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */
2196 /* 43236 chip-specific ChipControl register bits */
2268 #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */
2566 /* 4349 GCI function sel values */
2569 * http://hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/ToplevelArchitecture4349B0#Function_Sel
2647 ((((val) & MUXENAB4349_ ## name ## _MASK) >> MUXENAB4349_ ## name ## _SHIFT) - 1)
2728 /* 43012 resources - End */
3200 #define CC_SR1_43430_SR_ASM_ADDR ((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8)
3373 /* 4335 resources--END */
3375 /* 43012 PMU resources based on pmu_params.xls - Start */
3427 /* 43012 - offset at 5K */
3659 /* 4350 GCI function sel values */
3809 /* 4347 GCI function sel values */
3945 /* 43012 GCI function sel values */
3995 /* 4335 GCI function sel values
4061 /* 4345 GCI function sel values
4085 /* 4349 Group (4349, 4355, 4359) GCI AVS function sel values */
4090 /* 4345 GCI AVS function sel values */
4117 /* GCI GPIO for function sel GCI-0/GCI-1 */
4348 /* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic
4357 ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1)
4361 #define MUXENAB43012_GETIX(val, name) (val - 1)
4424 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
4492 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
4494 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
4561 /* WLAN channel numbers - used from wifi.h */
4573 /* WLAN - number of antenna */
4595 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */