Lines Matching +full:0 +full:x1d000000
5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
48 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
59 uint32 pmucontrol; /* 0x600 */
60 uint32 pmucapabilities; /* 0x604 */
61 uint32 pmustatus; /* 0x608 */
62 uint32 res_state; /* 0x60C */
63 uint32 res_pending; /* 0x610 */
64 uint32 pmutimer; /* 0x614 */
65 uint32 min_res_mask; /* 0x618 */
66 uint32 max_res_mask; /* 0x61C */
67 uint32 res_table_sel; /* 0x620 */
73 uint32 gpiosel; /* 0x638, rev >= 1 */
74 uint32 gpioenable; /* 0x63c, rev >= 1 */
75 uint32 res_req_timer_sel; /* 0x640 */
76 uint32 res_req_timer; /* 0x644 */
77 uint32 res_req_mask; /* 0x648 */
78 uint32 core_cap_ext; /* 0x64C */
79 uint32 chipcontrol_addr; /* 0x650 */
80 uint32 chipcontrol_data; /* 0x654 */
85 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
86 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
87 uint32 retention_ctl; /* 0x670 */
88 uint32 ILPPeriod; /* 0x674 */
90 uint32 retention_grpidx; /* 0x680 */
91 uint32 retention_grpctl; /* 0x684 */
92 uint32 mac_res_req_timer; /* 0x688 */
93 uint32 mac_res_req_mask; /* 0x68c */
95 uint32 pmucontrol_ext; /* 0x6d8 */
96 uint32 slowclkperiod; /* 0x6dc */
97 uint32 pmu_statstimer_addr; /* 0x6e0 */
98 uint32 pmu_statstimer_ctrl; /* 0x6e4 */
99 uint32 pmu_statstimer_N; /* 0x6e8 */
101 uint32 mac_res_req_timer1; /* 0x6f0 */
102 uint32 mac_res_req_mask1; /* 0x6f4 */
104 uint32 pmuintmask0; /* 0x700 */
105 uint32 pmuintmask1; /* 0x704 */
107 uint32 pmuintstatus; /* 0x740 */
108 uint32 extwakeupstatus; /* 0x744 */
109 uint32 watchdog_res_mask; /* 0x748 */
110 uint32 PAD[1]; /* 0x74C */
111 uint32 swscratch; /* 0x750 */
112 uint32 PAD[3]; /* 0x754-0x75C */
113 uint32 extwakemask0; /* 0x760 */
114 uint32 extwakemask1; /* 0x764 */
115 uint32 PAD[2]; /* 0x768-0x76C */
116 uint32 extwakereqmask[2]; /* 0x770-0x774 */
117 uint32 PAD[2]; /* 0x778-0x77C */
118 uint32 pmuintctrl0; /* 0x780 */
119 uint32 pmuintctrl1; /* 0x784 */
121 uint32 extwakectrl[2]; /* 0x790 */
123 uint32 fis_ctrl_status; /* 0x7b4 */
124 uint32 fis_min_res_mask; /* 0x7b8 */
126 uint32 PrecisionTmrCtrlStatus; /* 0x7c0 */
175 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */
180 uint32 chipid; /* 0x0 */
186 uint32 otpstatus; /* 0x10, corerev >= 10 */
192 uint32 intstatus; /* 0x20 */
196 uint32 chipcontrol; /* 0x28, rev >= 11 */
197 uint32 chipstatus; /* 0x2c, rev >= 11 */
200 uint32 jtagcmd; /* 0x30, rev >= 10 */
206 uint32 flashcontrol; /* 0x40 */
212 uint32 broadcastaddress; /* 0x50 */
216 uint32 gpiopullup; /* 0x58, corerev >= 20 */
217 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
218 uint32 gpioin; /* 0x60 */
219 uint32 gpioout; /* 0x64 */
220 uint32 gpioouten; /* 0x68 */
221 uint32 gpiocontrol; /* 0x6C */
222 uint32 gpiointpolarity; /* 0x70 */
223 uint32 gpiointmask; /* 0x74 */
230 uint32 watchdog; /* 0x80 */
236 uint32 gpiotimerval; /* 0x88 */
240 uint32 clockcontrol_n; /* 0x90 */
247 uint32 capabilities_ext; /* 0xac */
250 uint32 pll_on_delay; /* 0xb0 */
256 uint32 system_clk_ctl; /* 0xc0 */
261 uint32 bp_addrlow; /* 0xd0 */
275 uint32 fabid; /* 0xf8 */
278 uint32 eromptr; /* 0xfc */
281 uint32 pcmcia_config; /* 0x100 */
293 uint32 SECI_config; /* 0x130 SECI configuration */
301 uint32 sromcontrol; /* 0x190 */
304 uint32 PAD[1]; /* 0x19C */
306 uint32 nflashctrl; /* 0x1a0 */
311 uint32 nflashwaitcnt0; /* 0x1b4 */
314 uint32 seci_uart_data; /* 0x1C0 */
323 uint32 clk_ctl_st; /* 0x1e0 */
325 uint32 powerctl; /* 0x1e8 */
329 uint8 uart0data; /* 0x300 */
339 uint8 uart1data; /* 0x400 */
346 uint8 uart1scratch; /* 0x407 */
348 uint32 sr_memrw_addr; /* 0x4d0 */
349 uint32 sr_memrw_data; /* 0x4d4 */
353 uint32 sr_capability; /* 0x500 */
354 uint32 sr_control0; /* 0x504 */
355 uint32 sr_control1; /* 0x508 */
356 uint32 gpio_control; /* 0x50C */
359 uint32 sr1_control0; /* 0x584 */
360 uint32 sr1_control1; /* 0x588 */
366 uint32 pmucontrol; /* 0x600 */
380 uint32 gpiosel; /* 0x638, rev >= 1 */
381 uint32 gpioenable; /* 0x63c, rev >= 1 */
385 uint32 core_cap_ext; /* 0x64c */
386 uint32 chipcontrol_addr; /* 0x650 */
387 uint32 chipcontrol_data; /* 0x654 */
392 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
393 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
394 uint32 retention_ctl; /* 0x670 */
395 uint32 ILPPeriod; /* 0x674 */
397 uint32 retention_grpidx; /* 0x680 */
398 uint32 retention_grpctl; /* 0x684 */
399 uint32 mac_res_req_timer; /* 0x688 */
400 uint32 mac_res_req_mask; /* 0x68c */
402 uint32 pmucontrol_ext; /* 0x6d8 */
403 uint32 slowclkperiod; /* 0x6dc */
404 uint32 pmu_statstimer_addr; /* 0x6e0 */
405 uint32 pmu_statstimer_ctrl; /* 0x6e4 */
406 uint32 pmu_statstimer_N; /* 0x6e8 */
408 uint32 mac_res_req_timer1; /* 0x6f0 */
409 uint32 mac_res_req_mask1; /* 0x6f4 */
411 uint32 pmuintmask0; /* 0x700 */
412 uint32 pmuintmask1; /* 0x704 */
414 uint32 pmuintstatus; /* 0x740 */
415 uint32 extwakeupstatus; /* 0x744 */
417 uint32 extwakemask0; /* 0x760 */
418 uint32 extwakemask1; /* 0x764 */
419 uint32 PAD[2]; /* 0x768-0x76C */
420 uint32 extwakereqmask[2]; /* 0x770-0x774 */
421 uint32 PAD[2]; /* 0x778-0x77C */
422 uint32 pmuintctrl0; /* 0x780 */
423 uint32 PAD[3]; /* 0x784 - 0x78c */
424 uint32 extwakectrl[1]; /* 0x790 */
426 uint32 fis_ctrl_status; /* 0x7b4 */
427 uint32 fis_min_res_mask; /* 0x7b8 */
429 uint16 sromotp[512]; /* 0x800 */
432 uint32 nand_revision; /* 0xC00 */
494 uint32 gci_corecaps0; /* GCI starting at 0xC00 */
498 uint32 gci_corestat; /* 0xC10 */
499 uint32 gci_intstat; /* 0xC14 */
500 uint32 gci_intmask; /* 0xC18 */
501 uint32 gci_wakemask; /* 0xC1C */
502 uint32 gci_levelintstat; /* 0xC20 */
503 uint32 gci_eventintstat; /* 0xC24 */
505 uint32 gci_indirect_addr; /* 0xC40 */
506 uint32 gci_gpioctl; /* 0xC44 */
508 uint32 gci_gpiomask; /* 0xC4C */
509 uint32 gci_eventsummary; /* 0xC50 */
510 uint32 gci_miscctl; /* 0xC54 */
516 uint32 gci_control_0; /* 0xD70 */
517 uint32 gci_control_1; /* 0xD74 */
518 uint32 gci_intpolreg; /* 0xD78 */
519 uint32 gci_levelintmask; /* 0xD7C */
520 uint32 gci_eventintmask; /* 0xD80 */
522 uint32 gci_inbandlevelintmask; /* 0xD90 */
523 uint32 gci_inbandeventintmask; /* 0xD94 */
525 uint32 gci_seciauxtx; /* 0xDA0 */
526 uint32 gci_seciauxrx; /* 0xDA4 */
527 uint32 gci_secitx_datatag; /* 0xDA8 */
528 uint32 gci_secirx_datatag; /* 0xDAC */
529 uint32 gci_secitx_datamask; /* 0xDB0 */
530 uint32 gci_seciusef0tx_reg; /* 0xDB4 */
531 uint32 gci_secif0tx_offset; /* 0xDB8 */
532 uint32 gci_secif0rx_offset; /* 0xDBC */
533 uint32 gci_secif1tx_offset; /* 0xDC0 */
534 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */
535 uint32 gci_rxfifoctrl; /* 0xDC8 */
549 uint32 gci_chipctrl; /* 0xE00 */
550 uint32 gci_chipsts; /* 0xE04 */
551 uint32 gci_gpioout; /* 0xE08 */
552 uint32 gci_gpioout_read; /* 0xE0C */
553 uint32 gci_mpwaketx; /* 0xE10 */
554 uint32 gci_mpwakedetect; /* 0xE14 */
555 uint32 gci_seciin_ctrl; /* 0xE18 */
556 uint32 gci_seciout_ctrl; /* 0xE1C */
557 uint32 gci_seciin_auxfifo_en; /* 0xE20 */
558 uint32 gci_seciout_txen_txbr; /* 0xE24 */
559 uint32 gci_seciin_rxbrstatus; /* 0xE28 */
560 uint32 gci_seciin_rxerrstatus; /* 0xE2C */
561 uint32 gci_seciin_fcstatus; /* 0xE30 */
562 uint32 gci_seciout_txstatus; /* 0xE34 */
563 uint32 gci_seciout_txbrstatus; /* 0xE38 */
568 #define CC_CHIPID 0
570 #define CC_CHIPST 0x2c
571 #define CC_EROMPTR 0xfc
573 #define CC_OTPST 0x10
574 #define CC_INTSTATUS 0x20
575 #define CC_INTMASK 0x24
576 #define CC_JTAGCMD 0x30
577 #define CC_JTAGIR 0x34
578 #define CC_JTAGDR 0x38
579 #define CC_JTAGCTRL 0x3c
580 #define CC_GPIOPU 0x58
581 #define CC_GPIOPD 0x5c
582 #define CC_GPIOIN 0x60
583 #define CC_GPIOOUT 0x64
584 #define CC_GPIOOUTEN 0x68
585 #define CC_GPIOCTRL 0x6c
586 #define CC_GPIOPOL 0x70
587 #define CC_GPIOINTM 0x74
588 #define CC_GPIOEVENT 0x78
589 #define CC_GPIOEVENTMASK 0x7c
590 #define CC_WATCHDOG 0x80
591 #define CC_GPIOEVENTPOL 0x84
592 #define CC_CLKC_N 0x90
593 #define CC_CLKC_M0 0x94
594 #define CC_CLKC_M1 0x98
595 #define CC_CLKC_M2 0x9c
596 #define CC_CLKC_M3 0xa0
597 #define CC_CLKDIV 0xa4
598 #define CC_CAP_EXT 0xac
599 #define CC_SYS_CLK_CTL 0xc0
600 #define CC_CLKDIV2 0xf0
602 #define PMU_CTL 0x600
603 #define PMU_CAP 0x604
604 #define PMU_ST 0x608
605 #define PMU_RES_STATE 0x60c
606 #define PMU_RES_PENDING 0x610
607 #define PMU_TIMER 0x614
608 #define PMU_MIN_RES_MASK 0x618
609 #define PMU_MAX_RES_MASK 0x61c
610 #define CC_CHIPCTL_ADDR 0x650
611 #define CC_CHIPCTL_DATA 0x654
612 #define PMU_REG_CONTROL_ADDR 0x658
613 #define PMU_REG_CONTROL_DATA 0x65C
614 #define PMU_PLL_CONTROL_ADDR 0x660
615 #define PMU_PLL_CONTROL_DATA 0x664
617 #define CC_SROM_CTRL 0x190
618 #define CC_SROM_ADDRESS 0x194u
619 #define CC_SROM_DATA 0x198u
621 #define CC_SROM_OTP 0xa000 /* SROM/OTP address space */
623 #define CC_SROM_OTP 0x0800
625 #define CC_GCI_INDIRECT_ADDR_REG 0xC40
626 #define CC_GCI_CHIP_CTRL_REG 0xE00
629 #define CC_SWD_CTRL 0x380
630 #define CC_SWD_REQACK 0x384
631 #define CC_SWD_DATA 0x388
632 #define GPIO_SEL_0 0x00001111
633 #define GPIO_SEL_1 0x11110000
634 #define GPIO_SEL_8 0x00001111
635 #define GPIO_SEL_9 0x11110000
637 #define CHIPCTRLREG0 0x0
638 #define CHIPCTRLREG1 0x1
639 #define CHIPCTRLREG2 0x2
640 #define CHIPCTRLREG3 0x3
641 #define CHIPCTRLREG4 0x4
642 #define CHIPCTRLREG5 0x5
643 #define CHIPCTRLREG6 0x6
644 #define REGCTRLREG4 0x4
645 #define REGCTRLREG5 0x5
646 #define REGCTRLREG6 0x6
647 #define MINRESMASKREG 0x618
648 #define MAXRESMASKREG 0x61c
649 #define CHIPCTRLADDR 0x650
650 #define CHIPCTRLDATA 0x654
651 #define RSRCTABLEADDR 0x620
652 #define PMU_RES_DEP_MASK 0x624
653 #define RSRCUPDWNTIME 0x628
654 #define PMUREG_RESREQ_MASK 0x68c
655 #define PMUREG_RESREQ_TIMER 0x688
656 #define PMUREG_RESREQ_MASK1 0x6f4
657 #define PMUREG_RESREQ_TIMER1 0x6f0
658 #define EXT_LPO_AVAIL 0x100
659 #define LPO_SEL (1 << 0)
660 #define CC_EXT_LPO_PU 0x200000
661 #define GC_EXT_LPO_PU 0x2
662 #define CC_INT_LPO_PU 0x100000
663 #define GC_INT_LPO_PU 0x1
664 #define EXT_LPO_SEL 0x8
665 #define INT_LPO_SEL 0x4
667 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000
669 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000
682 #define LHL_LPO1_SEL 0
683 #define LHL_LPO2_SEL 0x1
684 #define LHL_32k_SEL 0x2
685 #define LHL_EXT_SEL 0x3
687 #define EXTLPO_BUF_PD 0x40
688 #define LPO1_PD_EN 0x1
689 #define LPO1_PD_SEL 0x6
690 #define LPO1_PD_SEL_VAL 0x4
691 #define LPO2_PD_EN 0x8
692 #define LPO2_PD_SEL 0x30
693 #define LPO2_PD_SEL_VAL 0x20
694 #define OSC_32k_PD 0x80
696 #define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3
698 #define LHL_LPO_AUTO 0x0
699 #define LHL_LPO1_ENAB 0x1
700 #define LHL_LPO2_ENAB 0x2
701 #define LHL_OSC_32k_ENAB 0x3
702 #define LHL_EXT_LPO_ENAB 0x4
703 #define RADIO_LPO_ENAB 0x5
705 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4
706 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8
707 #define LHL_CLK_DET_CNT 0xF0
711 #define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000
712 #define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600
717 #define SUBCORE_POWER_ON 0x0001
718 #define PHY_POWER_ON 0x0010
719 #define VDDM_POWER_ON 0x0100
720 #define MEMLPLDO_POWER_ON 0x1000
721 #define SUBCORE_POWER_ON_CHK 0x00040000
722 #define PHY_POWER_ON_CHK 0x00080000
723 #define VDDM_POWER_ON_CHK 0x00100000
724 #define MEMLPLDO_POWER_ON_CHK 0x00200000
729 #define CC_NAND_REVISION 0xC00
730 #define CC_NAND_CMD_START 0xC04
731 #define CC_NAND_CMD_ADDR 0xC0C
732 #define CC_NAND_SPARE_RD_0 0xC20
733 #define CC_NAND_SPARE_RD_4 0xC24
734 #define CC_NAND_SPARE_RD_8 0xC28
735 #define CC_NAND_SPARE_RD_C 0xC2C
736 #define CC_NAND_CONFIG 0xC48
737 #define CC_NAND_DEVID 0xC60
738 #define CC_NAND_DEVID_EXT 0xC64
739 #define CC_NAND_INTFC_STATUS 0xC6C
743 #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */
744 #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */
746 #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */
748 #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */
750 #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */
754 #define CC_CAP_UARTS_MASK 0x00000003 /**< Number of UARTs */
755 #define CC_CAP_MIPSEB 0x00000004 /**< MIPS is in big-endian mode */
756 #define CC_CAP_UCLKSEL 0x00000018 /**< UARTs clock select */
757 #define CC_CAP_UINTCLK 0x00000008 /**< UARTs are driven by internal divided clock */
758 #define CC_CAP_UARTGPIO 0x00000020 /**< UARTs own GPIOs 15:12 */
759 #define CC_CAP_EXTBUS_MASK 0x000000c0 /**< External bus mask */
760 #define CC_CAP_EXTBUS_NONE 0x00000000 /**< No ExtBus present */
761 #define CC_CAP_EXTBUS_FULL 0x00000040 /**< ExtBus: PCMCIA, IDE & Prog */
762 #define CC_CAP_EXTBUS_PROG 0x00000080 /**< ExtBus: ProgIf only */
763 #define CC_CAP_FLASH_MASK 0x00000700 /**< Type of flash */
764 #define CC_CAP_PLL_MASK 0x00038000 /**< Type of PLL */
765 #define CC_CAP_PWR_CTL 0x00040000 /**< Power control */
766 #define CC_CAP_OTPSIZE 0x00380000 /**< OTP Size (0 = none) */
769 #define CC_CAP_JTAGP 0x00400000 /**< JTAG Master Present */
770 #define CC_CAP_ROM 0x00800000 /**< Internal boot rom active */
771 #define CC_CAP_BKPLN64 0x08000000 /**< 64-bit backplane */
772 #define CC_CAP_PMU 0x10000000 /**< PMU Present, rev >= 20 */
773 #define CC_CAP_ECI 0x20000000 /**< ECI Present, rev >= 21 */
774 #define CC_CAP_SROM 0x40000000 /**< Srom Present, rev >= 32 */
775 #define CC_CAP_NFLASH 0x80000000 /**< Nand flash present, rev >= 35 */
777 #define CC_CAP2_SECI 0x00000001 /**< SECI Present, rev >= 36 */
778 #define CC_CAP2_GSIO 0x00000002 /**< GSIO (spi/i2c) present, rev >= 37 */
781 #define CC_CAP_EXT_SECI_PRESENT 0x00000001 /**< SECI present */
782 #define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /**< GSIO present */
783 #define CC_CAP_EXT_GCI_PRESENT 0x00000004 /**< GCI present */
784 #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /**< UART present */
785 #define CC_CAP_EXT_AOB_PRESENT 0x00000040 /**< AOB present */
786 #define CC_CAP_EXT_SWD_PRESENT 0x00000400 /**< SWD present */
789 #define GCI_WL_CHN_INFO_MASK (0xFF00)
791 #define GCI_WL_MCHAN_BIT_MASK (0x0010)
795 #define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002)
796 #define GCI_SWDIV_ANT_VALID_SHIFT 0x1
797 #define GCI_SWDIV_ANT_VALID_DISABLE 0x0
801 #define GCI_WL_STROBE_BIT_MASK (0x0020)
805 #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT)
806 #define GCI_WL_ANT_BIT_MASK (0x00c0)
809 #define PLL_NONE 0x00000000
810 #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */
811 #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */
812 #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */
813 #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */
814 #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */
815 #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */
816 #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */
852 #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */
853 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */
854 #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */
855 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */
862 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */
865 #define OTPS_OL_MASK 0x000000ff
866 #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */
867 #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */
868 #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */
869 #define OTPS_OL_GU 0x00000008 /**< general use region is locked */
870 #define OTPS_GUP_MASK 0x00000f00
872 #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */
873 #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */
874 #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */
875 #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */
876 #define OTPS_READY 0x00001000
878 #define OTPS_RV_MASK 0x0fff0000
879 #define OTPS_PROGOK 0x40000000
882 #define OTPC_PROGSEL 0x00000001
883 #define OTPC_PCOUNT_MASK 0x0000000e
885 #define OTPC_VSEL_MASK 0x000000f0
887 #define OTPC_TMM_MASK 0x00000700
889 #define OTPC_ODM 0x00000800
890 #define OTPC_PROGEN 0x80000000
893 #define OTPC_40NM_PROGSEL_SHIFT 0
895 #define OTPC_40NM_PCOUNT_WR 0xA
896 #define OTPC_40NM_PCOUNT_V1X 0xB
898 #define OTPC_40NM_REGCSEL_DEF 0x4
904 #define OTPC_40NM_VSEL_WR 0xA
905 #define OTPC_40NM_VSEL_V1X 0xA
906 #define OTPC_40NM_VSEL_R1X 0x5
909 #define OTPC1_CPCSEL_SHIFT 0
912 #define OTPC1_TM_WR 0x84
913 #define OTPC1_TM_V1X 0x84
914 #define OTPC1_TM_R1X 0x4
915 #define OTPC1_CLK_EN_MASK 0x00020000
916 #define OTPC1_CLK_DIV_MASK 0x00FC0000
919 #define OTPP_COL_MASK 0x000000ff
920 #define OTPP_COL_SHIFT 0
921 #define OTPP_ROW_MASK 0x0000ff00
922 #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */
924 #define OTPP_OC_MASK 0x0f000000
926 #define OTPP_READERR 0x10000000
927 #define OTPP_VALUE_MASK 0x20000000
929 #define OTPP_START_BUSY 0x80000000
930 #define OTPP_READ 0x40000000 /* HND OTP */
933 #define OTPL_HWRGN_OFF_MASK 0x00000FFF
934 #define OTPL_HWRGN_OFF_SHIFT 0
935 #define OTPL_WRAP_REVID_MASK 0x00F80000
937 #define OTPL_WRAP_TYPE_MASK 0x00070000
939 #define OTPL_WRAP_TYPE_65NM 0
942 #define OTPL_ROW_SIZE_MASK 0x0000F000
946 #define OTP_CISFORMAT_NEW 0x80000000
949 #define OTPPOC_READ 0
960 #define OTPPOC_READ_40NM 0
978 #define OTPPOC_READ_28NM 0
1009 #define OTPP_OC_MASK_28NM 0x0f800000
1011 #define OTPC_PROGEN_28NM 0x8
1012 #define OTPC_DBLERRCLR 0x20
1013 #define OTPC_CLK_EN_MASK 0x00000040
1014 #define OTPC_CLK_DIV_MASK 0x00000F80
1017 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF
1025 #define JCMD_START 0x80000000
1026 #define JCMD_BUSY 0x80000000
1027 #define JCMD_STATE_MASK 0x60000000
1028 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */
1029 #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */
1030 #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */
1031 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */
1032 #define JCMD0_ACC_MASK 0x0000f000
1033 #define JCMD0_ACC_IRDR 0x00000000
1034 #define JCMD0_ACC_DR 0x00001000
1035 #define JCMD0_ACC_IR 0x00002000
1036 #define JCMD0_ACC_RESET 0x00003000
1037 #define JCMD0_ACC_IRPDR 0x00004000
1038 #define JCMD0_ACC_PDR 0x00005000
1039 #define JCMD0_IRW_MASK 0x00000f00
1040 #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */
1041 #define JCMD_ACC_IRDR 0x00000000
1042 #define JCMD_ACC_DR 0x00010000
1043 #define JCMD_ACC_IR 0x00020000
1044 #define JCMD_ACC_RESET 0x00030000
1045 #define JCMD_ACC_IRPDR 0x00040000
1046 #define JCMD_ACC_PDR 0x00050000
1047 #define JCMD_ACC_PIR 0x00060000
1048 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */
1049 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */
1050 #define JCMD_IRW_MASK 0x00001f00
1052 #define JCMD_DRW_MASK 0x0000003f
1058 #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */
1067 #define CLKD_SFLASH 0x1f000000
1069 #define CLKD_OTP 0x000f0000
1071 #define CLKD_JTAG 0x00000f00
1073 #define CLKD_UART 0x000000ff
1075 #define CLKD2_SROM 0x00000007
1076 #define CLKD2_SROMDIV_32 0
1084 #define CLKD2_SWD 0xf8000000
1088 #define CI_GPIO 0x00000001 /**< gpio intr */
1089 #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */
1090 #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */
1091 #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */
1092 #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */
1093 #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */
1094 #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */
1095 #define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */
1096 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */
1099 #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */
1100 #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */
1101 #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */
1102 #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */
1103 #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */
1104 #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled,
1105 * 0: LPO is enabled
1107 #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock,
1108 * 0: power logic control
1110 #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors
1113 #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't
1116 #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */
1117 #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */
1121 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */
1122 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */
1123 #define SYCC_FP 0x00000004 /**< ForcePLLOn */
1124 #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */
1125 #define SYCC_HR 0x00000010 /**< Force HT */
1126 #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */
1131 #define WD_SSRESET_PCIE_F0_EN 0x10000000
1133 #define WD_SSRESET_PCIE_F1_EN 0x20000000
1134 #define WD_SSRESET_PCIE_F2_EN 0x40000000
1136 #define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000
1137 #define WD_COUNTER_MASK 0x0fffffff
1143 #define BPIA_BYTEEN 0x0000000f
1144 #define BPIA_SZ1 0x00000001
1145 #define BPIA_SZ2 0x00000003
1146 #define BPIA_SZ4 0x00000007
1147 #define BPIA_SZ8 0x0000000f
1148 #define BPIA_WRITE 0x00000100
1149 #define BPIA_START 0x00000200
1150 #define BPIA_BUSY 0x00000200
1151 #define BPIA_ERROR 0x00000400
1154 #define CF_EN 0x00000001 /**< enable */
1155 #define CF_EM_MASK 0x0000000e /**< mode */
1157 #define CF_EM_FLASH 0 /**< flash/asynchronous mode */
1160 #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */
1161 #define CF_BS 0x00000020 /**< byteswap */
1162 #define CF_CD_MASK 0x000000c0 /**< clock divider */
1164 #define CF_CD_DIV2 0x00000000 /**< backplane/2 */
1165 #define CF_CD_DIV3 0x00000040 /**< backplane/3 */
1166 #define CF_CD_DIV4 0x00000080 /**< backplane/4 */
1167 #define CF_CE 0x00000100 /**< clock enable */
1168 #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */
1171 #define PM_W0_MASK 0x0000003f /**< waitcount0 */
1172 #define PM_W1_MASK 0x00001f00 /**< waitcount1 */
1174 #define PM_W2_MASK 0x001f0000 /**< waitcount2 */
1176 #define PM_W3_MASK 0x1f000000 /**< waitcount3 */
1180 #define PA_W0_MASK 0x0000003f /**< waitcount0 */
1181 #define PA_W1_MASK 0x00001f00 /**< waitcount1 */
1183 #define PA_W2_MASK 0x001f0000 /**< waitcount2 */
1185 #define PA_W3_MASK 0x1f000000 /**< waitcount3 */
1189 #define PI_W0_MASK 0x0000003f /**< waitcount0 */
1190 #define PI_W1_MASK 0x00001f00 /**< waitcount1 */
1192 #define PI_W2_MASK 0x001f0000 /**< waitcount2 */
1194 #define PI_W3_MASK 0x1f000000 /**< waitcount3 */
1198 #define PW_W0_MASK 0x0000001f /**< waitcount0 */
1199 #define PW_W1_MASK 0x00001f00 /**< waitcount1 */
1201 #define PW_W2_MASK 0x001f0000 /**< waitcount2 */
1203 #define PW_W3_MASK 0x1f000000 /**< waitcount3 */
1206 #define PW_W0 0x0000000c
1207 #define PW_W1 0x00000a00
1208 #define PW_W2 0x00020000
1209 #define PW_W3 0x01000000
1212 #define FW_W0_MASK 0x0000003f /**< waitcount0 */
1213 #define FW_W1_MASK 0x00001f00 /**< waitcount1 */
1215 #define FW_W2_MASK 0x001f0000 /**< waitcount2 */
1217 #define FW_W3_MASK 0x1f000000 /**< waitcount3 */
1221 #define SRC_START 0x80000000
1222 #define SRC_BUSY 0x80000000
1223 #define SRC_OPCODE 0x60000000
1224 #define SRC_OP_READ 0x00000000
1225 #define SRC_OP_WRITE 0x20000000
1226 #define SRC_OP_WRDIS 0x40000000
1227 #define SRC_OP_WREN 0x60000000
1228 #define SRC_OTPSEL 0x00000010
1229 #define SRC_OTPPRESENT 0x00000020
1230 #define SRC_LOCK 0x00000008
1231 #define SRC_SIZE_MASK 0x00000006
1232 #define SRC_SIZE_1K 0x00000000
1233 #define SRC_SIZE_4K 0x00000002
1234 #define SRC_SIZE_16K 0x00000004
1236 #define SRC_PRESENT 0x00000001
1239 #define PCTL_ILP_DIV_MASK 0xffff0000
1241 #define PCTL_LQ_REQ_EN 0x00008000
1242 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */
1243 #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */
1244 #define PCTL_HT_REQ_EN 0x00000100
1245 #define PCTL_ALP_REQ_EN 0x00000080
1246 #define PCTL_XTALFREQ_MASK 0x0000007c
1248 #define PCTL_ILP_DIV_EN 0x00000002
1249 #define PCTL_LPO_SEL 0x00000001
1252 #define PCTL_EXT_USE_LHL_TIMER 0x00000010
1253 #define PCTL_EXT_FASTLPO_ENAB 0x00000080
1254 #define PCTL_EXT_FASTLPO_SWENAB 0x00000200
1255 #define PCTL_EXT_FASTSEQ_ENAB 0x00001000
1256 #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000 /**< rev33 for FLL1M */
1258 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77
1261 #define PMU_RCTL_CLK_DIV_SHIFT 0
1273 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0
1282 #define CSTRETCH_HT 0xffff0000
1283 #define CSTRETCH_ALP 0x0000ffff
1284 #define CSTRETCH_REDUCE_8 0x00080008
1290 #define CN_N1_MASK 0x3f /**< n1 control */
1291 #define CN_N2_MASK 0x3f00 /**< n2 control */
1293 #define CN_PLLC_MASK 0xf0000 /**< pll control */
1297 #define CC_M1_MASK 0x3f /**< m1 control */
1298 #define CC_M2_MASK 0x3f00 /**< m2 control */
1300 #define CC_M3_MASK 0x3f0000 /**< m3 control */
1302 #define CC_MC_MASK 0x1f000000 /**< mux control */
1306 #define CC_F6_2 0x02 /**< A factor of 2 in */
1307 #define CC_F6_3 0x03 /**< 6-bit fields like */
1308 #define CC_F6_4 0x05 /**< N1, M1 or M3 */
1309 #define CC_F6_5 0x09
1310 #define CC_F6_6 0x11
1311 #define CC_F6_7 0x21
1315 #define CC_MC_BYPASS 0x08
1316 #define CC_MC_M1 0x04
1317 #define CC_MC_M1M2 0x02
1318 #define CC_MC_M1M2M3 0x01
1319 #define CC_MC_M1M3 0x11
1331 #define CC_T6_M0 120000000 /**< sb clock for m = 0 */
1340 #define CLKC_5350_N 0x0311
1341 #define CLKC_5350_M 0x04020009
1344 #define FLASH_NONE 0x000 /**< No flash */
1345 #define SFLASH_ST 0x100 /**< ST serial flash */
1346 #define SFLASH_AT 0x200 /**< Atmel serial flash */
1347 #define NFLASH 0x300
1348 #define PFLASH 0x700 /**< Parallel flash */
1349 #define QSPIFLASH_ST 0x800
1350 #define QSPIFLASH_AT 0x900
1353 #define CC_CFG_EN 0x0001 /**< Enable */
1354 #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */
1355 #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */
1356 #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */
1357 #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */
1358 #define CC_CFG_EM_IDE 0x0006 /**< IDE */
1359 #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */
1360 #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */
1361 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */
1362 #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */
1363 #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */
1366 #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */
1367 #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */
1368 #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */
1369 #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */
1370 #define CC_EB_IDE 0x1a800000 /**< IDE memory base */
1371 #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */
1372 #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */
1373 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */
1374 #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */
1377 #define SFLASH_OPCODE 0x000000ff
1378 #define SFLASH_ACTION 0x00000700
1379 #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */
1380 #define SFLASH_START 0x80000000
1384 #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */
1385 #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */
1386 #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */
1387 #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */
1388 #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */
1389 #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */
1390 #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */
1393 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */
1394 #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */
1395 #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */
1396 #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */
1397 #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */
1398 #define SFLASH_ST_PP 0x0302 /**< Page Program */
1399 #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */
1400 #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */
1401 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */
1402 #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */
1403 #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */
1404 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */
1406 #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */
1407 #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */
1408 #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */
1409 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */
1411 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */
1412 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */
1415 #define SFLASH_ST_WIP 0x01 /**< Write In Progress */
1416 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */
1417 #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */
1419 #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */
1422 #define SFLASH_AT_READ 0x07e8
1423 #define SFLASH_AT_PAGE_READ 0x07d2
1426 #define SFLASH_AT_STATUS 0x01d7
1427 #define SFLASH_AT_BUF1_WRITE 0x0384
1428 #define SFLASH_AT_BUF2_WRITE 0x0387
1429 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
1430 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
1431 #define SFLASH_AT_BUF1_PROGRAM 0x0288
1432 #define SFLASH_AT_BUF2_PROGRAM 0x0289
1433 #define SFLASH_AT_PAGE_ERASE 0x0281
1434 #define SFLASH_AT_BLOCK_ERASE 0x0250
1435 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
1436 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
1437 #define SFLASH_AT_BUF1_LOAD 0x0253
1438 #define SFLASH_AT_BUF2_LOAD 0x0255
1439 #define SFLASH_AT_BUF1_COMPARE 0x0260
1440 #define SFLASH_AT_BUF2_COMPARE 0x0261
1441 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
1442 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
1445 #define SFLASH_AT_READY 0x80
1446 #define SFLASH_AT_MISMATCH 0x40
1447 #define SFLASH_AT_ID_MASK 0x38
1451 #define GSIO_START 0x80000000
1455 #define MUXENAB_GCI_UART_MASK (0x00000f00)
1457 #define MUXENAB_GCI_UART_FNSEL_MASK (0x00003000)
1466 #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */
1467 #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */
1468 #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */
1469 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */
1478 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */
1479 #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */
1480 #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */
1481 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */
1482 #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */
1483 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */
1484 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */
1485 #define UART_LSR_BREAK 0x10 /**< Break interrupt */
1486 #define UART_LSR_FRAMING 0x08 /**< Framing error */
1487 #define UART_LSR_PARITY 0x04 /**< Parity error */
1488 #define UART_LSR_OVERRUN 0x02 /**< Overrun error */
1489 #define UART_LSR_RXRDY 0x01 /**< Receiver ready */
1493 #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */
1494 #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */
1495 #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */
1496 #define UART_IIR_NOINT 0x1 /**< No interrupt pending */
1497 #define UART_IIR_THRE 0x2 /**< THR empty */
1498 #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */
1499 #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */
1500 #define UART_IIR_CHAR_TIME 0xc /**< Character time */
1510 #define PST_SLOW_WR_PENDING 0x0400
1511 #define PST_EXTLPOAVAIL 0x0100
1512 #define PST_WDRESET 0x0080
1513 #define PST_INTPEND 0x0040
1514 #define PST_SBCLKST 0x0030
1515 #define PST_SBCLKST_ILP 0x0010
1516 #define PST_SBCLKST_ALP 0x0020
1517 #define PST_SBCLKST_HT 0x0030
1518 #define PST_ALPAVAIL 0x0008
1519 #define PST_HTAVAIL 0x0004
1520 #define PST_RESINIT 0x0003
1521 #define PST_ILPFASTLPO 0x00010000
1524 #define PCAP_REV_MASK 0x000000ff
1525 #define PCAP_RC_MASK 0x00001f00
1527 #define PCAP_TC_MASK 0x0001e000
1529 #define PCAP_PC_MASK 0x001e0000
1531 #define PCAP_VC_MASK 0x01e00000
1533 #define PCAP_CC_MASK 0x1e000000
1535 #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */
1537 #define PCAP5_VC_MASK 0x07c00000
1539 #define PCAP5_CC_MASK 0xf8000000
1544 #define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT)
1546 #define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT)
1549 #define PMU_ST_SRC_SHIFT (0) /* stat timer source number */
1550 #define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT)
1552 #define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT)
1554 #define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT)
1556 #define PMU_ST_DISAB 0
1558 #define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT)
1560 #define PMU_ST_INT_DISAB 0
1563 #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000
1567 #define PRRT_TIME_MASK 0x03ff
1568 #define PRRT_INTEN 0x0400
1573 #define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */
1574 #define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */
1575 #define PRRT_ALP_REQ 0x1000
1576 #define PRRT_HT_REQ 0x2000
1577 #define PRRT_HQ_REQ 0x4000
1580 #define PMU_INTC_ALP_REQ 0x1
1581 #define PMU_INTC_HT_REQ 0x2
1582 #define PMU_INTC_HQ_REQ 0x4
1584 /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */
1599 #define PMU_CHIPCTL0 0
1601 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0)
1602 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0)
1603 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6)
1604 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6)
1605 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12)
1606 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12)
1607 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15)
1608 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15)
1614 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
1623 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000
1624 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010
1626 #define PMU_CC1_IF_TYPE_MASK 0x00000030
1627 #define PMU_CC1_IF_TYPE_RMII 0x00000000
1628 #define PMU_CC1_IF_TYPE_MII 0x00000010
1629 #define PMU_CC1_IF_TYPE_RGMII 0x00000020
1631 #define PMU_CC1_SW_TYPE_MASK 0x000000c0
1632 #define PMU_CC1_SW_TYPE_EPHY 0x00000000
1633 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
1634 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
1635 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0
1637 #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080
1638 #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000
1640 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u
1641 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u
1645 #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000
1657 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3 << 26)
1658 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3 << 26)
1659 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0 << 28)
1660 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3 << 28)
1668 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3F << 0)
1669 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3F << 0)
1670 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15)
1671 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15)
1672 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3F << 6)
1673 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3F << 6)
1674 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21)
1675 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21)
1676 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2 << 12)
1677 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7 << 12)
1678 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x6 << 27)
1679 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27)
1685 #define PMU_CC4_IF_TYPE_MASK 0x00003000
1686 #define PMU_CC4_IF_TYPE_RMII 0x00000000
1687 #define PMU_CC4_IF_TYPE_MII 0x00001000
1688 #define PMU_CC4_IF_TYPE_RGMII 0x00002000
1690 #define PMU_CC4_SW_TYPE_MASK 0x0000c000
1691 #define PMU_CC4_SW_TYPE_EPHY 0x00000000
1692 #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000
1693 #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000
1694 #define PMU_CC4_SW_TYPE_RGMII 0x0000c000
1727 /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */
1728 #define PMU_CC7_IF_TYPE_MASK 0x000000c0
1729 #define PMU_CC7_IF_TYPE_RMII 0x00000000
1730 #define PMU_CC7_IF_TYPE_MII 0x00000040
1731 #define PMU_CC7_IF_TYPE_RGMII 0x00000080
1737 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0
1738 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff
1740 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00
1742 #define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000
1744 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000
1752 #define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0
1762 #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u)
1784 #define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF)
1785 #define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4)
1786 #define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8)
1787 #define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12)
1788 #define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16)
1789 #define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20)
1797 #define PMU0_PLL0_PLLCTL0 0
1800 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
1805 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
1816 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
1818 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
1820 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
1824 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
1829 #define PMU1_PLL0_PLLCTL0 0
1830 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
1832 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
1837 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
1838 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
1839 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
1841 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
1843 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
1846 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
1847 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
1848 #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C
1849 #define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00
1850 #define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28
1852 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1853 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1857 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
1858 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
1859 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
1860 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
1861 #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f
1862 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
1863 #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a
1864 #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c
1865 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
1867 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
1868 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24
1869 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
1873 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
1878 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
1879 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
1886 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1888 #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000
1890 #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000
1910 #define PMU2_PLL_PLLCTL0 0
1911 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
1913 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
1918 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
1919 #define PMU2_PLL_PC1_M1DIV_SHIFT 0
1920 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
1922 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
1924 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
1929 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
1930 #define PMU2_PLL_PC2_M5DIV_SHIFT 0
1931 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
1933 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
1935 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
1940 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
1941 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
1948 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
1950 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
1952 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
1954 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
1956 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
1958 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
1962 #define PMU5_PLL_P1P2_OFF 0
1963 #define PMU5_PLL_P1_MASK 0x0f000000
1965 #define PMU5_PLL_P2_MASK 0x00f00000
1968 #define PMU5_PLL_MDIV_MASK 0x000000ff
1971 #define PMU5_PLL_NDIV_MASK 0xfff00000
1973 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
1976 #define PMU5_PLL_MRAT_MASK 0xf0000000
1978 #define PMU5_PLL_ABRAT_MASK 0x08000000
1980 #define PMU5_PLL_FDIV_MASK 0x07ffffff
1983 #define PMU5_PLL_PCHI_MASK 0x0000003f
1986 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
1987 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
1996 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
1999 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc
2000 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18
2002 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff
2003 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0
2005 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc
2006 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18
2007 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00
2009 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc
2010 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18
2012 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00
2013 #define PMU7_PLL_PLLCTL11_VAL 0x22222200
2016 #define PMU15_PLL_PLLCTL0 0
2017 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
2018 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0
2019 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
2021 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
2023 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
2025 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
2027 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
2029 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
2033 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060
2035 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040
2037 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80
2039 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000
2041 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000
2043 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000
2045 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000
2049 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001
2050 #define PMU15_PLL_PC2_CTEN_SHIFT 0
2053 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001
2054 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0
2055 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000
2057 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01
2058 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0
2059 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02
2061 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04
2063 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18
2065 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60
2067 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0
2073 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007
2074 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0
2075 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038
2077 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0
2079 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00
2081 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000
2083 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000
2085 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000
2087 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000
2089 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000
2091 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000
2093 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000
2095 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000
2097 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000
2101 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF
2102 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0
2103 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000
2105 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000
2109 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF
2110 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0
2111 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000
2113 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000
2116 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1
2117 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5
2122 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070
2125 #define PMU17_PLLCTL2_NDIV_MODE_INT 0
2130 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0
2138 #define PMU4335_PLL0_PC2_P1DIV_MASK 0x000f0000
2140 #define PMU4335_PLL0_PC2_NDIV_INT_MASK 0xff800000
2142 #define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00
2146 #define PMU4347_PLL0_PC2_P1DIV_MASK 0x000f0000
2148 #define PMU4347_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
2150 #define PMU4347_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff
2151 #define PMU4347_PLL0_PC3_NDIV_FRAC_SHIFT 0
2152 #define PMU4347_PLL1_PC5_P1DIV_MASK 0xc0000000
2154 #define PMU4347_PLL1_PC6_P1DIV_MASK 0x00000003
2155 #define PMU4347_PLL1_PC6_P1DIV_SHIFT 0
2156 #define PMU4347_PLL1_PC6_NDIV_INT_MASK 0x00000ffc
2158 #define PMU4347_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000
2165 #define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000
2167 #define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
2169 #define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff
2170 #define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0
2171 #define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000
2173 #define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003
2174 #define PMU4369_PLL1_PC6_P1DIV_SHIFT 0
2175 #define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc
2177 #define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000
2189 #define RES43236_REGULATOR 0
2197 #define CCTRL43236_BT_COEXIST (1<<0) /**< 0 disable */
2198 #define CCTRL43236_SECI (1<<1) /**< 0 SECI is disabled (JATG functional) */
2199 #define CCTRL43236_EXT_LNA (1<<2) /**< 0 disable */
2201 #define CCTRL43236_GSIO (1<<4) /**< 0 disable */
2204 #define CST43236_SFLASH_MASK 0x00000040
2205 #define CST43236_OTP_SEL_MASK 0x00000080
2207 #define CST43236_HSIC_MASK 0x00000100 /**< USB/HSIC */
2208 #define CST43236_BP_CLK 0x00000200 /**< 120/96Mbps */
2209 #define CST43236_BOOT_MASK 0x00001800
2211 #define CST43236_BOOT_FROM_SRAM 0 /**< boot from SRAM, ARM in reset */
2216 #define PMU1_PLL0_CHIPCTL0 0
2220 #define SOCDEVRAM_BP_ADDR 0x1E000000
2221 #define SOCDEVRAM_ARM_ADDR 0x00800000
2223 #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0
2227 #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F
2229 #define PMU_VREG0_RAMP_SEL_MASK 0x7
2236 #define PMU_VREG4_CLDO_PWM_MASK 0x7
2239 #define PMU_VREG4_LPLDO1_MASK 0x7
2240 #define PMU_VREG4_LPLDO1_1p20V 0
2250 #define PMU4350_VREG4_LPLDO1_1p10V 0
2260 #define PMU_VREG4_LPLDO2_LVM_MASK 0x7
2262 #define PMU_VREG4_LPLDO2_HVM_MASK 0x7
2263 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f
2264 #define PMU_VREG4_LPLDO2_1p00V 0
2271 #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1
2275 #define PMU_VREG5_HSICAVDD_PD_MASK 0x1
2277 #define PMU_VREG5_HSICDVDD_PD_MASK 0x1
2280 #define CST43228_OTP_PRESENT 0x2
2283 #define CCTRL4360_I2C_MODE (1 << 0)
2300 #define RES4360_REGULATOR 0
2312 #define CST4360_XTAL_40MZ 0x00000001
2313 #define CST4360_SFLASH 0x00000002
2314 #define CST4360_SPROM_PRESENT 0x00000004
2315 #define CST4360_SFLASH_TYPE 0x00000004
2316 #define CST4360_OTP_ENABLED 0x00000008
2317 #define CST4360_REMAP_ROM 0x00000010
2318 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060
2320 #define CST4360_ILP_DIVEN 0x00000080
2321 #define CST4360_MODE_USB 0x00000100
2322 #define CST4360_SPROM_SIZE_MASK 0x00000600
2324 #define CST4360_BBPLL_LOCK 0x00000800
2325 #define CST4360_AVBBPLL_LOCK 0x00001000
2326 #define CST4360_USBBBPLL_LOCK 0x00002000
2330 #define CCTRL_4360_UART_SEL 0x2
2338 #define RES43602_LPLDO_PU 0
2368 #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */
2380 #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */
2382 #define CC_SR1_43602_SR_ASM_ADDR (0x0)
2385 #define PMU43602_PLL_CTL6_VAL 0x68000528
2386 #define PMU43602_PLL_CTL7_VAL 0x6
2391 #define RES4365_REGULATOR_PU 0
2407 #define RES43684_REGULATOR_PU 0
2425 #define RES7271_REGULATOR_PU 0
2436 #define RES4349_LPLDO_PU 0
2469 #define RES4373_LPLDO_PU 0
2501 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1
2502 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0
2504 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2)
2505 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6)
2514 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1
2515 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0
2517 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2)
2518 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6)
2527 #define CC_SR1_4349_SR_ASM_ADDR (0x10)
2528 #define CST4349_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
2529 #define CST4349_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
2530 #define CST4349_SPROM_PRESENT 0x00000010
2533 #define CST4373_CHIPMODE_USB20D(cs) (((cs) & (1 << 8)) != 0) /* USB */
2534 #define CST4373_CHIPMODE_SDIOD(cs) (((cs) & (1 << 7)) != 0) /* SDIO */
2535 #define CST4373_CHIPMODE_PCIE(cs) (((cs) & (1 << 6)) != 0) /* PCIE */
2536 #define CST4373_SFLASH_PRESENT 0x00000010
2540 #define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_MASK (0x7 << 15)
2542 #define CC2_4349_PHY_PWRSE_RST_CNT_MASK (0xF << 0)
2543 #define CC2_4349_PHY_PWRSE_RST_CNT_SHIFT (0)
2571 #define CC4349_FNSEL_HWDEF (0)
2589 #define RES4364_LPLDO_PU 0
2622 #define CC4349_PIN_GPIO_00 (0)
2644 #define MUXENAB4349_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
2649 #define CR4_4364_RAM_BASE (0x160000)
2652 #define CC_SR1_4364_SR_CORE0_ASM_ADDR (0x10)
2653 #define CC_SR1_4364_SR_CORE1_ASM_ADDR (0x10)
2655 #define CC_SR0_4364_SR_ENG_EN_MASK 0x1
2656 #define CC_SR0_4364_SR_ENG_EN_SHIFT 0
2658 #define CC_SR0_4364_SR_RSRC_TRIGGER (0xC << 2)
2659 #define CC_SR0_4364_SR_WD_MEM_MIN_DIV (0x3 << 6)
2669 #define PMU_4364_CC1_ENABLE_BBPLL_PWR_DWN (0x1 << 4)
2670 #define PMU_4364_CC1_BBPLL_ARESET_LQ_TIME (0x1 << 8)
2671 #define PMU_4364_CC1_BBPLL_ARESET_HT_UPTIME (0x1 << 10)
2672 #define PMU_4364_CC1_BBPLL_DRESET_LQ_UPTIME (0x1 << 12)
2673 #define PMU_4364_CC1_BBPLL_DRESET_HT_UPTIME (0x4 << 16)
2674 #define PMU_4364_CC1_SUBCORE_PWRSW_UP_DELAY (0x8 << 20)
2675 #define PMU_4364_CC1_SUBCORE_PWRSW_RESET_CNT (0x4 << 24)
2677 #define PMU_4364_CC2_PHY_PWRSW_RESET_CNT (0x2 << 0)
2678 #define PMU_4364_CC2_PHY_PWRSW_RESET_MASK (0x7)
2684 #define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_OFF (0)
2685 #define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_OFF (0)
2690 #define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_OFF (0)
2708 #define PMU_VREG_0 (0u)
2731 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03
2732 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490
2733 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03
2734 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410
2737 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07
2738 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF
2758 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
2759 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u
2767 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
2768 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u
2780 #define PMU_4364_VREG5_MAC_CLK_1x1_AUTO (0x1 << 18)
2781 #define PMU_4364_VREG5_SR_AUTO (0x1 << 20)
2782 #define PMU_4364_VREG5_BT_PWM_MASK (0x1 << 21)
2783 #define PMU_4364_VREG5_BT_AUTO (0x1 << 22)
2784 #define PMU_4364_VREG5_WL2CLB_DVFS_EN_MASK (0x1 << 23)
2785 #define PMU_4364_VREG5_BT_PWMK (0)
2786 #define PMU_4364_VREG5_WL2CLB_DVFS_EN (0)
2788 #define PMU_4364_VREG6_BBPLL_AUTO (0x1 << 17)
2789 #define PMU_4364_VREG6_MINI_PMU_PWM (0x1 << 18)
2790 #define PMU_4364_VREG6_LNLDO_AUTO (0x1 << 21)
2791 #define PMU_4364_VREG6_PCIE_PWRDN_0_AUTO (0x1 << 23)
2792 #define PMU_4364_VREG6_PCIE_PWRDN_1_AUTO (0x1 << 25)
2793 #define PMU_4364_VREG6_MAC_CLK_3x3_PWM (0x1 << 27)
2794 #define PMU_4364_VREG6_ENABLE_FINE_CTRL (0x1 << 30)
2796 #define PMU_4364_PLL0_DISABLE_CHANNEL6 (0x1 << 18)
2798 #define CC_GCI1_REG (0x1)
2799 #define CC_GCI1_4364_IND_STATE_FOR_GPIO9_11 (0x0ccccccc)
2808 #define CST4364_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
2809 #define CST4364_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
2810 #define CST4364_SPROM_PRESENT 0x00000010
2812 #define PMU_4364_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF
2813 #define PMU_4364_MACCORE_1_RES_REQ_MASK 0x7FFB3647
2815 #define PMU_4364_RSDB_MODE (0)
2819 #define PMU_4364_MAX_MASK_1x1 (0x7FFF3E47)
2820 #define PMU_4364_MAX_MASK_RSDB (0x7FFFFFFF)
2821 #define PMU_4364_MAX_MASK_3x3 (0x3FCFFFFF)
2823 #define PMU_4364_SAVE_RESTORE_UPDNTIME_1x1 (0xC000C)
2824 #define PMU_4364_SAVE_RESTORE_UPDNTIME_3x3 (0xF000F)
2827 #define FORCE_CLK_OFF 0
2829 #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0)
2831 #define TSF_CLK_FRAC_L_4364_120MHZ 0x8889
2832 #define TSF_CLK_FRAC_H_4364_120MHZ 0x8
2833 #define TSF_CLK_FRAC_L_4364_160MHZ 0x6666
2834 #define TSF_CLK_FRAC_H_4364_160MHZ 0x6
2846 #define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10)
2849 #define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12)
2852 #define RES4347_MEMLPLDO_PU 0
2886 #define RES4369_DUMMY 0
2919 #define CST4347_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
2920 #define CST4347_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
2921 #define CST4347_JTAG_STRAP_ENABLED(cs) (((cs) & (1 << 20)) != 0) /* JTAG strap st */
2922 #define CST4347_SPROM_PRESENT 0x00000010
2950 #define CC4_4347_LHL_TIMER_SELECT (1 << 0)
2962 #define VREG5_4347_MEMLPLDO_ADJ_MASK 0xF0000000
2964 #define VREG5_4347_LPLDO_ADJ_MASK 0x00F00000
2968 #define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */
2969 #define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */
2970 #define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */
2971 #define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */
2972 #define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */
2973 #define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */
2974 #define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */
2975 #define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */
2976 #define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */
2977 #define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */
2978 #define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */
2979 #define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */
2980 #define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */
2981 #define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */
2982 #define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */
2983 #define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */
2990 * We use first 12kB (0x3000) in BMC buffer for template in main core and
2991 * 6.5kB (0x1A00) in aux core, followed by ASM code
2993 #define SR_ASM_ADDR_MAIN_4347 (0x18)
2994 #define SR_ASM_ADDR_AUX_4347 (0xd)
2995 #define SR_ASM_ADDR_DIG_4347 (0x0)
2997 #define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00)
2998 #define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00)
2999 #define SR_ASM_ADDR_DIG_4369 (0x0)
3005 #define SR0_SR_ENG_EN_MASK 0x1
3006 #define SR0_SR_ENG_EN_SHIFT 0
3008 #define SR0_RSRC_TRIGGER (0xC << 2)
3009 #define SR0_WD_MEM_MIN_DIV (0x3 << 6)
3019 #define SR0_4369_SR_ENG_EN_MASK 0x1
3020 #define SR0_4369_SR_ENG_EN_SHIFT 0
3022 #define SR0_4369_RSRC_TRIGGER (0xC << 2)
3023 #define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6)
3033 #define LHL4369_UP_CNT 0
3091 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
3097 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
3100 * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls
3102 #define RES4369_DUMMY 0
3135 #define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
3136 #define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
3137 #define CST4369_SPROM_PRESENT 0x00000010
3139 #define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF
3140 #define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647
3143 #define RES43430_LPLDO_PU 0
3176 #define CST43430_SDIO_MODE 0x00000001
3177 #define CST43430_GSPI_MODE 0x00000002
3178 #define CST43430_RSRC_INIT_MODE_0 0x00000080
3179 #define CST43430_RSRC_INIT_MODE_1 0x00000100
3180 #define CST43430_SEL0_SDIO 0x00000200
3181 #define CST43430_SEL1_SDIO 0x00000400
3182 #define CST43430_SEL2_SDIO 0x00000800
3183 #define CST43430_BBPLL_LOCKED 0x00001000
3184 #define CST43430_DBG_INST_DETECT 0x00004000
3185 #define CST43430_CLB2WL_BT_READY 0x00020000
3186 #define CST43430_JTAG_MODE 0x00100000
3187 #define CST43430_HOST_IFACE 0x00400000
3188 #define CST43430_TRIM_EN 0x00800000
3189 #define CST43430_DIN_PACKAGE_OPTION 0x10000000
3191 #define PMU43430_PLL0_PC2_P1DIV_MASK 0x0000000f
3192 #define PMU43430_PLL0_PC2_P1DIV_SHIFT 0
3193 #define PMU43430_PLL0_PC2_NDIV_INT_MASK 0x0000ff80
3195 #define PMU43430_PLL0_PC4_MDIV2_MASK 0x0000ff00
3199 #define SRAM_43430_SR_ASM_ADDR 0x7f800
3200 #define CC_SR1_43430_SR_ASM_ADDR ((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8)
3206 #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000
3207 #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F
3209 #define PMU43012_MAC_RES_REQ_TIMER 0x1D000000
3210 #define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF
3212 #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000
3213 #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F
3216 #define CHIP_HOSTIF_PCIEMODE 0x1
3217 #define CHIP_HOSTIF_USBMODE 0x2
3218 #define CHIP_HOSTIF_SDIOMODE 0x4
3224 #define RES4335_LPLDO_PO 0
3257 #define CST4335_SPROM_MASK 0x00000020
3258 #define CST4335_SFLASH_MASK 0x00000040
3260 #define CST4335_RES_INIT_MODE_MASK 0x00000180
3261 #define CST4335_CHIPMODE_MASK 0xF
3262 #define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */
3263 #define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */
3264 #define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /**< HSIC || USBDA */
3265 #define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */
3268 #define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
3272 #define CR4_55500_RAM_START (0x3a0000)
3273 #define CR4_55500_TCAM_SZ (0x800)
3274 #define CR4_55500_TRX_HDR_SZ (0x2b4)
3276 #define CR4_55560_RAM_START (0x370000)
3277 #define CR4_55560_TCAM_SZ (0x800)
3279 #define CR4_55560_TRX_HDR_SZ (0x2b4)
3281 #define CR4_55560_TRX_HDR_SZ (0x20)
3287 #define PATCHTBL_SIZE (0x800)
3288 #define CR4_4335_RAM_BASE (0x180000)
3289 #define CR4_4345_LT_C0_RAM_BASE (0x1b0000)
3290 #define CR4_4345_GE_C0_RAM_BASE (0x198000)
3291 #define CR4_4349_RAM_BASE (0x180000)
3292 #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000)
3293 #define CR4_4350_RAM_BASE (0x180000)
3294 #define CR4_4360_RAM_BASE (0x0)
3295 #define CR4_43602_RAM_BASE (0x180000)
3296 #define CA7_4365_RAM_BASE (0x200000)
3297 #define CR4_4373_RAM_BASE (0x160000)
3298 #define CST4373_JTAG_ENABLE(cs) (((cs) & (1 << 0)) != 0)
3299 #define CST4373_CHIPMODE_RSRC_INIT0(cs) (((cs) & (1 << 1)) != 0)
3300 #define CST4373_SDIO_PADVDDIO(cs) (((cs) & (1 << 5)) != 0)
3301 #define CST4373_USBHUB_BYPASS(cs) (((cs) & (1 << 9)) != 0)
3302 #define STRAP4373_CHIPMODE_RSRC_INIT1 0x1
3303 #define STRAP4373_VTRIM_EN 0x1
3304 #define STRAP4373_SFLASH_PRESENT 0x1
3306 #define OTP4373_SFLASH_MASK 0x3F
3307 #define OTP4373_SFLASH_PRESENT_MASK 0x1
3308 #define OTP4373_SFLASH_TYPE_MASK 0x2
3309 #define OTP4373_SFLASH_TYPE_SHIFT 0x1
3310 #define OTP4373_SFLASH_CLKDIV_MASK 0x3C
3311 #define OTP4373_SFLASH_CLKDIV_SHIFT 0x2
3312 #define SPROM4373_OTP_SELECT 0x00000010
3313 #define SPROM4373_OTP_PRESENT 0x00000020
3314 #define CC4373_SFLASH_CLKDIV_MASK 0x1F000000
3317 #define CR4_4347_RAM_BASE (0x170000)
3318 #define CR4_4362_RAM_BASE (0x170000)
3319 #define CR4_4369_RAM_BASE (0x170000)
3320 #define CR4_4377_RAM_BASE (0x170000)
3321 #define CR4_43751_RAM_BASE (0x170000)
3322 #define CA7_4367_RAM_BASE (0x200000)
3323 #define CR4_4378_RAM_BASE (0x352000)
3325 #define CA7_4368_RAM_BASE (0x200000)
3334 #define SPROM4335_OTP_SELECT 0x00000010
3335 #define SPROM4335_OTP_PRESENT 0x00000020
3340 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770
3343 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000
3348 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1
3349 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2
3350 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C
3354 #define SPROM4335_OTP_SELECT 0x00000010
3355 #define SPROM4335_OTP_PRESENT 0x00000020
3360 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770
3363 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000
3368 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1
3369 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2
3370 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C
3376 #define RES43012_MEMLPLDO_PU 0
3407 #define CST43012_SPROM_PRESENT 0x00000010
3410 #define SR0_43012_SR_ENG_EN_MASK 0x1
3411 #define SR0_43012_SR_ENG_EN_SHIFT 0
3413 #define SR0_43012_SR_RSRC_TRIGGER (0xC << 2)
3414 #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3 << 6)
3428 #define SR1_43012_SR_INIT_ADDR_MASK 0x3ff
3429 #define SR1_43012_SR_ASM_ADDR 0xA
3432 #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003f
3433 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0
3434 #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00
3436 #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00
3441 #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003
3442 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0
3443 #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000c
3447 #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000
3449 #define BCM7271_PMU30_ALPCLK_ONEMHZ_ENAB 0x00010000
3452 #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010
3453 #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040
3454 #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800
3455 #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000
3456 #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000
3459 #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000
3460 #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000
3461 #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000
3462 #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000
3463 #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000
3464 #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000
3465 #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000
3466 #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000
3467 #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000
3468 #define PMUCCTL04_43012_USE_LOCK 0x20000000
3469 #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000
3470 #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000
3474 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0
3476 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000
3478 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000
3480 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000
3482 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038
3485 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0
3488 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1F
3490 #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400
3492 #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001
3493 #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020
3494 #define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080
3495 #define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200
3496 #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400
3497 #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000
3498 #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000
3499 #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000
3500 #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000
3502 #define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000
3505 #define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0
3508 #define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000
3512 #define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000
3514 #define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F
3516 #define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000
3518 #define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F
3520 #define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000
3522 #define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0
3524 #define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0
3526 #define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5
3528 #define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000
3530 #define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_VAL 0x7
3533 #define CST4345_SPROM_MASK 0x00000020
3534 #define CST4345_SFLASH_MASK 0x00000040
3536 #define CST4345_RES_INIT_MODE_MASK 0x00000180
3537 #define CST4345_CHIPMODE_MASK 0x4000F
3538 #define CST4345_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */
3539 #define CST4345_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */
3540 #define CST4345_CHIPMODE_HSIC(cs) (((cs) & (1 << 2)) != 0) /* HSIC */
3541 #define CST4345_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */
3542 #define CST4345_CHIPMODE_USB20D(cs) (((cs) & (1 << 18)) != 0) /* USBDA */
3545 #define CST4350_SDIO_MODE 0x00000001
3546 #define CST4350_HSIC20D_MODE 0x00000002
3547 #define CST4350_BP_ON_HSIC_CLK 0x00000004
3548 #define CST4350_PCIE_MODE 0x00000008
3549 #define CST4350_USB20D_MODE 0x00000010
3550 #define CST4350_USB30D_MODE 0x00000020
3551 #define CST4350_SPROM_PRESENT 0x00000040
3552 #define CST4350_RSRC_INIT_MODE_0 0x00000080
3553 #define CST4350_RSRC_INIT_MODE_1 0x00000100
3554 #define CST4350_SEL0_SDIO 0x00000200
3555 #define CST4350_SEL1_SDIO 0x00000400
3556 #define CST4350_SDIO_PAD_MODE 0x00000800
3557 #define CST4350_BBPLL_LOCKED 0x00001000
3558 #define CST4350_USBPLL_LOCKED 0x00002000
3559 #define CST4350_LINE_STATE 0x0000C000
3560 #define CST4350_SERDES_PIPE_PLLLOCK 0x00010000
3561 #define CST4350_BT_READY 0x00020000
3562 #define CST4350_SFLASH_PRESENT 0x00040000
3563 #define CST4350_CPULESS_ENABLE 0x00080000
3564 #define CST4350_STRAP_HOST_IFC_1 0x00100000
3565 #define CST4350_STRAP_HOST_IFC_2 0x00200000
3566 #define CST4350_STRAP_HOST_IFC_3 0x00400000
3567 #define CST4350_RAW_SPROM_PRESENT 0x00800000
3568 #define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000
3569 #define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000
3570 #define CST4350_SDIO_PAD_VDDIO 0x04000000
3571 #define CST4350_GSPI_MODE 0x08000000
3572 #define CST4350_PACKAGE_OPTION 0xF0000000
3576 #define CST4350_PACKAGE_WLCSP 0x0
3577 #define CST4350_PACKAGE_PCIE 0x1
3578 #define CST4350_PACKAGE_WLBGA 0x2
3579 #define CST4350_PACKAGE_DBG 0x3
3580 #define CST4350_PACKAGE_USB 0x4
3581 #define CST4350_PACKAGE_USB_HSIC 0x4
3603 #define CST4350_HOST_IFC_MASK 0x00700000
3607 #define CST4350_IFC_MODE_SDIOD 0x0
3608 #define CST4350_IFC_MODE_HSIC20D 0x1
3609 #define CST4350_IFC_MODE_HSIC30D 0x2
3610 #define CST4350_IFC_MODE_PCIE 0x3
3611 #define CST4350_IFC_MODE_USB20D 0x4
3612 #define CST4350_IFC_MODE_USB30D 0x5
3613 #define CST4350_IFC_MODE_USB30D_WL 0x6
3614 #define CST4350_IFC_MODE_USB30D_BT 0x7
3619 #define RES4350_LPLDO_PU 0
3651 #define MUXENAB4350_UART_MASK (0x0000000f)
3652 #define MUXENAB4350_UART_SHIFT 0
3653 #define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for host_wake */
3655 #define MUXENAB4349_UART_MASK (0xf)
3660 #define CC4350_FNSEL_HWDEF (0)
3678 #define CC4350_PIN_GPIO_00 (0)
3697 #define CC2_4350_PHY_PWRSW_UPTIME_MASK (0xf << 0)
3698 #define CC2_4350_PHY_PWRSW_UPTIME_SHIFT (0)
3699 #define CC2_4350_VDDM_PWRSW_UPDELAY_MASK (0xf << 4)
3701 #define CC2_4350_VDDM_PWRSW_UPTIME_MASK (0xf << 8)
3703 #define CC2_4350_SBC_PWRSW_DNDELAY_MASK (0x3 << 12)
3705 #define CC2_4350_PHY_PWRSW_DNDELAY_MASK (0x3 << 14)
3707 #define CC2_4350_VDDM_PWRSW_DNDELAY_MASK (0x3 << 16)
3717 #define CC3_SR_CLK_SR_MEM_MASK (1 << 0)
3718 #define CC3_SR_CLK_SR_MEM_SHIFT (0)
3725 #define CC3_SR_MINDIV_FAST_CLK_MASK (0xF << 4)
3735 #define CC3_SR_NUM_CLK_HIGH_MASK (0x7 << 12)
3741 #define CC3_SR_BIT17_19_TBD_MASK (0x7 << 17)
3753 #define CC3_SR_BIT25_26_TBD_MASK (0x3 << 25)
3757 #define CC3_SR_GPIO_MUX_MASK (0xF << 28)
3761 #define CC4_SR_INIT_ADDR_MASK (0x3FF0000)
3762 #define CC4_4350_SR_ASM_ADDR (0x30)
3763 #define CC4_4350_C0_SR_ASM_ADDR (0x0)
3764 #define CC4_4335_SR_ASM_ADDR (0x48)
3765 #define CC4_4345_SR_ASM_ADDR (0x48)
3778 #define VREG6_4350_SR_EXT_CLKDIV_MASK (0x3 << 21)
3810 #define CC4347_FNSEL_HWDEF (0)
3841 #define CC_GCI_CHIPCTRL_00 (0)
3854 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12)
3857 #define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */
3866 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8)
3868 #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFF << 8)
3869 #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCC << 8)
3874 #define GCI_CHIPSTATUS_00 (0)
3893 #define RES4345_LPLDO_PU 0
3928 #define CC43012_PIN_GPIO_00 (0)
3946 #define CC43012_FNSEL_HWDEF (0)
3966 #define CC4335_PIN_GPIO_00 (0)
3997 #define CC4335_FNSEL_HWDEF (0)
4015 #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */
4027 #define CC4345_PIN_GPIO_00 (0)
4063 #define CC4345_FNSEL_HWDEF (0)
4080 #define MUXENAB4345_UART_MASK (0x0000000f)
4081 #define MUXENAB4345_UART_SHIFT 0
4082 #define MUXENAB4345_HOSTWAKE_MASK (0x000000f0)
4086 #define CC4349_GRP_GCI_AVS_CTRL_MASK (0xffe00000)
4091 #define CC4345_GCI_AVS_CTRL_MASK (0xfc)
4096 #define CC43430_PIN_GPIO_00 (0)
4108 #define MUXENAB43430_UART_MASK (0x0000000f)
4109 #define MUXENAB43430_UART_SHIFT 0
4110 #define MUXENAB43430_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
4114 #define CC43430_RFSWCTRL_EN_MASK (0x7f8)
4117 /* GCI GPIO for function sel GCI-0/GCI-1 */
4118 #define CC_GCI_GPIO_0 (0)
4136 #define CC_GCI_GPIO_INVALID 0xFF
4139 #define GCIMASK(pos) (((uint32)0xF) << pos)
4143 #define GCIGETNBL(val, pos) ((val >> pos) & 0xF)
4146 #define GCIMASK_8B(pos) (((uint32)0xFF) << pos)
4150 #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF)
4153 #define GCIMASK_4B(pos) (((uint32)0xF) << pos)
4157 #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF)
4160 #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */
4178 #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */
4196 #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */
4226 #define LHL_PWRSEQCTL_SLEEP_EN (1 << 0)
4258 #define LHL_PWRSEQ_CTL (0x000000ff)
4260 /* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78)
4263 #define LHL_PWRUP_ISOLATION_CNT (0x6 << 8)
4264 #define LHL_PWRUP_RETENTION_CNT (0x5 << 16)
4265 #define LHL_PWRUP_PWRSW_CNT (0x7 << 24)
4269 #define LHL_PWRUP_CTL_MASK (0x3F3F3F00)
4274 #define LHL_PWRUP_ISOLATION_CNT_4347 (0x7 << 8)
4275 #define LHL_PWRUP_RETENTION_CNT_4347 (0x5 << 16)
4276 #define LHL_PWRUP_PWRSW_CNT_4347 (0x7 << 24)
4282 #define LHL_PWRUP2_CLDO_DN_CNT (0x0)
4283 #define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8)
4284 #define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16)
4285 #define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24)
4286 #define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F)
4292 /* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */
4293 #define LHL_PWRDN_SLEEP_CNT (0x4)
4294 #define LHL_PWRDN_CTL_MASK (0x3F)
4296 /* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */
4297 #define LHL_PWRDN2_CLDO_DN_CNT (0x4)
4298 #define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8)
4299 #define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16)
4300 #define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24)
4305 #define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F)
4310 #define LHL_WL_ARMTIM0_INTRP_EN 0x00000001
4311 #define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002
4314 #define LHL_WL_MACTIM0_INTRP_EN 0x00000001
4315 #define LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER 0x00000002
4318 #define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000
4321 #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001
4323 #define LHL_PS_MODE_0 0
4327 #define GCI_MAILBOXDATA_TOWLAN (1 << 0)
4345 #define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0)
4351 #define MUXENAB4335_UART_MASK (0x0000000f)
4353 #define MUXENAB4335_UART_SHIFT 0
4354 #define MUXENAB4335_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for SDIO host_wake */
4360 #define MUXENAB43012_HOSTWAKE_MASK (0x00000001)
4373 #define RES53573_REGULATOR_PU 0
4396 #define CST53573_LOCK_CPUPLL 0x00000001
4397 #define CST53573_LOCK_MISCPLL 0x00000002
4398 #define CST53573_LOCK_DDRPLL 0x00000004
4399 #define CST53573_LOCK_PCIEPLL 0x00000008
4400 #define CST53573_EPHY_ENERGY_DET 0x00001f00
4401 #define CST53573_RAW_ENERGY 0x0003e000
4402 #define CST53573_BBPLL_LOCKED_O 0x00040000
4403 #define CST53573_SERDES_PIPE_PLLLOCK 0x00080000
4404 #define CST53573_STRAP_PCIE_EP_MODE 0x00100000
4405 #define CST53573_EPHY_PLL_LOCK 0x00200000
4406 #define CST53573_AUDIO_PLL_LOCKED_O 0x00400000
4407 #define CST53573_PCIE_LINK_IN_L11 0x01000000
4408 #define CST53573_PCIE_LINK_IN_L12 0x02000000
4409 #define CST53573_DIN_PACKAGEOPTION 0xf0000000
4413 #define PMU_53573_CC1_HT_CLK_REQ_CTRL_MASK 0x00000010
4414 #define PMU_53573_CC1_HT_CLK_REQ_CTRL 0x00000010
4417 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP_MASK 0x00000010
4418 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP 0x00000000
4419 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN_MASK 0x00000002
4420 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN 0x00000002
4424 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
4425 #define SECI_STAT_BI (1 << 0) /* Break Interrupt */
4440 #define SECI_MODE_UART 0x0
4441 #define SECI_MODE_SECI 0x1
4442 #define SECI_MODE_LEGACY_3WIRE_BT 0x2
4443 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3
4444 #define SECI_MODE_HALF_SECI 0x4
4446 #define SECI_RESET (1 << 0)
4450 #define SECI_MODE_MASK 0x7
4455 #define SECI_SLIP_ESC_CHAR 0xDB
4457 #define SECI_SIGNOFF_1 0
4458 #define SECI_REFRESH_REQ 0xDA
4465 #define SECI_UART_MSR_CTS_STATE (1 << 0)
4471 #define GCI_RXF_LVL_MASK (0xFF << 0)
4472 #define GCI_RXF_TIMEOUT_MASK (0xFF << 8)
4476 #define SECI_TXF_LVL_MASK (0x3F << 8)
4477 #define TXF_AE_LVL_DEFAULT 0x4
4478 #define SECI_RXF_LVL_FC_MASK (0x3F << 16)
4481 #define SECI_UART_FCR_RFR (1 << 0)
4492 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
4494 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
4506 #define SECI_UART_MCR_TX_EN (1 << 0)
4517 #define SECI_UART_LSR_RXOVR_MASK (1 << 0)
4525 #define SECI_UART_MSR_CTSS_MASK (1 << 0)
4534 #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF
4542 #define LTECX_MUX_MODE_IDX 0
4543 #define LTECX_MUX_MODE_WCI2 0x0
4544 #define LTECX_MUX_MODE_GPIO 0x1
4547 #define LTECX_NVRAM_FSYNC_IDX 0
4553 #define LTECX_NVRAM_WCI2IN_IDX 0
4564 #define ECI_BW_20 0x0
4565 #define ECI_BW_25 0x1
4566 #define ECI_BW_30 0x2
4567 #define ECI_BW_35 0x3
4568 #define ECI_BW_40 0x4
4569 #define ECI_BW_45 0x5
4570 #define ECI_BW_50 0x6
4571 #define ECI_BW_ALL 0x7
4577 /* otpctrl1 0xF4 */
4578 #define OTPC_FORCE_PWR_OFF 0x02000000
4580 #define CC_SR_CTL0_ENABLE_MASK 0x1
4581 #define CC_SR_CTL0_ENABLE_SHIFT 0
4583 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */
4592 #define CC_SR_CTL1_SR_INIT_MASK 0x3FF
4593 #define CC_SR_CTL1_SR_INIT_SHIFT 0
4595 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
4599 #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0
4609 #define GCI_GPIO_STS_VALUE_BIT 0
4613 #define GCI_GPIO_STS_CLEAR 0xF
4615 #define GCI_GPIO_STS_EDGE_TRIG_BIT 0
4623 #define SRPWR_DMN0_PCIE (0) /* PCIE */
4650 #define SRPWR_DMN_ID_MASK (0xF)
4653 #define PMU_PREC_USEC_TIMER_ENABLE 0x1