Lines Matching +full:0 +full:x3fffc000
44 #define NAN_OUI_TYPE 0x13 /* Type/Version */
45 #define NAN_AF_OUI_TYPE 0x18 /* Type/Version */
47 #define NAN_IE_ID 0xdd
70 #define NAN_SRF_BLOOM_MASK 0x01
71 #define NAN_SRF_INCLUDE_MASK 0x02
72 #define NAN_SRF_INDEX_MASK 0x0C
77 #define NAN_BLOOM_CRC32_MASK 0xFFFF
80 #define NAN_ATTR_ID_OFF 0
102 #define NAN_SLOT_DUR_0TU 0
127 /* NAN_PUB_AF_CATEGORY 0x04 */
129 /* NAN_PUB_AF_ACTION 0x09 */
131 /* NAN_OUI 0x50-6F-9A */
133 /* NAN_OUI_TYPE 0x13 */
141 NAN_ATTR_MASTER_IND = 0,
193 NAN_AVAIL_RES_16_TU = 0,
200 uint8 id; /* IE ID: NAN_IE_ID 0xDD */
203 uint8 oui_type; /* NAN_OUI_TYPE 0x13 */
231 uint8 svcid[0]; /* 6*len of srvc IDs */
235 #define NAN_SC_PUBLISH 0x0
236 #define NAN_SC_SUBSCRIBE 0x1
237 #define NAN_SC_FOLLOWUP 0x2
239 #define NAN_SC_MATCHING_FILTER_PRESENT 0x4
241 #define NAN_SC_SR_FILTER_PRESENT 0x8
243 #define NAN_SC_SVC_INFO_PRESENT 0x10
245 #define NAN_SC_RANGE_LIMITED 0x20
247 #define NAN_SC_BINDING_BITMAP_PRESENT 0x40
251 /* Attribute ID - 0x03. */
268 /* Attribute ID - 0x07. */
276 [0-3]: Id for associated further avail map attribute
277 [4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
278 [6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
288 /* Attribute ID - 0x0A. */
292 /* MAP id: val [0..15], values[16-255] reserved */
302 [0-1]: avail interval duration: 0:16ms; 1:32ms; 2:64ms;
315 #define NAN_MAPCTRL_IDMASK 0x7
317 #define NAN_MAPCTRL_DURMASK 0x30
318 #define NAN_MAPCTRL_REPEAT 0x40
321 #define NAN_VENDOR_TYPE_RTT 0
327 uint8 id; /* 0xDD */
338 uint8 id; /* 0xDD */
346 /* Attribute ID - 0x06. */
356 [0-3]: Id for associated further avail map attribute
357 [4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
358 [6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
367 #define NAN_RANGING_MAP_CTRL_ID_SHIFT 0
368 #define NAN_RANGING_MAP_CTRL_ID_MASK 0x0F
370 #define NAN_RANGING_MAP_CTRL_DUR_MASK 0x30
372 #define NAN_RANGING_MAP_CTRL_REPEAT_MASK 0x40
384 NAN_RANGING_PROTO_FTM = 0
388 uint8 id; /* 0x0C */
394 [0-3]: Id for associated further avail map attribute
395 [4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
396 [6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
401 uint8 protocol; /* FTM = 0 */
406 uint8 id; /* 0x1A */
410 0: LCI Local Coordinates
427 uint8 id; /* 0x1B */
430 uint8 type_status; /* bits 0-3 type, 4-7 status */
442 uint8 ranging_ctrl; /* Bit 0: ranging report required or not */
450 uint8 id; /* 0x1C */
453 See definition in 9.4.2.22.18 in 802.11mc D5.0
465 #define NAN_RNG_REPORT_REQUIRED 0x01
466 #define NAN_RNG_FTM_PARAMS_PRESENT 0x02
467 #define NAN_RNG_SCHED_ENTRY_PRESENT 0X04
470 #define NAN_RNG_LOCATION_FLAGS_LOCAL_CORD 0x1
471 #define NAN_RNG_LOCATION_FLAGS_GEO_SPATIAL 0x2
472 #define NAN_RNG_LOCATION_FLAGS_CIVIC 0x4
473 #define NAN_RNG_LOCATION_FLAGS_LAST_MVMT 0x8
476 #define NAN_RNG_LOCATION_MASK_LAST_MVT_TSF 0x3FFFC000
480 #define NAN_FTM_MAX_BURST_DUR_SHIFT 0
486 #define NAN_FTM_MAX_BURST_DUR_MASK 0x00000F
487 #define NAN_FTM_MIN_FTM_DELTA_MASK 0x00003F
488 #define NAN_FTM_NUM_FTM_MASK 0x00001F
489 #define NAN_FTM_FORMAT_BW_MASK 0x00003F
503 #define NAN_FTM_PARAMS_UINT32_TO_ATTR(ftm_u32, ftm_attr) {ftm_attr[0] = ftm_u32 & 0xFF; \
504 ftm_attr[1] = (ftm_u32 >> 8) & 0xFF; ftm_attr[2] = (ftm_u32 >> 16) & 0xFF;}
507 #define NAN_FTM_PARAMS_ATTR_TO_UINT32(ftm_p, ftm_u32) (ftm_u32 = ftm_p[0] | ftm_p[1] << 8 | \
520 #define NAN_CONN_CAPABILITY_WFD 0x0001
521 #define NAN_CONN_CAPABILITY_WFDS 0x0002
522 #define NAN_CONN_CAPABILITY_TDLS 0x0004
523 #define NAN_CONN_CAPABILITY_INFRA 0x0008
524 #define NAN_CONN_CAPABILITY_IBSS 0x0010
525 #define NAN_CONN_CAPABILITY_MESH 0x0020
527 #define NAN_DEFAULT_MAP_ID 0 /* nan default map id */
528 #define NAN_DEFAULT_MAP_CTRL 0 /* nan default map control */
531 /* Attribute ID - 0x04. */
540 uint8 id; /* id - 0x20 */
550 uint8 id; /* id - 0x12 */
576 uint8 aux_chan[0]; /* Auxiliary Channel bitmap */
588 #define NAN_ENTRY_CNTRL_TYPE_COMM_AVAIL_MASK 0x1
590 #define NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL_MASK 0x2
592 #define NAN_ENTRY_CNTRL_TYPE_COND_AVAIL_MASK 0x4
594 #define NAN_AVAIL_CTRL_MAP_ID_MASK 0x000F
596 #define NAN_AVAIL_CTRL_COMM_CHANGED_MASK 0x0010
598 #define NAN_AVAIL_CTRL_POTEN_CHANGED_MASK 0x0020
600 #define NAN_AVAIL_CTRL_PUBLIC_CHANGED_MASK 0x0040
602 #define NAN_AVAIL_CTRL_NDC_CHANGED_MASK 0x0080
604 #define NAN_AVAIL_CTRL_MCAST_CHANGED_MASK 0x0100
606 #define NAN_AVAIL_CTRL_MCAST_CHG_CHANGED_MASK 0x0200
608 #define NAN_AVAIL_CTRL_CHANGED_FLAGS_MASK 0x03f0
610 #define NAN_AVAIL_ENTRY_CTRL_AVAIL_TYPE_MASK 0x07
612 #define NAN_AVAIL_ENTRY_CTRL_USAGE_MASK 0x18
616 #define NAN_AVAIL_ENTRY_CTRL_UTIL_MASK 0xE0
620 #define NAN_AVAIL_ENTRY_CTRL_RX_NSS_MASK 0xF00
624 #define NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT_MASK 0x1000
629 #define NAN_TIME_BMAP_CTRL_BITDUR_MASK 0x07
631 #define NAN_TIME_BMAP_CTRL_PERIOD_MASK 0x38
635 #define NAN_TIME_BMAP_CTRL_OFFSET_MASK 0x7FC0
643 #define NAN_AVAIL_CHAN_LIST_TYPE_BAND 0x00
644 #define NAN_AVAIL_CHAN_LIST_TYPE_CHANNEL 0x01
645 #define NAN_AVAIL_CHAN_LIST_NON_CONTIG_BW 0x02
646 #define NAN_AVAIL_CHAN_LIST_NUM_ENTRIES_MASK 0xF0
653 uint8 var[0];
657 #define NAN_CHAN_OP_CLASS_MASK 0x01
658 #define NAN_CHAN_NON_CONT_BW_MASK 0x02
659 #define NAN_CHAN_RSVD_MASK 0x03
660 #define NAN_CHAN_NUM_ENTRIES_MASK 0xF0
663 uint8 band[0];
667 #define NAN_ENTRY_CNTRL_TYPE_COMM_AVAIL 0x1
669 #define NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL 0x2
671 #define NAN_ENTRY_CNTRL_TYPE_COND_AVAIL 0x4
680 #define NAN_ENTRY_CNTRL_TYPE_OF_AVAIL_MASK 0x07
681 #define NAN_ENTRY_CNTRL_TYPE_OF_AVAIL_SHIFT 0
683 #define NAN_ENTRY_CNTRL_USAGE_PREF_MASK 0x18
686 #define NAN_ENTRY_CNTRL_UTIL_MASK 0x1E0
692 #define NAN_TIME_BMP_CNTRL_RSVD_MASK 0x01
693 #define NAN_TIME_BMP_CNTRL_RSVD_SHIFT 0
695 #define NAN_TIME_BMP_CNTRL_BMP_LEN_MASK 0x7E
698 #define NAN_TIME_BMP_CNTRL_BIT_DUR_MASK 0x380
701 #define NAN_TIME_BMP_CNTRL_PERIOD_MASK 0x1C00
704 #define NAN_TIME_BMP_CNTRL_START_OFFSET_MASK 0x3FE000
707 #define NAN_TIME_BMP_CNTRL_RESERVED_MASK 0xC00000
724 NAN_TIME_BMP_BIT_DUR_16TU_IDX = 0,
752 #define NAN_CHAN_ENTRY_TYPE_MASK 0x01
753 #define NAN_CHAN_ENTRY_TYPE_SHIFT 0
755 #define NAN_CHAN_ENTRY_LEN_IND_MASK 0x02
758 #define NAN_CHAN_ENTRY_RESERVED_MASK 0x0C
761 #define NAN_CHAN_ENTRY_NO_OF_CHAN_ENTRY_MASK 0xF0
764 #define NAN_CHAN_ENTRY_TYPE_BANDS 0
767 #define NAN_CHAN_ENTRY_BW_LT_80MHZ 0
780 #define NDL_ATTR_CTRL_PEER_ID_PRESENT_MASK 0x01
781 #define NDL_ATTR_CTRL_PEER_ID_PRESENT_SHIFT 0
782 #define NDL_ATTR_CTRL_IM_SCHED_PRESENT_MASK 0x02
784 #define NDL_ATTR_CTRL_NDC_ATTR_PRESENT_MASK 0x04
786 #define NDL_ATTR_CTRL_QOS_ATTR_PRESENT_MASK 0x08
788 #define NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT_MASK 0x10 /* max idle period */
790 #define NDL_ATTR_CTRL_NDL_TYPE_MASK 0x20 /* NDL type */
792 #define NDL_ATTR_CTRL_NDL_SETUP_REASON_MASK 0xC0 /* NDL Setup Reason */
796 #define NDL_ATTR_CTRL_NDL_TYPE_S_NDL 0x0 /* S-NDL */
797 #define NDL_ATTR_CTRL_NDL_TYPE_P_NDL 0x1 /* P-NDL */
800 #define NDL_ATTR_CTRL_NDL_SETUP_REASON_NDP_RANG 0x0 /* NDP or Ranging */
801 #define NDL_ATTR_CTRL_NDL_SETUP_REASON_FSD_GAS 0x1 /* FSD using GAS */
803 #define NAN_NDL_TYPE_MASK 0x0F
804 #define NDL_ATTR_TYPE_STATUS_REQUEST 0x00
805 #define NDL_ATTR_TYPE_STATUS_RESPONSE 0x01
806 #define NDL_ATTR_TYPE_STATUS_CONFIRM 0x02
807 #define NDL_ATTR_TYPE_STATUS_CONTINUED 0x00
808 #define NDL_ATTR_TYPE_STATUS_ACCEPTED 0x10
809 #define NDL_ATTR_TYPE_STATUS_REJECTED 0x20
820 #define NAN_NDL_STATUS_MASK 0xF0
828 #define NDL_ATTR_CTRL_NONE 0
843 uint8 id; /* NAN_ATTR_NAN_NDL = 0x17 */
846 uint8 type_status; /* Bits[3-0] type subfield, Bits[7-4] status subfield */
863 #define NAN_NDL_QOS_MIN_SLOT_NO_PREF 0
865 #define NAN_NDL_QOS_MAX_LAT_NO_PREF 0xFFFF
870 uint8 id; /* 0x0F */
876 uint8 num_antennas; /* Bit 0-3 tx, 4-7 rx */
884 #define NAN_DEV_CAP_ALL_MAPS_FLAG_MASK 0x1 /* nan default map control */
885 #define NAN_DEV_CAP_ALL_MAPS_FLAG_SHIFT 0
887 #define NAN_DEV_CAP_MAPID_MASK 0x1E
893 #define NAN_DEV_CAP_AWAKE_DW_2G_MASK 0x07
895 #define NAN_DEV_CAP_AWAKE_DW_5G_MASK 0x38
897 #define NAN_DEV_CAP_AWAKE_DW_RSVD_MASK 0xC0
900 #define NAN_DEV_CAP_AWAKE_DW_2G_SHIFT 0
907 #define NAN_DEV_CAP_COMMIT_DW_2G_MASK 0x07
908 #define NAN_DEV_CAP_COMMIT_DW_2G_OVERWRITE_MASK 0x3C0
910 #define NAN_DEV_CAP_COMMIT_DW_5G_MASK 0x38
911 #define NAN_DEV_CAP_COMMIT_DW_5G_OVERWRITE_MASK 0x3C00
913 #define NAN_DEV_CAP_COMMIT_DW_RSVD_MASK 0xC000
915 #define NAN_DEV_CAP_COMMIT_DW_2G_SHIFT 0
920 #define NAN_DEV_CAP_OP_PHY_MODE_HT_ONLY 0x00
921 #define NAN_DEV_CAP_OP_PHY_MODE_VHT 0x01
922 #define NAN_DEV_CAP_OP_PHY_MODE_VHT_8080 0x02
923 #define NAN_DEV_CAP_OP_PHY_MODE_VHT_160 0x04
924 #define NAN_DEV_CAP_OP_PAGING_NDL 0x08
926 #define NAN_DEV_CAP_OP_MODE_VHT_MASK 0x01
927 #define NAN_DEV_CAP_OP_MODE_VHT_SHIFT 0
928 #define NAN_DEV_CAP_OP_MODE_VHT8080_MASK 0x02
930 #define NAN_DEV_CAP_OP_MODE_VHT160_MASK 0x04
932 #define NAN_DEV_CAP_OP_MODE_PAGING_NDL_MASK 0x08
936 #define NAN_DEV_CAP_TX_ANT_MASK 0x0F
937 #define NAN_DEV_CAP_RX_ANT_MASK 0xF0
942 #define NAN_DEV_CAP_DFS_MASTER_MASK 0x01
943 #define NAN_DEV_CAP_DFS_MASTER_SHIFT 0
945 #define NAN_DEV_CAP_EXT_KEYID_MASK 0x02
948 #define NAN_DEV_CAP_NDPE_ATTR_SUPPORT_MASK 0x08
953 NAN_BAND_ID_TVWS = 0,
965 #define NAN_ULW_ATTR_CTRL_SCHED_ID_MASK 0x000F
966 #define NAN_ULW_ATTR_CTRL_SCHED_ID_SHIFT 0
967 #define NAN_ULW_ATTR_CTRL_SEQ_ID_MASK 0xFF00
970 #define NAN_ULW_OVWR_ALL_MASK 0x01
971 #define NAN_ULW_OVWR_ALL_SHIFT 0
972 #define NAN_ULW_OVWR_MAP_ID_MASK 0x1E
975 #define NAN_ULW_CTRL_TYPE_MASK 0x03
976 #define NAN_ULW_CTRL_TYPE_SHIFT 0
978 #define NAN_ULW_CTRL_CHAN_AVAIL_MASK 0x04
982 #define NAN_ULW_CTRL_RX_NSS_MASK 0x78
985 #define NAN_ULW_CTRL_TYPE_BAND 0
989 #define NAN_ULW_CNT_DOWN_NO_EXPIRE 0xFF /* ULWs doen't end until next sched update */
990 #define NAN_ULW_CNT_DOWN_CANCEL 0x0 /* cancel remaining ulws */
1002 * ulw[0] == optional field ULW control when present.
1012 /* NAN_PUB_AF_CATEGORY 0x04 */
1014 /* NAN_PUB_AF_ACTION 0x09 */
1016 /* NAN_OUI 0x50-6F-9A */
1029 /* Subtype-0 is Reserved */
1030 #define NAN_MGMT_FRM_SUBTYPE_RESERVED 0
1031 #define NAN_MGMT_FRM_SUBTYPE_INVALID 0
1060 #define NAN_REASON_RESERVED 0x0
1061 #define NAN_REASON_UNSPECIFIED 0x1
1062 #define NAN_REASON_RESOURCE_LIMIT 0x2
1063 #define NAN_REASON_INVALID_PARAMS 0x3
1064 #define NAN_REASON_FTM_PARAM_INCAP 0x4
1065 #define NAN_REASON_NO_MOVEMENT 0x5
1066 #define NAN_REASON_INVALID_AVAIL 0x6
1067 #define NAN_REASON_IMMUT_UNACCEPT 0x7
1068 #define NAN_REASON_SEC_POLICY 0x8
1069 #define NAN_REASON_QOS_UNACCEPT 0x9
1070 #define NAN_REASON_NDP_REJECT 0xa
1071 #define NAN_REASON_NDL_UNACCEPTABLE 0xb
1082 #define NAN_NDP_CTRL_CONFIRM_REQUIRED 0x01
1083 #define NAN_NDP_CTRL_SECURTIY_PRESENT 0x04
1084 #define NAN_NDP_CTRL_PUB_ID_PRESENT 0x08
1085 #define NAN_NDP_CTRL_RESP_NDI_PRESENT 0x10
1086 #define NAN_NDP_CTRL_SPEC_INFO_PRESENT 0x20
1087 #define NAN_NDP_CTRL_RESERVED 0xA0
1091 uint8 id; /* NDP: 0x10, NDPE: 0x29 */
1094 uint8 type_status; /* bits 0-3 type, 4-7 status */
1102 #define NAN_NDP_TYPE_MASK 0x0F
1103 #define NAN_NDP_TYPE_REQUEST 0x0
1104 #define NAN_NDP_TYPE_RESPONSE 0x1
1105 #define NAN_NDP_TYPE_CONFIRM 0x2
1106 #define NAN_NDP_TYPE_SECURITY 0x3
1107 #define NAN_NDP_TYPE_TERMINATE 0x4
1116 #define NAN_NDP_STATUS_MASK 0xF0
1117 #define NAN_NDP_STATUS_CONT (0 << NAN_NDP_STATUS_SHIFT)
1127 #define NAN_NDP_SETUP_STATUS_FAIL 0
1131 #define NAN_RNG_TYPE_MASK 0x0F
1132 #define NAN_RNG_TYPE_REQUEST 0x0
1133 #define NAN_RNG_TYPE_RESPONSE 0x1
1134 #define NAN_RNG_TYPE_TERMINATE 0x2
1137 #define NAN_RNG_STATUS_MASK 0xF0
1138 #define NAN_RNG_STATUS_ACCEPT (0 << NAN_RNG_STATUS_SHIFT)
1154 #define NAN_SCHED_ENTRY_MAPID_MASK 0x0F
1159 #define NAN_DEV_ELE_MAPID_CTRL_MASK 0x1
1160 #define NAN_DEV_ELE_MAPID_CTRL_SHIFT 0
1161 #define NAN_DEV_ELE_MAPID_MASK 0x1E
1168 } while (0);
1178 } while (0);
1185 #define NAN_SCHED_ENTRY_MAPID_MASK 0x0F
1186 #define NAN_SCHED_ENTRY_MAPID_SHIFT 0
1192 } while (0);
1209 #define NAN_NDC_ATTR_PROPOSED_NDC_MASK 0x1
1210 #define NAN_NDC_ATTR_PROPOSED_NDC_SHIFT 0
1220 } while (0)
1224 /* Attribute ID - 0x11 */
1249 #define NAN_SDE_CF_FSD_REQUIRED (1 << 0)
1279 #define NAN_SEC_CIPHER_SUITE_CAP_REPLAY_4 0
1280 #define NAN_SEC_CIPHER_SUITE_CAP_REPLAY_16 (1 << 0)
1285 NAN_SEC_ALGO_NONE = 0,
1300 uint8 attr_id; /* 0x22 - NAN_ATTR_CIPHER_SUITE_INFO */
1311 #define NAN_SEC_CTX_ID_TYPE_PMKID (1 << 0)
1323 uint8 attr_id; /* 0x23 - NAN_ATTR_SEC_CTX_ID_INFO */
1338 uint8 attr_id; /* 0x24 - NAN_ATTR_SHARED_KEY_DESC */
1351 #define NAN_SEC_NCSSK_DESC_MASK 0x7
1352 #define NAN_SEC_NCSSK_DESC_SHIFT 0
1353 #define NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK 0x8
1355 #define NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK 0x40
1357 #define NAN_SEC_NCSSK_DESC_KEY_ACK_MASK 0x80
1359 #define NAN_SEC_NCSSK_DESC_KEY_MIC_MASK 0x100
1361 #define NAN_SEC_NCSSK_DESC_KEY_SEC_MASK 0x200
1363 #define NAN_SEC_NCSSK_DESC_KEY_ERR_MASK 0x400
1365 #define NAN_SEC_NCSSK_DESC_KEY_REQ_MASK 0x800
1367 #define NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK 0x1000
1369 #define NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK 0x2000
1378 NAN_SEC_NCSSK_DESC_MASK);} while (0)
1384 NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK);} while (0)
1391 NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK);} while (0)
1397 NAN_SEC_NCSSK_DESC_KEY_ACK_MASK);} while (0)
1403 NAN_SEC_NCSSK_DESC_KEY_MIC_MASK);} while (0)
1409 NAN_SEC_NCSSK_DESC_KEY_SEC_MASK);} while (0)
1415 NAN_SEC_NCSSK_DESC_KEY_ERR_MASK);} while (0)
1421 NAN_SEC_NCSSK_DESC_KEY_REQ_MASK);} while (0)
1428 NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK);} while (0)
1435 NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK);} while (0)
1438 #define NAN_SEC_NCSSK_KEY_DESC_VER 0 /* NCSSK-128/256 */
1448 #define NAN_NMSG_TYPE_MASK 0x0F
1449 #define NMSG_ATTR_TYPE_STATUS_REQUEST 0x00
1450 #define NMSG_ATTR_TYPE_STATUS_RESPONSE 0x01
1451 #define NMSG_ATTR_TYPE_STATUS_CONFIRM 0x02
1452 #define NMSG_ATTR_TYPE_STATUS_SEC_INSTALL 0x03
1453 #define NMSG_ATTR_TYPE_STATUS_TERMINATE 0x04
1454 #define NMSG_ATTR_TYPE_STATUS_IMPLICIT_ENROL 0x05
1456 #define NMSG_ATTR_TYPE_STATUS_CONTINUED 0x00
1457 #define NMSG_ATTR_TYPE_STATUS_ACCEPTED 0x10
1458 #define NMSG_ATTR_TYPE_STATUS_REJECTED 0x20
1460 #define NMSG_CTRL_PUB_ID_PRESENT 0x0001
1461 #define NMSG_CTRL_NMSG_ID_PRESENT 0x0002
1462 #define NMSG_CTRL_SECURITY_PRESENT 0x0004
1463 #define NMSG_CTRL_MANY_TO_MANY_PRESENT 0x0008
1464 #define NMSG_CTRL_SVC_INFO_PRESENT 0x0010
1468 uint8 id; /* Attribute ID - 0x11 */
1476 uint8 var[0];
1479 #define NMSG_ATTR_MCAST_SCHED_MAP_ID_MASK 0x1E
1481 #define NMSG_ATTR_MCAST_SCHED_TIME_MAP_MASK 0x20
1486 uint8 id; /* 0x16 */