infineon/include/hndsoc.h

2  * Broadcom HND chip & on-chip-interconnect-related definitions.
6  * Copyright (C) 1999-2017, Broadcom Corporation
27  * <<Broadcom-WL-IPTag/Open:>>
29  * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih)	((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE	0x18200000	/* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR	0x4008	/* WR-CAP offset */
89 #define	SI_FASTRAM		0x19000000	/* On-chip RAM on chips that also have DDR */
94 #define	SI_ARMCM3_ROM		0x1e000000	/* ARM Cortex-M3 ROM */
104 #define	SI_ARM7S_ROM		0x20000000	/* ARM7TDMI-S ROM */
105 #define	SI_ARMCR4_ROM		0x000f0000	/* ARM Cortex-R4 ROM */
106 #define	SI_ARMCM3_SRAM2		0x60000000	/* ARM Cortex-M3 SRAM Region 2 */
107 #define	SI_ARM7S_SRAM2		0x80000000	/* ARM7TDMI-S SRAM Region 2 */
108 #define	SI_ARMCA7_ROM		0x00000000	/* ARM Cortex-A7 ROM */
110 #define	SI_ARMCA7_RAM		0x00200000	/* ARM Cortex-A7 RAM */
131 							 * 3-byte address modes in spi flash
156 #define	SRAM_CORE_ID		0x802		/* sram core */
188 #define	SRAMC_CORE_ID		0x822		/* SRAM controller core */
191 #define	ARM7S_CORE_ID		0x825		/* ARM7tdmi-s core */
193 #define	PMU_CORE_ID		0x827		/* PMU core */
194 #define	SSNPHY_CORE_ID		0x828		/* 802.11n single-stream phy core */
253 #define NS_PCIEG2_CORE_REV_B0	0x7		/* NS-B0 PCIE Gen 2 core rev */
288 /* dot11 core-specific status flags */
293  * communicate w/PMU regarding clock control.
339 #define BISZ_SIZE		7		/* descriptor size in 32-bit integers */
355 #define PMU_BASE_OFFSET	0x00012000	/* PMU offset is changed for ccrev >= 56 */