infineon/include/bcmpcispi.h

2  * Broadcom PCI-SPI Host Controller Register Definitions
6  * Copyright (C) 1999-2017, Broadcom Corporation
27  * <<Broadcom-WL-IPTag/Open:>>
29  * $Id: bcmpcispi.h 514727 2014-11-12 03:02:48Z $
42 	uint32 spih_ctrl;		/* 0x00 SPI Control Register */
43 	uint32 spih_stat;		/* 0x04 SPI Status Register */
44 	uint32 spih_data;		/* 0x08 SPI Data Register, 32-bits wide */
45 	uint32 spih_ext;		/* 0x0C SPI Extension Register */
46 	uint32 PAD[4];			/* 0x10-0x1F PADDING */
48 	uint32 spih_gpio_ctrl;		/* 0x20 SPI GPIO Control Register */
49 	uint32 spih_gpio_data;		/* 0x24 SPI GPIO Data Register */
50 	uint32 PAD[6];			/* 0x28-0x3F PADDING */
52 	uint32 spih_int_edge;		/* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
53 	uint32 spih_int_pol;		/* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
55 	uint32 spih_int_mask;		/* 0x48 SPI Interrupt Mask */
56 	uint32 spih_int_status;		/* 0x4C SPI Interrupt Status */
57 	uint32 PAD[4];			/* 0x50-0x5F PADDING */
59 	uint32 spih_hex_disp;		/* 0x60 SPI 4-digit hex display value */
60 	uint32 spih_current_ma;		/* 0x64 SPI SD card current consumption in mA */
61 	uint32 PAD[1];			/* 0x68 PADDING */
62 	uint32 spih_disp_sel;		/* 0x6c SPI 4-digit hex display mode select (1=current) */
63 	uint32 PAD[4];			/* 0x70-0x7F PADDING */
64 	uint32 PAD[8];			/* 0x80-0x9F PADDING */
65 	uint32 PAD[8];			/* 0xA0-0xBF PADDING */
66 	uint32 spih_pll_ctrl;	/* 0xC0 PLL Control Register */
67 	uint32 spih_pll_status;	/* 0xC4 PLL Status Register */
68 	uint32 spih_xtal_freq;	/* 0xC8 External Clock Frequency in units of 10000Hz */
69 	uint32 spih_clk_count;	/* 0xCC External Clock Count Register */
74 	uint32 cfg_space[0x40];		/* 0x000-0x0FF PCI Configuration Space (Read Only) */
75 	uint32 P_IMG_CTRL0;		/* 0x100 PCI Image0 Control Register */
77 	uint32 P_BA0;			/* 0x104 32 R/W PCI Image0 Base Address register */
78 	uint32 P_AM0;			/* 0x108 32 R/W PCI Image0 Address Mask register */
79 	uint32 P_TA0;			/* 0x10C 32 R/W PCI Image0 Translation Address register */
80 	uint32 P_IMG_CTRL1;		/* 0x110 32 R/W PCI Image1 Control register */
81 	uint32 P_BA1;			/* 0x114 32 R/W PCI Image1 Base Address register */
82 	uint32 P_AM1;			/* 0x118 32 R/W PCI Image1 Address Mask register */
83 	uint32 P_TA1;			/* 0x11C 32 R/W PCI Image1 Translation Address register */
84 	uint32 P_IMG_CTRL2;		/* 0x120 32 R/W PCI Image2 Control register */
85 	uint32 P_BA2;			/* 0x124 32 R/W PCI Image2 Base Address register */
86 	uint32 P_AM2;			/* 0x128 32 R/W PCI Image2 Address Mask register */
87 	uint32 P_TA2;			/* 0x12C 32 R/W PCI Image2 Translation Address register */
88 	uint32 P_IMG_CTRL3;		/* 0x130 32 R/W PCI Image3 Control register */
89 	uint32 P_BA3;			/* 0x134 32 R/W PCI Image3 Base Address register */
90 	uint32 P_AM3;			/* 0x138 32 R/W PCI Image3 Address Mask register */
91 	uint32 P_TA3;			/* 0x13C 32 R/W PCI Image3 Translation Address register */
92 	uint32 P_IMG_CTRL4;		/* 0x140 32 R/W PCI Image4 Control register */
93 	uint32 P_BA4;			/* 0x144 32 R/W PCI Image4 Base Address register */
94 	uint32 P_AM4;			/* 0x148 32 R/W PCI Image4 Address Mask register */
95 	uint32 P_TA4;			/* 0x14C 32 R/W PCI Image4 Translation Address register */
96 	uint32 P_IMG_CTRL5;		/* 0x150 32 R/W PCI Image5 Control register */
97 	uint32 P_BA5;			/* 0x154 32 R/W PCI Image5 Base Address register */
98 	uint32 P_AM5;			/* 0x158 32 R/W PCI Image5 Address Mask register */
99 	uint32 P_TA5;			/* 0x15C 32 R/W PCI Image5 Translation Address register */
100 	uint32 P_ERR_CS;		/* 0x160 32 R/W PCI Error Control and Status register */
101 	uint32 P_ERR_ADDR;		/* 0x164 32 R PCI Erroneous Address register */
102 	uint32 P_ERR_DATA;		/* 0x168 32 R PCI Erroneous Data register */
104 	uint32 PAD[5];			/* 0x16C-0x17F PADDING */
106 	uint32 WB_CONF_SPC_BAR;		/* 0x180 32 R WISHBONE Configuration Space Base Address */
107 	uint32 W_IMG_CTRL1;		/* 0x184 32 R/W WISHBONE Image1 Control register */
108 	uint32 W_BA1;			/* 0x188 32 R/W WISHBONE Image1 Base Address register */
109 	uint32 W_AM1;			/* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
110 	uint32 W_TA1;			/* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
111 	uint32 W_IMG_CTRL2;		/* 0x194 32 R/W WISHBONE Image2 Control register */
112 	uint32 W_BA2;			/* 0x198 32 R/W WISHBONE Image2 Base Address register */
113 	uint32 W_AM2;			/* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
114 	uint32 W_TA2;			/* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
115 	uint32 W_IMG_CTRL3;		/* 0x1A4 32 R/W WISHBONE Image3 Control register */
116 	uint32 W_BA3;			/* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
117 	uint32 W_AM3;			/* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
118 	uint32 W_TA3;			/* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
119 	uint32 W_IMG_CTRL4;		/* 0x1B4 32 R/W WISHBONE Image4 Control register */
120 	uint32 W_BA4;			/* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
121 	uint32 W_AM4;			/* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
122 	uint32 W_TA4;			/* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
123 	uint32 W_IMG_CTRL5;		/* 0x1C4 32 R/W WISHBONE Image5 Control register */
124 	uint32 W_BA5;			/* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
125 	uint32 W_AM5;			/* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
126 	uint32 W_TA5;			/* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
127 	uint32 W_ERR_CS;		/* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
128 	uint32 W_ERR_ADDR;		/* 0x1D8 32 R WISHBONE Erroneous Address register */
129 	uint32 W_ERR_DATA;		/* 0x1DC 32 R WISHBONE Erroneous Data register */
130 	uint32 CNF_ADDR;		/* 0x1E0 32 R/W Configuration Cycle register */
131 	uint32 CNF_DATA;		/* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
133 	uint32 INT_ACK;			/* 0x1E8 32 R Interrupt Acknowledge register */
134 	uint32 ICR;			/* 0x1EC 32 R/W Interrupt Control register */
135 	uint32 ISR;			/* 0x1F0 32 R/W Interrupt Status register */
143 #define PCI_INT_PROP_EN		(1 << 0)	/* Interrupt Propagation Enable */
151 #define PCI_INT_PROP_ST		(1 << 0)	/* Interrupt Propagation Status */
158 #define SPIH_CTLR_INTR		(1 << 0)	/* SPI Host Controller Core Interrupt */
163 #define SPIH_CS			(1 << 0)	/* SPI Chip Select (active low) */
168 #define SPIH_STATE_MASK		0x30		/* SPI Transfer State Machine state mask */
173 #define SPIH_RFEMPTY		(1 << 0)	/* SPI Read FIFO Empty */
181 #define SPI_SPIN_BOUND		0xf4240		/* 1 million */