Lines Matching +full:4 +full:ghz +full:- +full:coexistence
2 * Broadcom device-specific manifest constants.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: bcmdevs.h 701163 2017-05-23 22:21:03Z $
111 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
112 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
114 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */
115 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */
127 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */
129 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */
130 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */
131 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
133 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */
134 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */
136 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */
154 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
155 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */
171 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */
174 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
175 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
179 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
180 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
182 #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */
183 #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */
184 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */
185 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */
338 #define BCM43349_D11N2G_ID 0x43e7 /* 43349 802.11n 2.4Ghz band id */
339 #define BCM43349_D11N5G_ID 0x43e8 /* 43349 802.11n 5Ghz band id */
468 /* DEPRECATED but still referenced in components - start */
471 /* DEPRECATED but still referenced in components - end */
677 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
679 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
680 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
711 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */
720 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
726 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
743 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
754 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
760 #define BFL2_WLCX_ATLAS 0x00000040 /* Board flag to initialize ECI for WLCX on FL-ATLAS */
761 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */
762 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace
766 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
767 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
768 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
770 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
774 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
791 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */
800 /* SROM 11 - 11ac boardflag definitions */
803 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
808 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
810 #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
811 #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
812 #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
837 /* acphy, to use backed off gaintbl for lte-coex */
839 /* acphy, to use backed off gaintbl for lte-coex */
842 #define BFL3_1X1_RSDB_ANT 0x01000000 /* to find if 2-ant RSDB board or 1-ant RSDB board */
852 #define BFL3_EXT_LPO_ISCLOCK 0x02000000 /* External LPO is clock, not x-tal */
864 #define BFL4_SROM12_4dBPAD (1 << 0) /* To distinguigh between normal and 4dB pad board */
868 #define BFL4_SROM13_CCK_SPUR_EN (1 << 4) /* using cck spur reduction setting in 4366 */
899 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
900 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
902 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */
903 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */
904 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */
905 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */
919 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */
921 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
923 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
924 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
930 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */