Lines Matching refs:W_REG
146 W_REG(osh, &pmu->min_res_mask, (min_mask | current_res_state)); in si_switch_pmu_dependency()
155 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
156 W_REG(osh, &pmu->res_updn_timer, PMU_4364_SAVE_RESTORE_UPDNTIME_1x1); in si_switch_pmu_dependency()
160 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
176 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
177 W_REG(osh, &pmu->res_updn_timer, in si_switch_pmu_dependency()
190 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
208 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
209 W_REG(osh, &pmu->res_updn_timer, in si_switch_pmu_dependency()
223 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
239 W_REG(osh, &pmu->max_res_mask, max_mask); in si_switch_pmu_dependency()
240 W_REG(osh, &pmu->min_res_mask, min_mask); in si_switch_pmu_dependency()
323 W_REG(osh, &pmu->ILPPeriod, ilp_period); in si_pmu_ulp_ilp_config()
361 W_REG(osh, &pmu->res_table_sel, in si_pmu_ds1_res_init()
363 W_REG(osh, &pmu->res_updn_timer, in si_pmu_ds1_res_init()
406 W_REG(osh, &pmu->min_res_mask, min_res_mask); in si_pmu_set_min_res_mask()
466 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_update()
474 W_REG(osh, &pmu->pmu_statstimer_ctrl, stats_timer_ctrl); in si_pmustatstimer_update()
475 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_update()
599 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_dump()
628 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_start()
653 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_stop()
676 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_clear()
677 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_clear()
707 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_clear_overflow()
736 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_read()