Lines Matching +full:hw +full:- +full:settle +full:- +full:time
3 * of the SiliconBackplane-based Broadcom chips.
7 * Copyright (C) 1999-2017, Broadcom Corporation
28 * <<Broadcom-WL-IPTag/Open:>>
30 * $Id: hndpmu.c 700652 2017-05-20 02:44:31Z $
99 * 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
100 * hardware supports this), if no hw support drive strength is not programmed.
111 * but the bit definitions are chip-specific. We are keeping this function available in si_sdiod_drive_strength_init()
143 current_res_state = R_REG(osh, &pmu->res_state); in si_switch_pmu_dependency()
144 min_mask = R_REG(osh, &pmu->min_res_mask); in si_switch_pmu_dependency()
145 max_mask = R_REG(osh, &pmu->max_res_mask); in si_switch_pmu_dependency()
146 W_REG(osh, &pmu->min_res_mask, (min_mask | current_res_state)); in si_switch_pmu_dependency()
150 if (CHIPID(sih->chip) == BCM4364_CHIP_ID) { in si_switch_pmu_dependency()
155 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
156 W_REG(osh, &pmu->res_updn_timer, PMU_4364_SAVE_RESTORE_UPDNTIME_1x1); in si_switch_pmu_dependency()
160 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
175 if (CHIPID(sih->chip) == BCM4364_CHIP_ID) { in si_switch_pmu_dependency()
176 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
177 W_REG(osh, &pmu->res_updn_timer, in si_switch_pmu_dependency()
190 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
207 if (CHIPID(sih->chip) == BCM4364_CHIP_ID) { in si_switch_pmu_dependency()
208 W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE); in si_switch_pmu_dependency()
209 W_REG(osh, &pmu->res_updn_timer, in si_switch_pmu_dependency()
223 W_REG(osh, &cc->sr1_control0, in si_switch_pmu_dependency()
239 W_REG(osh, &pmu->max_res_mask, max_mask); in si_switch_pmu_dependency()
240 W_REG(osh, &pmu->min_res_mask, min_mask); in si_switch_pmu_dependency()
242 /* Add some delay; allow resources to come up and settle. */ in si_switch_pmu_dependency()
279 ilpcycles_per_sec = crinfo->ilpcycles_per_sec; in si_pmu_ulp_exit_cb()
292 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_pmu_ulp_chipconfig()
323 W_REG(osh, &pmu->ILPPeriod, ilp_period); in si_pmu_ulp_ilp_config()
345 switch (CHIPID(sih->chip)) { in si_pmu_ds1_res_init()
356 while (pmu_res_updown_table_sz--) { in si_pmu_ds1_res_init()
361 W_REG(osh, &pmu->res_table_sel, in si_pmu_ds1_res_init()
363 W_REG(osh, &pmu->res_updn_timer, in si_pmu_ds1_res_init()
378 switch (CHIPID(sih->chip)) { in si_pmu_wake_bit_offset()
406 W_REG(osh, &pmu->min_res_mask, min_res_mask); in si_pmu_set_min_res_mask()
441 * //core-n active duration : pmu_rsrc_state(CORE_RDY_AUX)
443 * //core-n active duration : pmu_rsrc_state(CORE_RDY_AUX)
451 //deep-sleep duration : pmu_rsrc_state(XTAL_PU)
453 //deep-sleep entry count : pmu_rsrc_state(XTAL_PU)
455 //core-n active duration : pmu_rsrc_state(CORE_RDY_MAIN)
457 //core-n active duration : pmu_rsrc_state(CORE_RDY_MAIN)
466 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_update()
474 W_REG(osh, &pmu->pmu_statstimer_ctrl, stats_timer_ctrl); in si_pmustatstimer_update()
475 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_update()
494 OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_int_enable()
516 AND_REG(osh, &pmu->pmuintmask0, ~PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_int_disable()
541 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_init()
549 OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_init()
576 pmucapabilities = R_REG(osh, &pmu->pmucapabilities); in si_pmustatstimer_dump()
577 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_dump()
578 AlpPeriod = R_REG(osh, &pmu->slowclkperiod); in si_pmustatstimer_dump()
579 ILPPeriod = R_REG(osh, &pmu->ILPPeriod); in si_pmustatstimer_dump()
586 pmuintstatus = R_REG(osh, &pmu->pmuintstatus); in si_pmustatstimer_dump()
587 pmuintmask0 = R_REG(osh, &pmu->pmuintmask0); in si_pmustatstimer_dump()
589 PMU_ERROR(("%s : TIME %d\n", __FUNCTION__, current_time_ms)); in si_pmustatstimer_dump()
596 pmuintmask0, pmuintstatus, PMUREV(sih->pmurev))); in si_pmustatstimer_dump()
599 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_dump()
600 stat_timer_ctrl = R_REG(osh, &pmu->pmu_statstimer_ctrl); in si_pmustatstimer_dump()
601 stat_timer_N = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_dump()
628 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_start()
629 OR_REG(osh, &pmu->pmu_statstimer_ctrl, PMU_ST_ENAB << PMU_ST_EN_SHIFT); in si_pmustatstimer_start()
653 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_stop()
654 AND_REG(osh, &pmu->pmu_statstimer_ctrl, ~(PMU_ST_ENAB << PMU_ST_EN_SHIFT)); in si_pmustatstimer_stop()
676 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_clear()
677 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_clear()
703 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_clear_overflow()
707 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_clear_overflow()
708 timerN = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_clear_overflow()
710 PMU_ERROR(("pmustatstimer overflow clear - timerid : %d\n", i)); in si_pmustatstimer_clear_overflow()
736 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_read()
737 stats_timer_N = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_read()