2  * Misc utility routines for accessing PMU corerev specific features
39  * They refer to different revisions of the PMU (which is at revision 18 @ Apr 25, 2012)
129 	pmuregs_t *pmu;  in si_switch_pmu_dependency()  local
135 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_switch_pmu_dependency()
138 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_switch_pmu_dependency()
141 	ASSERT(pmu != NULL);  in si_switch_pmu_dependency()
143 	current_res_state = R_REG(osh, &pmu->res_state);  in si_switch_pmu_dependency()
144 	min_mask = R_REG(osh, &pmu->min_res_mask);  in si_switch_pmu_dependency()
145 	max_mask = R_REG(osh, &pmu->max_res_mask);  in si_switch_pmu_dependency()
146 	W_REG(osh, &pmu->min_res_mask, (min_mask | current_res_state));  in si_switch_pmu_dependency()
155 			W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE);  in si_switch_pmu_dependency()
156 			W_REG(osh, &pmu->res_updn_timer, PMU_4364_SAVE_RESTORE_UPDNTIME_1x1);  in si_switch_pmu_dependency()
176 				W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE);  in si_switch_pmu_dependency()
177 				W_REG(osh, &pmu->res_updn_timer,  in si_switch_pmu_dependency()
208 				W_REG(osh, &pmu->res_table_sel, RES4364_SR_SAVE_RESTORE);  in si_switch_pmu_dependency()
209 				W_REG(osh, &pmu->res_updn_timer,  in si_switch_pmu_dependency()
238 	si_pmu_resdeptbl_upd(sih, osh, pmu, pmu_res_depend_table, pmu_res_depend_table_sz);  in si_switch_pmu_dependency()
239 	W_REG(osh, &pmu->max_res_mask, max_mask);  in si_switch_pmu_dependency()
240 	W_REG(osh, &pmu->min_res_mask, min_mask);  in si_switch_pmu_dependency()
241 	si_pmu_wait_for_steady_state(sih, osh, pmu);  in si_switch_pmu_dependency()
321 	pmuregs_t *pmu;  in si_pmu_ulp_ilp_config()  local
322 	pmu = si_setcoreidx(sih, si_findcoreidx(sih, PMU_CORE_ID, 0));  in si_pmu_ulp_ilp_config()
323 	W_REG(osh, &pmu->ILPPeriod, ilp_period);  in si_pmu_ulp_ilp_config()
327 /** Initialize DS1 PMU hardware resources */
331 	pmuregs_t *pmu;  in si_pmu_ds1_res_init()  local
336 	/* Remember original core before switch to chipc/pmu */  in si_pmu_ds1_res_init()
339 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmu_ds1_res_init()
341 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_ds1_res_init()
343 	ASSERT(pmu != NULL);  in si_pmu_ds1_res_init()
361 		W_REG(osh, &pmu->res_table_sel,  in si_pmu_ds1_res_init()
363 		W_REG(osh, &pmu->res_updn_timer,  in si_pmu_ds1_res_init()
393 	pmuregs_t *pmu;  in si_pmu_set_min_res_mask()  local
396 	/* Remember original core before switch to chipc/pmu */  in si_pmu_set_min_res_mask()
399 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmu_set_min_res_mask()
402 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_set_min_res_mask()
404 	ASSERT(pmu != NULL);  in si_pmu_set_min_res_mask()
406 	W_REG(osh, &pmu->min_res_mask, min_res_mask);  in si_pmu_set_min_res_mask()
438  * 8 pmu statistics timer default map
462 si_pmustatstimer_update(osl_t *osh, pmuregs_t *pmu, uint8 timerid)  in si_pmustatstimer_update()  argument
466 	W_REG(osh, &pmu->pmu_statstimer_addr, timerid);  in si_pmustatstimer_update()
474 	W_REG(osh, &pmu->pmu_statstimer_ctrl, stats_timer_ctrl);  in si_pmustatstimer_update()
475 	W_REG(osh, &pmu->pmu_statstimer_N, 0);  in si_pmustatstimer_update()
481 	pmuregs_t *pmu;  in si_pmustatstimer_int_enable()  local
485 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_int_enable()
488 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_int_enable()
490 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_int_enable()
492 	ASSERT(pmu != NULL);  in si_pmustatstimer_int_enable()
494 	OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK);  in si_pmustatstimer_int_enable()
503 	pmuregs_t *pmu;  in si_pmustatstimer_int_disable()  local
507 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_int_disable()
510 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_int_disable()
512 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_int_disable()
514 	ASSERT(pmu != NULL);  in si_pmustatstimer_int_disable()
516 	AND_REG(osh, &pmu->pmuintmask0, ~PMU_INT_STAT_TIMER_INT_MASK);  in si_pmustatstimer_int_disable()
525 	pmuregs_t *pmu;  in si_pmustatstimer_init()  local
532 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_init()
535 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_init()
537 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_init()
539 	ASSERT(pmu != NULL);  in si_pmustatstimer_init()
541 	core_cap_ext = R_REG(osh, &pmu->core_cap_ext);  in si_pmustatstimer_init()
546 		si_pmustatstimer_update(osh, pmu, i);  in si_pmustatstimer_init()
549 	OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK);  in si_pmustatstimer_init()
558 	pmuregs_t *pmu;  in si_pmustatstimer_dump()  local
567 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_dump()
570 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_dump()
572 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_dump()
574 	ASSERT(pmu != NULL);  in si_pmustatstimer_dump()
576 	pmucapabilities = R_REG(osh, &pmu->pmucapabilities);  in si_pmustatstimer_dump()
577 	core_cap_ext = R_REG(osh, &pmu->core_cap_ext);  in si_pmustatstimer_dump()
578 	AlpPeriod = R_REG(osh, &pmu->slowclkperiod);  in si_pmustatstimer_dump()
579 	ILPPeriod = R_REG(osh, &pmu->ILPPeriod);  in si_pmustatstimer_dump()
586 	pmuintstatus = R_REG(osh, &pmu->pmuintstatus);  in si_pmustatstimer_dump()
587 	pmuintmask0 = R_REG(osh, &pmu->pmuintmask0);  in si_pmustatstimer_dump()
599 		W_REG(osh, &pmu->pmu_statstimer_addr, i);  in si_pmustatstimer_dump()
600 		stat_timer_ctrl = R_REG(osh, &pmu->pmu_statstimer_ctrl);  in si_pmustatstimer_dump()
601 		stat_timer_N = R_REG(osh, &pmu->pmu_statstimer_N);  in si_pmustatstimer_dump()
613 	pmuregs_t *pmu;  in si_pmustatstimer_start()  local
617 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_start()
620 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_start()
622 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_start()
624 	ASSERT(pmu != NULL);  in si_pmustatstimer_start()
628 	W_REG(osh, &pmu->pmu_statstimer_addr, timerid);  in si_pmustatstimer_start()
629 	OR_REG(osh, &pmu->pmu_statstimer_ctrl, PMU_ST_ENAB << PMU_ST_EN_SHIFT);  in si_pmustatstimer_start()
638 	pmuregs_t *pmu;  in si_pmustatstimer_stop()  local
642 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_stop()
645 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_stop()
647 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_stop()
649 	ASSERT(pmu != NULL);  in si_pmustatstimer_stop()
653 	W_REG(osh, &pmu->pmu_statstimer_addr, timerid);  in si_pmustatstimer_stop()
654 	AND_REG(osh, &pmu->pmu_statstimer_ctrl, ~(PMU_ST_ENAB << PMU_ST_EN_SHIFT));  in si_pmustatstimer_stop()
663 	pmuregs_t *pmu;  in si_pmustatstimer_clear()  local
667 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_clear()
670 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_clear()
672 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_clear()
674 	ASSERT(pmu != NULL);  in si_pmustatstimer_clear()
676 	W_REG(osh, &pmu->pmu_statstimer_addr, timerid);  in si_pmustatstimer_clear()
677 	W_REG(osh, &pmu->pmu_statstimer_N, 0);  in si_pmustatstimer_clear()
690 	pmuregs_t *pmu;  in si_pmustatstimer_clear_overflow()  local
694 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_clear_overflow()
697 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_clear_overflow()
699 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_clear_overflow()
701 	ASSERT(pmu != NULL);  in si_pmustatstimer_clear_overflow()
703 	core_cap_ext = R_REG(osh, &pmu->core_cap_ext);  in si_pmustatstimer_clear_overflow()
707 		W_REG(osh, &pmu->pmu_statstimer_addr, i);  in si_pmustatstimer_clear_overflow()
708 		timerN = R_REG(osh, &pmu->pmu_statstimer_N);  in si_pmustatstimer_clear_overflow()
722 	pmuregs_t *pmu;  in si_pmustatstimer_read()  local
727 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_read()
730 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_read()
732 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_read()
734 	ASSERT(pmu != NULL);  in si_pmustatstimer_read()
736 	W_REG(osh, &pmu->pmu_statstimer_addr, timerid);  in si_pmustatstimer_read()
737 	stats_timer_N = R_REG(osh, &pmu->pmu_statstimer_N);  in si_pmustatstimer_read()
748 	pmuregs_t *pmu;  in si_pmustatstimer_cfg_src_num()  local
752 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_cfg_src_num()
755 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_cfg_src_num()
757 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_cfg_src_num()
759 	ASSERT(pmu != NULL);  in si_pmustatstimer_cfg_src_num()
762 	si_pmustatstimer_update(osh, pmu, timerid);  in si_pmustatstimer_cfg_src_num()
771 	pmuregs_t *pmu;  in si_pmustatstimer_cfg_cnt_mode()  local
775 	/* Remember original core before switch to chipc/pmu */  in si_pmustatstimer_cfg_cnt_mode()
778 		pmu = si_setcore(sih, PMU_CORE_ID, 0);  in si_pmustatstimer_cfg_cnt_mode()
780 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_cfg_cnt_mode()
782 	ASSERT(pmu != NULL);  in si_pmustatstimer_cfg_cnt_mode()
785 	si_pmustatstimer_update(osh, pmu, timerid);  in si_pmustatstimer_cfg_cnt_mode()