Lines Matching refs:sih
56 si_lhl_setup(si_t *sih, osl_t *osh) in si_lhl_setup() argument
58 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_lhl_setup()
61 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0); in si_lhl_setup()
63 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2); in si_lhl_setup()
68 LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL); in si_lhl_setup()
69 LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL); in si_lhl_setup()
70 LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT); in si_lhl_setup()
71 LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL); in si_lhl_setup()
72 } else if (BCM4347_CHIP(sih->chip)) { in si_lhl_setup()
73 if (LHL_IS_PSMODE_1(sih)) { in si_lhl_setup()
74 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_1); in si_lhl_setup()
76 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0); in si_lhl_setup()
79 LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL_4347); in si_lhl_setup()
80 LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL); in si_lhl_setup()
81 LHL_REG(sih, lhl_top_pwrdn_ctl_adr, in si_lhl_setup()
83 LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL); in si_lhl_setup()
94 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
97 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_GPIO1_GPIO_PIN], ~0, in si_lhl_setup()
99 LHL_REG(sih, gpio_int_en_port_adr[0], in si_lhl_setup()
101 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
104 si_gci_set_functionsel(sih, 1, CC4347_FNSEL_SAMEASPIN); in si_lhl_setup()
108 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
110 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_PERST_GPIO_PIN], ~0, in si_lhl_setup()
113 LHL_REG(sih, gpio_int_en_port_adr[0], in si_lhl_setup()
115 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
119 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
121 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_CLKREQ_GPIO_PIN], ~0, in si_lhl_setup()
125 LHL_REG(sih, gpio_int_en_port_adr[0], in si_lhl_setup()
127 LHL_REG(sih, gpio_int_st_port_adr[0], in si_lhl_setup()
134 si_lhl_set_lpoclk(si_t *sih, osl_t *osh, uint32 lpo_force) in si_lhl_set_lpoclk() argument
141 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in si_lhl_set_lpoclk()
155 LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, 0); in si_lhl_set_lpoclk()
160 LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, 0); in si_lhl_set_lpoclk()
165 LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, 0); in si_lhl_set_lpoclk()
170 LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, 0); in si_lhl_set_lpoclk()
178 LHL_REG(sih, lhl_clk_det_ctl_adr, in si_lhl_set_lpoclk()
183 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN, 0); in si_lhl_set_lpoclk()
184 LHL_REG(sih, lhl_clk_det_ctl_adr, in si_lhl_set_lpoclk()
202 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, 0); in si_lhl_set_lpoclk()
203 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN, in si_lhl_set_lpoclk()
225 LHL_REG(sih, lhl_main_ctl_adr, in si_lhl_set_lpoclk()
246 LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, EXTLPO_BUF_PD); in si_lhl_set_lpoclk()
250 LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, LPO1_PD_EN); in si_lhl_set_lpoclk()
251 LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_SEL, LPO1_PD_SEL_VAL); in si_lhl_set_lpoclk()
254 LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, LPO2_PD_EN); in si_lhl_set_lpoclk()
255 LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_SEL, LPO2_PD_SEL_VAL); in si_lhl_set_lpoclk()
258 LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, OSC_32k_PD); in si_lhl_set_lpoclk()
261 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06, LPO_SEL, 0); in si_lhl_set_lpoclk()
271 si_lhl_timer_config(si_t *sih, osl_t *osh, int timer_type) in si_lhl_timer_config() argument
277 origidx = si_coreidx(sih); in si_lhl_timer_config()
278 if (AOB_ENAB(sih)) { in si_lhl_timer_config()
279 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_lhl_timer_config()
281 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_lhl_timer_config()
289 LHL_REG(sih, lhl_wl_mactim0_intrp_adr, in si_lhl_timer_config()
296 PMU_REG(sih, mac_res_req_mask, ~0, si_pmu_rsrc_macphy_clk_deps(sih, osh, 0)); in si_lhl_timer_config()
299 HND_PMU_SYNC_WR(sih, pmu, pmu, osh, in si_lhl_timer_config()
300 PMUREGADDR(sih, pmu, pmu, mac_res_req_timer), in si_lhl_timer_config()
303 if (si_numd11coreunits(sih) > 1) { in si_lhl_timer_config()
304 LHL_REG(sih, lhl_wl_mactim1_intrp_adr, in si_lhl_timer_config()
308 PMU_REG(sih, mac_res_req_mask1, ~0, in si_lhl_timer_config()
309 si_pmu_rsrc_macphy_clk_deps(sih, osh, 1)); in si_lhl_timer_config()
311 HND_PMU_SYNC_WR(sih, pmu, pmu, osh, in si_lhl_timer_config()
312 PMUREGADDR(sih, pmu, pmu, mac_res_req_timer1), in si_lhl_timer_config()
320 LHL_REG(sih, lhl_wl_armtim0_intrp_adr, in si_lhl_timer_config()
325 PMU_REG(sih, res_req_mask, ~0, si_pmu_rsrc_ht_avail_clk_deps(sih, osh)); in si_lhl_timer_config()
330 HND_PMU_SYNC_WR(sih, pmu, pmu, osh, in si_lhl_timer_config()
331 PMUREGADDR(sih, pmu, pmu, res_req_timer), in si_lhl_timer_config()
337 si_setcoreidx(sih, origidx); in si_lhl_timer_config()
341 si_lhl_timer_enable(si_t *sih) in si_lhl_timer_enable() argument
344 PMU_REG(sih, pmuintctrl0, PMU_INTC_ALP_REQ, PMU_INTC_ALP_REQ); in si_lhl_timer_enable()
346 PMU_REG(sih, pmuintmask0, RSRC_INTR_MASK_TIMER_INT_0, RSRC_INTR_MASK_TIMER_INT_0); in si_lhl_timer_enable()
348 LHL_REG(sih, lhl_main_ctl_adr, LHL_FAST_WRITE_EN, LHL_FAST_WRITE_EN); in si_lhl_timer_enable()
350 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_USE_LHL_TIMER, PCTL_EXT_USE_LHL_TIMER); in si_lhl_timer_enable()
354 si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period) in si_lhl_ilp_config() argument
357 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_lhl_ilp_config()
358 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in si_lhl_ilp_config()
366 si_lhl_disable_sdio_wakeup(si_t *sih) in si_lhl_disable_sdio_wakeup() argument
369 LHL_REG(sih, gpio_int_en_port_adr[0], (1 << ULP_SDIO_CMD_PIN), 0); in si_lhl_disable_sdio_wakeup()
372 LHL_REG(sih, gpio_int_st_port_adr[0], (1 << ULP_SDIO_CMD_PIN), (1 << ULP_SDIO_CMD_PIN)); in si_lhl_disable_sdio_wakeup()
376 si_lhl_enable_sdio_wakeup(si_t *sih, osl_t *osh) in si_lhl_enable_sdio_wakeup() argument
381 gciregs = si_setcore(sih, GCI_CORE_ID, 0); in si_lhl_enable_sdio_wakeup()
383 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_lhl_enable_sdio_wakeup()
410 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_lhl_enable_sdio_wakeup()
533 si_set_lv_sleep_mode_lhl_config_4369(si_t *sih) in si_set_lv_sleep_mode_lhl_config_4369() argument
536 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0); in si_set_lv_sleep_mode_lhl_config_4369()
543 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val); in si_set_lv_sleep_mode_lhl_config_4369()