61 		LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0);  in si_lhl_setup()
63 		LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2);  in si_lhl_setup()
68 		LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL);  in si_lhl_setup()
69 		LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL);  in si_lhl_setup()
70 		LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT);  in si_lhl_setup()
71 		LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL);  in si_lhl_setup()
74 			LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_1);  in si_lhl_setup()
76 			LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0);  in si_lhl_setup()
79 		LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL_4347);  in si_lhl_setup()
80 		LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL);  in si_lhl_setup()
81 		LHL_REG(sih, lhl_top_pwrdn_ctl_adr,  in si_lhl_setup()
83 		LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL);  in si_lhl_setup()
94 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
97 		LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_GPIO1_GPIO_PIN], ~0,  in si_lhl_setup()
99 		LHL_REG(sih, gpio_int_en_port_adr[0],  in si_lhl_setup()
101 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
108 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
110 		LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_PERST_GPIO_PIN], ~0,  in si_lhl_setup()
113 		LHL_REG(sih, gpio_int_en_port_adr[0],  in si_lhl_setup()
115 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
119 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
121 		LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_CLKREQ_GPIO_PIN], ~0,  in si_lhl_setup()
125 		LHL_REG(sih, gpio_int_en_port_adr[0],  in si_lhl_setup()
127 		LHL_REG(sih, gpio_int_st_port_adr[0],  in si_lhl_setup()
155 			LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, 0);  in si_lhl_set_lpoclk()
160 			LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, 0);  in si_lhl_set_lpoclk()
165 			LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, 0);  in si_lhl_set_lpoclk()
170 			LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, 0);  in si_lhl_set_lpoclk()
178 	LHL_REG(sih, lhl_clk_det_ctl_adr,  in si_lhl_set_lpoclk()
183 	LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN, 0);  in si_lhl_set_lpoclk()
184 	LHL_REG(sih, lhl_clk_det_ctl_adr,  in si_lhl_set_lpoclk()
202 	LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, 0);  in si_lhl_set_lpoclk()
203 	LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN,  in si_lhl_set_lpoclk()
225 	LHL_REG(sih, lhl_main_ctl_adr,  in si_lhl_set_lpoclk()
246 		LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, EXTLPO_BUF_PD);  in si_lhl_set_lpoclk()
250 		LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, LPO1_PD_EN);  in si_lhl_set_lpoclk()
251 		LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_SEL, LPO1_PD_SEL_VAL);  in si_lhl_set_lpoclk()
254 		LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, LPO2_PD_EN);  in si_lhl_set_lpoclk()
255 		LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_SEL, LPO2_PD_SEL_VAL);  in si_lhl_set_lpoclk()
258 		LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, OSC_32k_PD);  in si_lhl_set_lpoclk()
289 		LHL_REG(sih, lhl_wl_mactim0_intrp_adr,  in si_lhl_timer_config()
304 			LHL_REG(sih, lhl_wl_mactim1_intrp_adr,  in si_lhl_timer_config()
320 		LHL_REG(sih, lhl_wl_armtim0_intrp_adr,  in si_lhl_timer_config()
348 	LHL_REG(sih, lhl_main_ctl_adr, LHL_FAST_WRITE_EN, LHL_FAST_WRITE_EN);  in si_lhl_timer_enable()
369 	LHL_REG(sih, gpio_int_en_port_adr[0], (1 << ULP_SDIO_CMD_PIN), 0);  in si_lhl_disable_sdio_wakeup()
372 	LHL_REG(sih, gpio_int_st_port_adr[0], (1 << ULP_SDIO_CMD_PIN), (1 << ULP_SDIO_CMD_PIN));  in si_lhl_disable_sdio_wakeup()