238 typedef struct dhd_bus {  struct
239 	dhd_pub_t	*dhd;	/**< pointer to per hardware (dongle) unique instance */
240 	struct pci_dev  *rc_dev;	/* pci RC device handle */
241 	struct pci_dev  *dev;		/* pci device handle */
243 	dll_t		flowring_active_list; /* constructed list of tx flowring queues */
245 	uint64		active_list_last_process_ts;
249 	si_t		*sih;			/* Handle for SI calls */
250 	char		*vars;			/* Variables (from CIS and/or other) */
251 	uint		varsz;			/* Size of variables buffer */
252 	uint32		sbaddr;			/* Current SB window pointer (-1, invalid) */
253 	sbpcieregs_t	*reg;			/* Registers for PCIE core */
255 	uint		armrev;			/* CPU core revision */
256 	uint		coreid;			/* CPU core id */
257 	uint		ramrev;			/* SOCRAM core revision */
258 	uint32		ramsize;		/* Size of RAM in SOCRAM (bytes) */
259 	uint32		orig_ramsize;		/* Size of RAM in SOCRAM (bytes) */
260 	bool		ramsize_adjusted;	/* flag to note adjustment, so that
264 	uint32		srmemsize;		/* Size of SRMEM */
266 	uint32		bus;			/* gSPI or SDIO bus */
267 	uint32		intstatus;		/* Intstatus bits (events) pending */
268 	bool		dpc_sched;		/* Indicates DPC schedule (intrpt rcvd) */
269 	bool		fcstate;		/* State of dongle flow-control */
271 	uint16		cl_devid;		/* cached devid for dhdsdio_probe_attach() */
272 	char		*fw_path;		/* module_param: path to firmware image */
273 	char		*nv_path;		/* module_param: path to nvram vars file */
275 	struct pktq	txq;			/* Queue length used for flow-control */
277 	bool		intr;			/* Use interrupts */
278 	bool		ipend;			/* Device interrupt is pending */
279 	bool		intdis;			/* Interrupts disabled by isr */
280 	uint		intrcount;		/* Count of device interrupt callbacks */
281 	uint		lastintrs;		/* Count as of last watchdog timer */
283 	dhd_console_t	console;		/* Console output polling support */
284 	uint		console_addr;		/* Console address from shared struct */
286 	bool		alp_only;		/* Don't use HT clock (ALP only) */
288 	bool		remap;		/* Contiguous 1MB RAM: 512K socram + 512K devram
292 	uint32		resetinstr;
293 	uint32		dongle_ram_base;
295 	ulong		shared_addr;
296 	pciedev_shared_t	*pcie_sh;
297 	uint32		dma_rxoffset;
298 	volatile char	*regs;		/* pci device memory va */
299 	volatile char	*tcm;		/* pci device memory va */
300 	osl_t		*osh;
301 	uint32		nvram_csm;	/* Nvram checksum */
302 	uint16		pollrate;
303 	uint16  polltick;
305 	volatile uint32  *pcie_mb_intr_addr;
306 	volatile uint32  *pcie_mb_intr_2_addr;
307 	void    *pcie_mb_intr_osh;
308 	bool	sleep_allowed;
310 	wake_counts_t	wake_counts;
313 	ring_sh_info_t	ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
315 	uint8	h2d_ring_count;
316 	uint8	d2h_ring_count;
317 	uint32  ringmem_ptr;
318 	uint32  ring_state_ptr;
320 	uint32 d2h_dma_scratch_buffer_mem_addr;
322 	uint32 h2d_mb_data_ptr_addr;
323 	uint32 d2h_mb_data_ptr_addr;
326 	uint32 def_intmask;
327 	uint32 d2h_mb_mask;
328 	uint32 pcie_mailbox_mask;
329 	uint32 pcie_mailbox_int;
330 	bool	ltrsleep_on_unload;
331 	uint	wait_for_d3_ack;
332 	uint16	max_tx_flowrings;
333 	uint16	max_submission_rings;
334 	uint16	max_completion_rings;
335 	uint16	max_cmn_rings;
336 	uint32	rw_index_sz;
337 	bool	db1_for_mb;
339 	dhd_timeout_t doorbell_timer;
340 	bool	device_wake_state;
341 	bool	irq_registered;
342 	bool	d2h_intr_method;
348 	uint8 no_cfg_restore;
350 	struct_pcie_register_event pcie_event;
355 	bool read_shm_fail;
379 	enum dhd_bus_low_power_state bus_low_power_state;  argument
380 	uint32  hostready_count; /* Number of hostready issued */
382 	bool	oob_presuspend;
384 	dhdpcie_config_save_t saved_config;
385 	ulong resume_intr_enable_count;
386 	ulong dpc_intr_enable_count;
387 	ulong isr_intr_disable_count;
388 	ulong suspend_intr_disable_count;
389 	ulong dpc_return_busdown_count;
390 	ulong non_ours_irq_count;
392 	ulong oob_intr_count;
393 	ulong oob_intr_enable_count;
394 	ulong oob_intr_disable_count;
395 	uint64 last_oob_irq_time;
396 	uint64 last_oob_irq_enable_time;
397 	uint64 last_oob_irq_disable_time;
399 	uint64 isr_entry_time;
400 	uint64 isr_exit_time;
401 	uint64 dpc_sched_time;
402 	uint64 dpc_entry_time;
403 	uint64 dpc_exit_time;
404 	uint64 resched_dpc_time;
405 	uint64 last_d3_inform_time;
406 	uint64 last_process_ctrlbuf_time;
407 	uint64 last_process_flowring_time;
408 	uint64 last_process_txcpl_time;
409 	uint64 last_process_rxcpl_time;
410 	uint64 last_process_infocpl_time;
411 	uint64 last_process_edl_time;
412 	uint64 last_suspend_start_time;
413 	uint64 last_suspend_end_time;
414 	uint64 last_resume_start_time;
415 	uint64 last_resume_end_time;
416 	uint64 last_non_ours_irq_time;
417 	uint8 hwa_enab_bmap;
418 	bool  idma_enabled;
419 	bool  ifrm_enabled;
420 	bool  dar_enabled;
444 } dhd_bus_t;  argument
464 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);  argument