1502 	sbpcieregs_t *sbpcieregs;  in dhdpcie_dongle_attach()
1545 		sbpcieregs = (sbpcieregs_t*)(bus->regs);  in dhdpcie_dongle_attach()
1710 	sbpcieregs = (sbpcieregs_t*)(bus->regs);  in dhdpcie_dongle_attach()
2208 				OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0);  in dhdpcie_bus_release_dongle()
2213 			                         (sbpcieregs_t *) bus->regs);  in dhdpcie_bus_release_dongle()
5181 		OFFSETOF(sbpcieregs_t, ftn_ctrl.control), ~0,  in dhdpcie_enum_reg_init()
5186 		OFFSETOF(sbpcieregs_t, ftn_ctrl.intmask), ~0, 0);  in dhdpcie_enum_reg_init()
5189 		OFFSETOF(sbpcieregs_t, ftn_ctrl.intstatus), ~0,  in dhdpcie_enum_reg_init()
5191 			OFFSETOF(sbpcieregs_t, ftn_ctrl.intstatus), 0, 0));  in dhdpcie_enum_reg_init()
5195 		OFFSETOF(sbpcieregs_t, ftn_ctrl.msi_vector), ~0, 0);  in dhdpcie_enum_reg_init()
5198 		OFFSETOF(sbpcieregs_t, ftn_ctrl.msi_intmask), ~0, 0);  in dhdpcie_enum_reg_init()
5201 		OFFSETOF(sbpcieregs_t, ftn_ctrl.msi_intstatus), ~0,  in dhdpcie_enum_reg_init()
5203 			OFFSETOF(sbpcieregs_t, ftn_ctrl.msi_intstatus), 0, 0));  in dhdpcie_enum_reg_init()
5207 		OFFSETOF(sbpcieregs_t, ftn_ctrl.pwr_intmask), ~0, 0);  in dhdpcie_enum_reg_init()
5210 		OFFSETOF(sbpcieregs_t, ftn_ctrl.pwr_intstatus), ~0,  in dhdpcie_enum_reg_init()
5212 			OFFSETOF(sbpcieregs_t, ftn_ctrl.pwr_intstatus), 0, 0));  in dhdpcie_enum_reg_init()
5216 		OFFSETOF(sbpcieregs_t, ftn_ctrl.mbox_intmask), ~0, 0);  in dhdpcie_enum_reg_init()
5219 		OFFSETOF(sbpcieregs_t, ftn_ctrl.mbox_intstatus), ~0,  in dhdpcie_enum_reg_init()
5221 			OFFSETOF(sbpcieregs_t, ftn_ctrl.mbox_intstatus), 0, 0));  in dhdpcie_enum_reg_init()
5813 		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,  in dhdpcie_bus_doiovar()
5815 		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0,  in dhdpcie_bus_doiovar()
5820 		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,  in dhdpcie_bus_doiovar()
5823 			OFFSETOF(sbpcieregs_t, configdata), 0, 0);  in dhdpcie_bus_doiovar()
7233 		OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);  in dhdpcie_force_alp()
7236 			OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, 0);  in dhdpcie_force_alp()
7249 	si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,  in dhdpcie_set_l1_entry_time()
7252 		OFFSETOF(sbpcieregs_t, configdata), 0, 0);  in dhdpcie_set_l1_entry_time()
7254 	si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0,  in dhdpcie_set_l1_entry_time()
7669 	sbpcieregs_t *pcieregs;  in dhdpcie_dongle_host_get_handshake_address()
7844 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_pre_wd_reset_sequence()
7849 		pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);  in dhdpcie_dongle_host_pre_wd_reset_sequence()
7863 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_post_wd_reset_sequence()
7869 		pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);  in dhdpcie_dongle_host_post_wd_reset_sequence()
7912 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_pre_chipid_access_sequence()
7919 		pcieregs = (sbpcieregs_t*)(regva);  in dhdpcie_dongle_host_pre_chipid_access_sequence()
11306 			OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_LINK_STATUS);  in dhdpcie_cto_init()
11309 			OFFSETOF(sbpcieregs_t, configdata), 0, 0);  in dhdpcie_cto_init()
11326 			OFFSETOF(sbpcieregs_t, ctoctrl), ~0,  in dhdpcie_cto_init()
11334 			OFFSETOF(sbpcieregs_t, ctoctrl), ~0, 0);  in dhdpcie_cto_init()
12813 			(uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg1),  in dhd_pcie_debug_info_dump()
12815 				OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg1), 0, 0),  in dhd_pcie_debug_info_dump()
12816 			(uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg2),  in dhd_pcie_debug_info_dump()
12818 				OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg2), 0, 0),  in dhd_pcie_debug_info_dump()
12819 			(uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg3),  in dhd_pcie_debug_info_dump()
12821 				OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg3), 0, 0),  in dhd_pcie_debug_info_dump()
12822 			(uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg4),  in dhd_pcie_debug_info_dump()
12824 				OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg4), 0, 0)));  in dhd_pcie_debug_info_dump()
12826 			(uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_code_logreg),  in dhd_pcie_debug_info_dump()
12828 				OFFSETOF(sbpcieregs_t, u.pcie2.err_code_logreg), 0, 0)));  in dhd_pcie_debug_info_dump()