1342 		OSL_PCI_WRITE_CONFIG(osh, i << 2, sizeof(uint32), bus->saved_config.header[i]);  in dhdpcie_config_restore()
1344 	OSL_PCI_WRITE_CONFIG(osh, PCI_CFG_CMD, sizeof(uint32), bus->saved_config.header[1]);  in dhdpcie_config_restore()
1348 			sizeof(uint32), bus->saved_config.pmcsr);  in dhdpcie_config_restore()
1350 	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_CAP, sizeof(uint32), bus->saved_config.msi_cap);  in dhdpcie_config_restore()
1352 			bus->saved_config.msi_addr0);  in dhdpcie_config_restore()
1354 			sizeof(uint32), bus->saved_config.msi_addr1);  in dhdpcie_config_restore()
1356 			sizeof(uint32), bus->saved_config.msi_data);  in dhdpcie_config_restore()
1359 			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat);  in dhdpcie_config_restore()
1361 			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat2);  in dhdpcie_config_restore()
1363 			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat);  in dhdpcie_config_restore()
1365 			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat2);  in dhdpcie_config_restore()
1368 			sizeof(uint32), bus->saved_config.l1pm0);  in dhdpcie_config_restore()
1370 			sizeof(uint32), bus->saved_config.l1pm1);  in dhdpcie_config_restore()
1373 			bus->saved_config.bar0_win);  in dhdpcie_config_restore()
1374 	dhdpcie_setbar1win(bus, bus->saved_config.bar1_win);  in dhdpcie_config_restore()
1390 		bus->saved_config.header[i] = OSL_PCI_READ_CONFIG(osh, i << 2, sizeof(uint32));  in dhdpcie_config_save()
1393 	bus->saved_config.pmcsr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32));  in dhdpcie_config_save()
1395 	bus->saved_config.msi_cap = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_CAP,  in dhdpcie_config_save()
1397 	bus->saved_config.msi_addr0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_L,  in dhdpcie_config_save()
1399 	bus->saved_config.msi_addr1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_H,  in dhdpcie_config_save()
1401 	bus->saved_config.msi_data = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_DATA,  in dhdpcie_config_save()
1404 	bus->saved_config.exp_dev_ctrl_stat = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1406 	bus->saved_config.exp_dev_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1408 	bus->saved_config.exp_link_ctrl_stat = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1410 	bus->saved_config.exp_link_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1413 	bus->saved_config.l1pm0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL1,  in dhdpcie_config_save()
1415 	bus->saved_config.l1pm1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL2,  in dhdpcie_config_save()
1418 	bus->saved_config.bar0_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN,  in dhdpcie_config_save()
1420 	bus->saved_config.bar1_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR1_WIN,  in dhdpcie_config_save()