7669 	sbpcieregs_t *pcieregs;  in dhdpcie_dongle_host_get_handshake_address()  local
7671 	pcieregs = si_setcore(sih, PCIE2_CORE_ID, 0);  in dhdpcie_dongle_host_get_handshake_address()
7672 	if (!pcieregs) {  in dhdpcie_dongle_host_get_handshake_address()
7675 	addr->d2h = &pcieregs->u1.dar_64.d2h_msg_reg0;  in dhdpcie_dongle_host_get_handshake_address()
7676 	addr->h2d = &pcieregs->u1.dar_64.h2d_msg_reg0;  in dhdpcie_dongle_host_get_handshake_address()
7844 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_pre_wd_reset_sequence()  local
7849 		pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);  in dhdpcie_dongle_host_pre_wd_reset_sequence()
7853 			&pcieregs->u1.dar_64.h2d_msg_reg0, &reg_val);  in dhdpcie_dongle_host_pre_wd_reset_sequence()
7863 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_post_wd_reset_sequence()  local
7869 		pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);  in dhdpcie_dongle_host_post_wd_reset_sequence()
7873 			&pcieregs->u1.dar_64.h2d_msg_reg0, &reg_val);  in dhdpcie_dongle_host_post_wd_reset_sequence()
7887 			dhdpcie_handshake_msg_reg_read(sih, osh, &pcieregs->u1.dar_64.d2h_msg_reg0,  in dhdpcie_dongle_host_post_wd_reset_sequence()
7912 	sbpcieregs_t *pcieregs = NULL;  in dhdpcie_dongle_host_pre_chipid_access_sequence()  local
7919 		pcieregs = (sbpcieregs_t*)(regva);  in dhdpcie_dongle_host_pre_chipid_access_sequence()
7922 		W_REG(osh, &pcieregs->u1.dar_64.h2d_msg_reg0, reg_val);  in dhdpcie_dongle_host_pre_chipid_access_sequence()
7936 			reg_val = R_REG(osh, &pcieregs->u1.dar_64.d2h_msg_reg0);  in dhdpcie_dongle_host_pre_chipid_access_sequence()