Lines Matching refs:cr4regs_t
12468 cr4regs_t *cr4regs; in dhd_pcie_dump_wrapper_regs()
12490 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corecontrol), val)); in dhd_pcie_dump_wrapper_regs()
12493 (uint)OFFSETOF(cr4regs_t, corecapabilities), val)); in dhd_pcie_dump_wrapper_regs()
12495 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corestatus), val)); in dhd_pcie_dump_wrapper_regs()
12497 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmiisrst), val)); in dhd_pcie_dump_wrapper_regs()
12499 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmimask), val)); in dhd_pcie_dump_wrapper_regs()
12501 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, isrmask), val)); in dhd_pcie_dump_wrapper_regs()
12503 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, swintreg), val)); in dhd_pcie_dump_wrapper_regs()
12505 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, intstatus), val)); in dhd_pcie_dump_wrapper_regs()
12507 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, cyclecnt), val)); in dhd_pcie_dump_wrapper_regs()
12509 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, inttimer), val)); in dhd_pcie_dump_wrapper_regs()
12511 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, clk_ctl_st), val)); in dhd_pcie_dump_wrapper_regs()
12513 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, powerctl), val)); in dhd_pcie_dump_wrapper_regs()