Lines Matching refs:cr4_regs
1477 volatile uint32 *cr4_regs; in dhdpcie_bus_mpu_disable() local
1479 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_mpu_disable()
1480 if (cr4_regs == NULL) { in dhdpcie_bus_mpu_disable()
1484 if (R_REG(bus->osh, cr4_regs + ARMCR4REG_CORECAP) & ACC_MPU_MASK) { in dhdpcie_bus_mpu_disable()
1486 W_REG(bus->osh, cr4_regs + ARMCR4REG_MPUCTRL, 0); in dhdpcie_bus_mpu_disable()
7332 volatile uint32 *cr4_regs; in dhdpcie_bus_download_state() local
7370 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_download_state()
7372 if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && in dhdpcie_bus_download_state()
7391 } else if (cr4_regs == NULL) { /* no CR4 present on chip */ in dhdpcie_bus_download_state()
7451 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, in dhdpcie_bus_download_state()
7453 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, in dhdpcie_bus_download_state()
7455 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, in dhdpcie_bus_download_state()
7457 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, in dhdpcie_bus_download_state()