Lines Matching refs:DHD_ERROR
679 DHD_ERROR(("%s: buscorerev=%d chipid=0x%x\n", in dhdpcie_chip_support_msi()
719 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
737 DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
745 DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
757 DHD_ERROR(("%s: dhdpcie_sromotp_customvar failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
761 DHD_ERROR(("%s:customvar2 is not OTPed" in dhdpcie_bus_attach()
772 DHD_ERROR(("%s: Not going to enumerate this module as " in dhdpcie_bus_attach()
785 DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
789 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhdpcie_bus_attach()
941 DHD_ERROR(("failed to start PCIe Loopback Test!!! " in dhd_bus_dmaxfer_lpbk()
947 DHD_ERROR(("failed to check PCIe Loopback Test!!! " in dhd_bus_dmaxfer_lpbk()
952 DHD_ERROR(("successful to check PCIe Loopback Test" in dhd_bus_dmaxfer_lpbk()
988 DHD_ERROR(("isr_entry_time="SEC_USEC_FMT in dhd_bus_query_dpc_sched_errors()
1013 DHD_ERROR(("%s: trying to clear intstatus after D3 Ack\n", __FUNCTION__)); in dhdpcie_bus_intstatus()
1029 DHD_ERROR(("%s: Device is removed or Link is down.\n", __FUNCTION__)); in dhdpcie_bus_intstatus()
1030 DHD_ERROR(("%s: INTSTAT : 0x%x INTMASK : 0x%x.\n", in dhdpcie_bus_intstatus()
1161 DHD_ERROR(("%s: ##### CTO RECOVERY REPORTED BY DONGLE " in dhdpcie_bus_isr()
1268 DHD_ERROR(("%s: Already in state %u \n", __FUNCTION__, cur_state)); in dhdpcie_set_pwr_state()
1281 DHD_ERROR(("%s: Invalid power state transition !\n", __FUNCTION__)); in dhdpcie_set_pwr_state()
1302 DHD_ERROR(("%s: power transition failed ! Current state is %u \n", in dhdpcie_set_pwr_state()
1306 DHD_ERROR(("%s: power transition to %u success \n", in dhdpcie_set_pwr_state()
1481 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); in dhdpcie_bus_mpu_disable()
1517 DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1532 DHD_ERROR(("%s : failed to read SPROM control register\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1553 DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1565 DHD_ERROR(("%s: error - pre chipid access sequence error %d\n", in dhdpcie_dongle_attach()
1577 DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1583 DHD_ERROR(("Disable CTO\n")); in dhdpcie_dongle_attach()
1588 DHD_ERROR(("Enable CTO\n")); in dhdpcie_dongle_attach()
1593 DHD_ERROR(("Disable CTO\n")); in dhdpcie_dongle_attach()
1635 DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1651 DHD_ERROR(("%s: ARM is not halted,FW is already running! Abort.\n", in dhdpcie_dongle_attach()
1723 DHD_ERROR(("%s: failed to find SYSMEM memory!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1746 DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1752 DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__)); in dhdpcie_dongle_attach()
1821 DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n", in dhdpcie_dongle_attach()
1837 DHD_ERROR(("%s : invalid ramsize %d(0x%x) is returned from dongle\n", in dhdpcie_dongle_attach()
1842 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n", in dhdpcie_dongle_attach()
1976 DHD_ERROR(("%s: Disabling wdtick before dhd deinit\n", in dhdpcie_advertise_bus_cleanup()
1988 DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n", in dhdpcie_advertise_bus_cleanup()
2003 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhdpcie_bus_remove_prep()
2193 DHD_ERROR(("%s : Skip release dongle due to linkdown \n", __FUNCTION__)); in dhdpcie_bus_release_dongle()
2265 DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n", in dhdpcie_bus_dongle_setmemsize()
2301 DHD_ERROR(("%s: already down by net_dev_reset\n", __FUNCTION__)); in dhd_bus_stop()
2308 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhd_bus_stop()
2409 DHD_ERROR(("----- CHIP 4358 A0 -----\n")); in concate_revision_bcm4358()
2412 DHD_ERROR(("----- CHIP 4358 A1 -----\n")); in concate_revision_bcm4358()
2417 DHD_ERROR(("----- CHIP 4358 A3 -----\n")); in concate_revision_bcm4358()
2422 DHD_ERROR(("----- Unknown chip version, ver=%x -----\n", chiprev)); in concate_revision_bcm4358()
2437 DHD_ERROR(("%s: chipver_tag %s \n", __FUNCTION__, chipver_tag)); in concate_revision_bcm4358()
2442 DHD_ERROR(("----- Board Rev [%d]-----\n", system_rev)); in concate_revision_bcm4358()
2462 DHD_ERROR(("----- CHIP 4359 B0 -----\n")); in concate_revision_bcm4359()
2465 DHD_ERROR(("----- CHIP 4359 B1 -----\n")); in concate_revision_bcm4359()
2468 DHD_ERROR(("----- CHIP 4359 C0 -----\n")); in concate_revision_bcm4359()
2471 DHD_ERROR(("----- Unknown chip version, ver=%x -----\n", chip_ver)); in concate_revision_bcm4359()
2682 DHD_ERROR(("invalid size/addr combination\n")); in dhd_parse_board_information_bcm()
2688 DHD_ERROR(("invalid size/addr combination\n")); in dhd_parse_board_information_bcm()
2738 DHD_ERROR(("failed to parse information (vid=%d, boardtype=%d)\n", in dhd_parse_board_information_bcm()
2757 DHD_ERROR(("%s:bus(%p) or bus->sih is NULL\n", __FUNCTION__, bus)); in dhd_find_naming_info_by_chip_rev()
2764 DHD_ERROR(("%s:failed to parse board information\n", __FUNCTION__)); in dhd_find_naming_info_by_chip_rev()
2836 DHD_ERROR(("%s:failed to find extension for nvram and firmware\n", __FUNCTION__)); in concate_revision_bcm4361()
2874 DHD_ERROR(("%s:failed to find extension for nvram and firmware\n", __FUNCTION__)); in concate_revision_bcm4375()
2893 DHD_ERROR(("%s:Bus is Invalid\n", __FUNCTION__)); in concate_revision()
2898 DHD_ERROR(("fw_path or nv_path is null.\n")); in concate_revision()
2920 DHD_ERROR(("REVISION SPECIFIC feature is not required\n")); in concate_revision()
2963 DHD_ERROR(("%s: fail to concatnate revison \n", in dhd_bus_download_firmware()
2973 DHD_ERROR(("%s: firmware path=%s, nvram path=%s\n", in dhd_bus_download_firmware()
3017 DHD_ERROR(("%s: revid is not found %x\n", __FUNCTION__, in dhdpcie_download_firmware()
3023 DHD_ERROR(("%s: unsupported device %x\n", __FUNCTION__, in dhdpcie_download_firmware()
3069 DHD_ERROR(("%s: dhd_tcm_test_enable %u\n", __FUNCTION__, dhd_tcm_test_enable)); in dhdpcie_download_code_file()
3072 DHD_ERROR(("dhd_bus_tcm_test failed\n")); in dhdpcie_download_code_file()
3076 DHD_ERROR(("%s: download firmware %s\n", __FUNCTION__, pfw_path)); in dhdpcie_download_code_file()
3088 DHD_ERROR(("%s: get file size fails ! \n", __FUNCTION__)); in dhdpcie_download_code_file()
3094 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); in dhdpcie_download_code_file()
3108 DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len)); in dhdpcie_download_code_file()
3114 DHD_ERROR(("%s: WARNING! reading beyond EOF, len=%d; read_len=%u;" in dhdpcie_download_code_file()
3142 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", in dhdpcie_download_code_file()
3149 DHD_ERROR(("%s: invalid address access to %x (offset end: %x)\n", in dhdpcie_download_code_file()
3212 DHD_ERROR(("%s: dhd_get_download_buffer len %d\n", __FUNCTION__, len)); in dhdpcie_download_nvram()
3224 DHD_ERROR(("%s: process_nvram_vars len %d\n", __FUNCTION__, len)); in dhdpcie_download_nvram()
3227 DHD_ERROR(("%s: invalid nvram size in process_nvram_vars \n", in dhdpcie_download_nvram()
3242 DHD_ERROR(("%s: error downloading vars: %d\n", in dhdpcie_download_nvram()
3273 DHD_ERROR(("%s: Failed to open firmware file\n", __FUNCTION__)); in dhdpcie_ramsize_read_image()
3279 DHD_ERROR(("%s: Failed to read %d bytes data\n", __FUNCTION__, len)); in dhdpcie_ramsize_read_image()
3321 DHD_ERROR(("%s: user restrict dongle ram size to %d.\n", __FUNCTION__, in dhdpcie_ramsize_adj()
3328 DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__)); in dhdpcie_ramsize_adj()
3348 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, search_len)); in dhdpcie_ramsize_adj()
3376 DHD_ERROR(("%s: Adjust dongle RAMSIZE to 0x%x\n", __FUNCTION__, in dhdpcie_ramsize_adj()
3408 DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__)); in _dhdpcie_download_firmware()
3416 DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__)); in _dhdpcie_download_firmware()
3423 DHD_ERROR(("%s:%d dongle image file download failed\n", __FUNCTION__, in _dhdpcie_download_firmware()
3434 DHD_ERROR(("%s:%d dongle image download failed\n", __FUNCTION__, __LINE__)); in _dhdpcie_download_firmware()
3444 DHD_ERROR(("%s:%d dongle nvram file download failed\n", __FUNCTION__, __LINE__)); in _dhdpcie_download_firmware()
3450 DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__)); in _dhdpcie_download_firmware()
3502 DHD_ERROR(("conlog: bufsize=0x%x\n", c->bufsize)); in dhdpcie_bus_readconsole()
3514 DHD_ERROR(("conlog: addr=0x%x, idx=0x%x, last=0x%x \n", c->log.buf, in dhdpcie_bus_readconsole()
3529 DHD_ERROR(("conlog: read error[1] ! \n")); in dhdpcie_bus_readconsole()
3536 DHD_ERROR(("conlog: read error[2] ! \n")); in dhdpcie_bus_readconsole()
3545 DHD_ERROR(("conlog: read error[3] ! \n")); in dhdpcie_bus_readconsole()
3584 DHD_ERROR(("%s: Dump Complete Console Buffer\n", __FUNCTION__)); in dhd_bus_dump_console_buffer()
3587 DHD_ERROR(("%s: Skip dump Console Buffer due to PCIe link down\n", __FUNCTION__)); in dhd_bus_dump_console_buffer()
3683 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize)); in dhdpcie_checkdied()
3690 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen)); in dhdpcie_checkdied()
3875 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__)); in dhdpcie_get_mem_dump()
3880 DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__)); in dhdpcie_get_mem_dump()
3890 DHD_ERROR(("%s: Out of memory (%d bytes)\n", in dhdpcie_get_mem_dump()
3902 DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret)); in dhdpcie_get_mem_dump()
3931 DHD_ERROR(("%s: PCIe link is down so skip\n", __FUNCTION__)); in dhdpcie_mem_dump()
3940 DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__)); in dhdpcie_mem_dump()
3945 DHD_ERROR(("%s: bus is down! can't collect mem dump. \n", __FUNCTION__)); in dhdpcie_mem_dump()
3956 DHD_ERROR(("%s: failed to get mem dump, err=%d\n", in dhdpcie_mem_dump()
3976 DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__)); in dhd_bus_get_mem_dump()
3990 DHD_ERROR(("%s bus is down\n", __FUNCTION__)); in dhd_bus_mem_dump()
4001 DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state, so skip\n", in dhd_bus_mem_dump()
4038 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhdpcie_bus_membytes()
4130 DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__, in dhd_bus_schedule_queue()
4138 DHD_ERROR((" %s : invalid flow_ring_node \n", __FUNCTION__)); in dhd_bus_schedule_queue()
4183 DHD_ERROR(("%s: dhd_tcpack_check_xmit() error.\n", in dhd_bus_schedule_queue()
4241 DHD_ERROR(("%s: Flow ring not intited yet \n", __FUNCTION__)); in dhd_bus_txdata()
4300 DHD_ERROR(("Dropping packet!! flowid %u status is %u\n", in dhd_bus_txdata()
4368 DHD_ERROR(("%s: Interface NOT started, previously stopped " in dhd_bus_start_queue()
4538 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhd_bus_cmn_writeshared()
4783 DHD_ERROR(("%s: Bypass pwr request\n", __FUNCTION__)); in dhd_bus_iovar_op()
4819 DHD_ERROR(("%s: Bypass pwr request clear\n", __FUNCTION__)); in dhd_bus_iovar_op()
5058 DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__)); in dhd_buzzz_dump_dngl()
5151 DHD_ERROR(("pcie_mdiosetblock: timed out\n")); in pcie2_mdiosetblock()
5231 DHD_ERROR(("******** Perform FLR ********\n")); in dhd_bus_perform_flr()
5247 DHD_ERROR(("Chip does not support FLR\n")); in dhd_bus_perform_flr()
5274 DHD_ERROR(("Set PCIE_SSRESET_DISABLE_BIT(%d) of PCIE_CFG_SUBSYSTEM_CONTROL(0x%x)\n", in dhd_bus_perform_flr()
5277 DHD_ERROR(("read_config: reg=0x%x read val=0x%x\n", PCIE_CFG_SUBSYSTEM_CONTROL, in dhd_bus_perform_flr()
5280 DHD_ERROR(("write_config: reg=0x%x write val=0x%x\n", PCIE_CFG_SUBSYSTEM_CONTROL, in dhd_bus_perform_flr()
5285 DHD_ERROR(("read_config: reg=0x%x read val=0x%x\n", PCIE_CFG_SUBSYSTEM_CONTROL, in dhd_bus_perform_flr()
5303 DHD_ERROR(("read_config: reg=0x%x read val=0x%x\n", in dhd_bus_perform_flr()
5310 DHD_ERROR(("ERROR: reg=0x%x bit %d is not cleared\n", in dhd_bus_perform_flr()
5315 DHD_ERROR(("%s cleared flr_force_fail flag\n", __FUNCTION__)); in dhd_bus_perform_flr()
5324 DHD_ERROR(("******** FLR Succedeed ********\n")); in dhd_bus_perform_flr()
5346 DHD_ERROR(("******** Perform BP reset ********\n")); in dhd_bus_perform_bp_reset()
5386 DHD_ERROR(("ERROR: reg=0x%x bit %d is not cleared\n", in dhd_bus_perform_bp_reset()
5406 DHD_ERROR(("ERROR: reg=0x%x bit %d is not cleared\n", in dhd_bus_perform_bp_reset()
5421 DHD_ERROR(("******** BP reset Succedeed ********\n")); in dhd_bus_perform_bp_reset()
5440 DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__)); in dhd_bus_devreset()
5441 DHD_ERROR(("%s: making dhdpub up FALSE\n", __FUNCTION__)); in dhd_bus_devreset()
5475 DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", in dhd_bus_devreset()
5497 DHD_ERROR(("%s: host clock stop failed: %d\n", in dhd_bus_devreset()
5506 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhd_bus_devreset()
5527 DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", in dhd_bus_devreset()
5551 DHD_ERROR(("%s: host clock stop failed: %d\n", in dhd_bus_devreset()
5559 DHD_ERROR(("%s: WLAN OFF Done\n", __FUNCTION__)); in dhd_bus_devreset()
5564 DHD_ERROR(("%s: == Power ON ==\n", __FUNCTION__)); in dhd_bus_devreset()
5569 DHD_ERROR(("%s: dhdpcie_bus_clock_start OK\n", in dhd_bus_devreset()
5578 DHD_ERROR(("%s: host pcie clock enable failed: %d\n", in dhd_bus_devreset()
5593 DHD_ERROR(("%s: host configuration restore failed: %d\n", in dhd_bus_devreset()
5600 DHD_ERROR(("%s: dhdpcie_bus_resource_alloc failed: %d\n", in dhd_bus_devreset()
5607 DHD_ERROR(("%s: dhdpcie_bus_dongle_attach failed: %d\n", in dhd_bus_devreset()
5614 DHD_ERROR(("%s: dhd_bus_request_irq failed: %d\n", in dhd_bus_devreset()
5627 DHD_ERROR(("%s: dhd_bus_start: %d\n", in dhd_bus_devreset()
5635 DHD_ERROR(("%s: Enabling wdtick after dhd init\n", in dhd_bus_devreset()
5639 DHD_ERROR(("%s: WLAN Power On Done\n", __FUNCTION__)); in dhd_bus_devreset()
5641 DHD_ERROR(("%s: what should we do here\n", __FUNCTION__)); in dhd_bus_devreset()
5649 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhd_bus_devreset()
5747 DHD_ERROR(("Bad argument. Possible values: 0, 1, 2 & 3\n")); in dhdpcie_set_dma_ring_indices()
5755 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_set_dma_ring_indices()
5842 DHD_ERROR(("Invalid size/addr combination \n")); in dhdpcie_bus_doiovar()
5861 DHD_ERROR(("Invalid size/addr combination \n")); in dhdpcie_bus_doiovar()
5879 DHD_ERROR(("Invalid size/addr combination \n")); in dhdpcie_bus_doiovar()
5898 DHD_ERROR(("Invalid size/addr combination \n")); in dhdpcie_bus_doiovar()
5908 DHD_ERROR(("supported only in pcie gen2\n")); in dhdpcie_bus_doiovar()
5916 DHD_ERROR(("pcie2_mdioop failed.\n")); in dhdpcie_bus_doiovar()
5924 DHD_ERROR(("supported only in pcie gen2\n")); in dhdpcie_bus_doiovar()
5929 DHD_ERROR(("pcie2_mdioop failed.\n")); in dhdpcie_bus_doiovar()
6003 DHD_ERROR(("%s:Wait Timedout, dhd_bus_busy_state = 0x%x\n", in dhdpcie_bus_doiovar()
6059 DHD_ERROR(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n", in dhdpcie_bus_doiovar()
6083 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d bytes at 0x%08x\n", in dhdpcie_bus_doiovar()
6085 DHD_ERROR(("%s: socram enable %d, protect %d\n", in dhdpcie_bus_doiovar()
6095 DHD_ERROR(("%s: bad address 0x%08x, size 0x%08x\n", in dhdpcie_bus_doiovar()
6097 DHD_ERROR(("%s: socram range 0x%08x,size 0x%08x\n", in dhdpcie_bus_doiovar()
6111 DHD_ERROR(("%s: Need to disable remap for address 0x%08x\n", in dhdpcie_bus_doiovar()
6345 DHD_ERROR(("%s: invalid argument for devreset\n", __FUNCTION__)); in dhdpcie_bus_doiovar()
6353 DHD_ERROR(("%s: Bus is NOT up\n", __FUNCTION__)); in dhdpcie_bus_doiovar()
6410 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6428 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6446 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6515 DHD_ERROR(("%s: Set hang_report as %d\n", in dhdpcie_bus_doiovar()
6711 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_lpback_req()
6715 DHD_ERROR(("prot is not inited\n")); in dhdpcie_bus_lpback_req()
6719 DHD_ERROR(("not in a readystate to LPBK is not inited\n")); in dhdpcie_bus_lpback_req()
6735 DHD_ERROR(("%s: link is down\n", __FUNCTION__)); in dhd_bus_dump_dar_registers()
6747 DHD_ERROR(("%s: DAR not supported for corerev(%d) < 24\n", in dhd_bus_dump_dar_registers()
6759 DHD_ERROR(("%s: dar_clk_ctrl(0x%x:0x%x) dar_pwr_ctrl(0x%x:0x%x) dar_intstat(0x%x:0x%x)\n", in dhd_bus_dump_dar_registers()
6763 DHD_ERROR(("%s: dar_errlog(0x%x:0x%x) dar_erraddr(0x%x:0x%x) dar_pcie_mbint(0x%x:0x%x)\n", in dhd_bus_dump_dar_registers()
6777 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhd_bus_hostready()
6781 DHD_ERROR(("%s : Read PCICMD Reg: 0x%08X\n", __FUNCTION__, in dhd_bus_hostready()
6792 DHD_ERROR(("%s: Ring Hostready:%d\n", __FUNCTION__, bus->hostready_count)); in dhd_bus_hostready()
6829 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_suspend()
6833 DHD_ERROR(("prot is not inited\n")); in dhdpcie_bus_suspend()
6843 DHD_ERROR(("not in a readystate\n")); in dhdpcie_bus_suspend()
6849 DHD_ERROR(("Dongle is in reset state.\n")); in dhdpcie_bus_suspend()
6858 DHD_ERROR(("Bus is already in SUSPEND state.\n")); in dhdpcie_bus_suspend()
6861 DHD_ERROR(("Bus is already in RESUME state.\n")); in dhdpcie_bus_suspend()
6872 DHD_ERROR(("%s: PCIe link was down, state=%d\n", in dhdpcie_bus_suspend()
6878 DHD_ERROR(("%s: Entering suspend state\n", __FUNCTION__)); in dhdpcie_bus_suspend()
6882 DHD_ERROR(("%s: Disabling wdtick before going to suspend\n", in dhdpcie_bus_suspend()
6889 DHD_ERROR(("Tx Request is not ended\n")); in dhdpcie_bus_suspend()
6944 DHD_ERROR(("%s: D3 ACK trying again intstatus=%x" in dhdpcie_bus_suspend()
6976 DHD_ERROR(("%s: Got D3 Ack \n", __FUNCTION__)); in dhdpcie_bus_suspend()
6980 DHD_ERROR(("%s():Suspend failed because of wakelock" in dhdpcie_bus_suspend()
6984 DHD_ERROR(("%s: Enabling wdtick due to wakelock active\n", in dhdpcie_bus_suspend()
7054 DHD_ERROR(("%s: Inducing DROP OOB IRQ\n", __FUNCTION__)); in dhdpcie_bus_suspend()
7094 DHD_ERROR(("%s: resumed on timeout for D3 ACK%s d3_inform_cnt %d\n", in dhdpcie_bus_suspend()
7137 DHD_ERROR(("%s: Event HANG send up due to D3_ACK timeout\n", in dhdpcie_bus_suspend()
7154 DHD_ERROR(("%s: Entering resume state\n", __FUNCTION__)); in dhdpcie_bus_suspend()
7215 DHD_ERROR(("%s: Enabling wdtick after resume\n", in dhdpcie_bus_suspend()
7271 DHD_ERROR(("%s: len %d\n", __FUNCTION__, len)); in dhd_apply_d11_war_length()
7284 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_dmaxfer_req()
7288 DHD_ERROR(("prot is not inited\n")); in dhdpcie_bus_dmaxfer_req()
7292 DHD_ERROR(("not in a readystate to LPBK is not inited\n")); in dhdpcie_bus_dmaxfer_req()
7297 DHD_ERROR(("len is too small or too large\n")); in dhdpcie_bus_dmaxfer_req()
7341 DHD_ERROR(("%s: REGS/TCM addresses not initialized\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7347 DHD_ERROR(("%s: NULL sih!!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7375 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7384 DHD_ERROR(("%s: Failed to find SYSMEM core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7395 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7428 DHD_ERROR(("%s: error %d dongle host pre handshake\n", in dhdpcie_bus_download_state()
7432 DHD_ERROR(("%s: dongle host pre handshake successful, dl FW\n", in dhdpcie_bus_download_state()
7438 DHD_ERROR(("%s: Shared region not initialized\n", in dhdpcie_bus_download_state()
7444 DHD_ERROR(("%s: First pass console buffer read failed\n", in dhdpcie_bus_download_state()
7468 DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7475 DHD_ERROR(("%s: Failed to get random seed to write to TCM !\n", in dhdpcie_bus_download_state()
7481 DHD_ERROR(("%s: Failed to find ARM CA7 core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7491 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7497 DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7507 DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7514 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7522 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", in dhdpcie_bus_download_state()
7534 DHD_ERROR(("%s: Second pass console buffer read failed\n", in dhdpcie_bus_download_state()
7541 DHD_ERROR(("%s: error %d dongle host post handshake\n", in dhdpcie_bus_download_state()
7545 DHD_ERROR(("%s: FW download successful\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7558 DHD_ERROR(("%s: error %d dongle host validation\n", in dhdpcie_bus_download_state()
7566 DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7574 DHD_ERROR(("%s: Failed to get random seed to write to TCM !\n", in dhdpcie_bus_download_state()
7581 DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__)); in dhdpcie_bus_download_state()
7598 DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n", in dhdpcie_bus_download_state()
7600 DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n", in dhdpcie_bus_download_state()
7614 DHD_ERROR(("%s: Final pass console buffer read failed\n", in dhdpcie_bus_download_state()
7620 DHD_ERROR(("%s: error %d dongle_host_post_varswrite\n", in dhdpcie_bus_download_state()
7624 DHD_ERROR(("%s VARS done bit set, BL can jump to mainline FW\n", in dhdpcie_bus_download_state()
7641 DHD_ERROR(("%s: Shared region not initialized\n", in dhdpcie_bus_download_state()
7646 DHD_ERROR(("%s: Failure case console buffer read failed\n", in dhdpcie_bus_download_state()
7819 DHD_ERROR(("%s: TRX img validation check successful\n", in dhdpcie_dongle_host_chk_validation()
7822 DHD_ERROR(("%s: TRX img validation check failed\n", __FUNCTION__)); in dhdpcie_dongle_host_chk_validation()
7883 DHD_ERROR(("Waiting %d us for D2H_READY\n", in dhdpcie_dongle_host_post_wd_reset_sequence()
7895 DHD_ERROR(("%s: error - Waiting for D2H_READY timeout %d\n", in dhdpcie_dongle_host_post_wd_reset_sequence()
7933 DHD_ERROR(("Waiting %d us for D2H_READY\n", in dhdpcie_dongle_host_pre_chipid_access_sequence()
7943 DHD_ERROR(("%s: error - Waiting for D2H_READY timeout %d\n", in dhdpcie_dongle_host_pre_chipid_access_sequence()
8012 DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n", in dhdpcie_bus_write_vars()
8018 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__)); in dhdpcie_bus_write_vars()
8020 DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n", in dhdpcie_bus_write_vars()
8105 DHD_ERROR(("%s: Could not find ccode info from the nvram %s\n", in dhdpcie_downloadvars()
8123 DHD_ERROR(("%s: Invalid parameter format when parsing for %s\n", in dhdpcie_downloadvars()
8147 DHD_ERROR(("%s : PCI config header not normal.\n", __FUNCTION__)); in dhdpcie_find_pci_capability()
8154 DHD_ERROR(("%s : PCI CAP pointer not present.\n", __FUNCTION__)); in dhdpcie_find_pci_capability()
8161 DHD_ERROR(("%s : PCI CAP pointer is 0x00.\n", __FUNCTION__)); in dhdpcie_find_pci_capability()
8188 DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__)); in dhdpcie_pme_active()
8193 DHD_ERROR(("%s : pme_sts_ctrl 0x%x\n", __FUNCTION__, pme_csr)); in dhdpcie_pme_active()
8214 DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__)); in dhdpcie_pme_cap()
8220 DHD_ERROR(("%s : pme_cap 0x%x\n", __FUNCTION__, pme_cap)); in dhdpcie_pme_cap()
8236 DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__)); in dhdpcie_lcreg()
8267 DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__)); in dhdpcie_clkreq()
8295 DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__)); in dhd_dump_intr_counters()
8301 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__)); in dhd_dump_intr_counters()
8479 DHD_ERROR(("%s: Bad IF index: %d associated with flowid: %d\n", in dhd_bus_dump()
8558 DHD_ERROR(("%s: Induce AXI signature drop\n", __FUNCTION__)); in dhd_axi_sig_match()
8562 DHD_ERROR(("%s: axi_tcm_addr: 0x%x, tcm range: 0x%x ~ 0x%x\n", in dhd_axi_sig_match()
8572 DHD_ERROR(("%s: No AXI signature: 0x%x\n", in dhd_axi_sig_match()
8577 DHD_ERROR(("%s: No AXI shared tcm address debug info.\n", __FUNCTION__)); in dhd_axi_sig_match()
8596 DHD_ERROR(("%s: No AXI TCM address debug info.\n", __FUNCTION__)); in dhd_axi_error()
8610 DHD_ERROR(("%s: Read AXI data from TCM address\n", __FUNCTION__)); in dhd_axi_error()
8615 DHD_ERROR(("%s: out of memory !\n", __FUNCTION__)); in dhd_axi_error()
8622 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", in dhd_axi_error()
8631 DHD_ERROR(("%s: failed to copy etd axi error info, err=%d\n", in dhd_axi_error()
8651 DHD_ERROR(("%s: signature : 0x%x\n", __FUNCTION__, axi_err_v1->signature)); in dhd_log_dump_axi_error()
8652 DHD_ERROR(("%s: version : 0x%x\n", __FUNCTION__, axi_err_v1->version)); in dhd_log_dump_axi_error()
8653 DHD_ERROR(("%s: length : 0x%x\n", __FUNCTION__, axi_err_v1->length)); in dhd_log_dump_axi_error()
8654 DHD_ERROR(("%s: dma_fifo_valid_count : 0x%x\n", in dhd_log_dump_axi_error()
8656 DHD_ERROR(("%s: axi_errorlog_status : 0x%x\n", in dhd_log_dump_axi_error()
8658 DHD_ERROR(("%s: axi_errorlog_core : 0x%x\n", in dhd_log_dump_axi_error()
8660 DHD_ERROR(("%s: axi_errorlog_hi : 0x%x\n", in dhd_log_dump_axi_error()
8662 DHD_ERROR(("%s: axi_errorlog_lo : 0x%x\n", in dhd_log_dump_axi_error()
8664 DHD_ERROR(("%s: axi_errorlog_id : 0x%x\n", in dhd_log_dump_axi_error()
8669 DHD_ERROR(("%s: valid:%d : 0x%x\n", __FUNCTION__, i, dma_fifo.valid)); in dhd_log_dump_axi_error()
8670 DHD_ERROR(("%s: direction:%d : 0x%x\n", in dhd_log_dump_axi_error()
8672 DHD_ERROR(("%s: index:%d : 0x%x\n", in dhd_log_dump_axi_error()
8674 DHD_ERROR(("%s: dpa:%d : 0x%x\n", in dhd_log_dump_axi_error()
8676 DHD_ERROR(("%s: desc_lo:%d : 0x%x\n", in dhd_log_dump_axi_error()
8678 DHD_ERROR(("%s: desc_hi:%d : 0x%x\n", in dhd_log_dump_axi_error()
8680 DHD_ERROR(("%s: din:%d : 0x%x\n", in dhd_log_dump_axi_error()
8682 DHD_ERROR(("%s: dout:%d : 0x%x\n", in dhd_log_dump_axi_error()
8686 DHD_ERROR(("%s: ctrl1:%d : 0x%x\n", in dhd_log_dump_axi_error()
8688 DHD_ERROR(("%s: ctrl2:%d : 0x%x\n", in dhd_log_dump_axi_error()
8690 DHD_ERROR(("%s: addrlo:%d : 0x%x\n", in dhd_log_dump_axi_error()
8692 DHD_ERROR(("%s: addrhi:%d : 0x%x\n", in dhd_log_dump_axi_error()
8698 DHD_ERROR(("%s: Invalid AXI version: 0x%x\n", __FUNCTION__, (*(uint8 *)axi_err))); in dhd_log_dump_axi_error()
8748 DHD_ERROR(("mailbox communication not supported\n")); in dhd_bus_gen_devmb_intr()
8785 DHD_ERROR(("%s: trying to ring the doorbell after D3 inform %d\n", in dhd_bus_ringbell()
8792 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhd_bus_ringbell()
8826 DHD_ERROR(("%s: trying to ring the doorbell after D3 inform %d\n", in dhd_bus_ringbell_2()
8833 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhd_bus_ringbell_2()
8850 DHD_ERROR(("%s: trying to ring the doorbell after D3 inform %d\n", in dhdpcie_bus_ringbell_fast()
8857 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhdpcie_bus_ringbell_fast()
8884 DHD_ERROR(("%s: trying to ring the doorbell after D3 inform %d\n", in dhdpcie_bus_ringbell_2_fast()
8891 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhdpcie_bus_ringbell_2_fast()
8907 DHD_ERROR(("%s: trying to ring the doorbell after D3 inform %d\n", in dhd_bus_ringbell_oldpcie()
8914 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhd_bus_ringbell_oldpcie()
8973 DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__)); in dhd_bus_dpc()
9018 DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); in dhdpcie_send_mb_data()
9028 DHD_ERROR(("failure sending the H2D Mailbox message " in dhdpcie_send_mb_data()
9046 DHD_ERROR(("%s : waited 1ms for the dngl " in dhdpcie_send_mb_data()
9048 DHD_ERROR(("%s : MB transaction is still pending 0x%04x\n", in dhdpcie_send_mb_data()
9095 DHD_ERROR(("%s: D3_ACK Recieved\n", __FUNCTION__)); in dhd_bus_handle_d3_ack()
9105 DHD_ERROR(("%s: Inducing D3 ACK timeout\n", __FUNCTION__)); in dhd_bus_handle_d3_ack()
9118 DHD_ERROR(("FW trap has happened\n")); in dhd_bus_handle_mb_data()
9134 DHD_ERROR(("DS-ENTRY AFTER D3-ACK!!!!! QUITING\n")); in dhd_bus_handle_mb_data()
9135 DHD_ERROR(("%s: making DHD_BUS_DOWN\n", __FUNCTION__)); in dhd_bus_handle_mb_data()
9160 DHD_ERROR(("TEST HANG: Skip to process D3 ACK\n")); in dhd_bus_handle_mb_data()
9188 DHD_ERROR(("%s: Invalid D2H_MB_DATA: 0x%08x\n", in dhdpcie_handle_mb_data()
9197 DHD_ERROR(("FW trap has happened\n")); in dhdpcie_handle_mb_data()
9218 DHD_ERROR(("TEST HANG: Skip to process D3 ACK\n")); in dhdpcie_handle_mb_data()
9241 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__)); in dhdpcie_read_handle_mb_data()
9288 DHD_ERROR(("%s: D3 Ack Recieved. " in dhdpcie_bus_process_mailbox_intr()
9354 DHD_ERROR(("AXI Error happened\n")); in dhdpci_bus_read_frames()
9373 DHD_ERROR(("%s: Bus is in power save state (%d). " in dhdpci_bus_read_frames()
9438 DHD_ERROR(("%s: read SHM failed but intstatus is valid\n", __FUNCTION__)); in dhdpci_bus_read_frames()
9448 DHD_ERROR(("%s: Link is Down.\n", __FUNCTION__)); in dhdpci_bus_read_frames()
9482 DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid addr\n", in dhdpcie_tcm_valid()
9490 DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv)); in dhdpcie_tcm_valid()
9496 DHD_ERROR(("Contents of pciedev_shared_t structure are not matching.\n")); in dhdpcie_tcm_valid()
9552 DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid\n", in dhdpcie_readshared_console()
9554 DHD_ERROR(("Waited %u usec, dongle is not ready\n", tmo.elapsed)); in dhdpcie_readshared_console()
9558 DHD_ERROR(("%s:PCIe shared addr (0x%08x) read took %u usec " in dhdpcie_readshared_console()
9565 DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv)); in dhdpcie_readshared_console()
9601 DHD_ERROR(("%s: PCIe link might be down\n", __FUNCTION__)); in dhdpcie_readshared()
9613 DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid\n", in dhdpcie_readshared()
9615 DHD_ERROR(("Waited %u usec, dongle is not ready\n", tmo.elapsed)); in dhdpcie_readshared()
9630 DHD_ERROR(("PCIe shared addr (0x%08x) read took %u usec " in dhdpcie_readshared()
9637 DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv)); in dhdpcie_readshared()
9665 DHD_ERROR(("%s: pcie_shared version %d in dhd " in dhdpcie_readshared()
9680 DHD_ERROR(("%s: FW Supports IdleFlow ring managment!\n", in dhdpcie_readshared()
9724 DHD_ERROR(("%s FW has to support either dma indices or d2h sync\n", in dhdpcie_readshared()
9749 DHD_ERROR(("%s: rings_info_ptr is invalid 0x%x, skip reading ring info\n", in dhdpcie_readshared()
9778 DHD_ERROR(("dongle completion rings are invalid %d\n", in dhdpcie_readshared()
9783 DHD_ERROR(("dongle submission rings are invalid %d\n", in dhdpcie_readshared()
9788 DHD_ERROR(("dongle txflow rings are invalid %d\n", bus->max_tx_flowrings)); in dhdpcie_readshared()
9802 DHD_ERROR(("%s: Failed to allocate memory for dma'ing h2d indices" in dhdpcie_readshared()
9817 DHD_ERROR(("%s: Failed to allocate memory for dma'ing d2h indices" in dhdpcie_readshared()
9829 DHD_ERROR(("%s: Failed to alloc memory for Implicit DMA\n", in dhdpcie_readshared()
9842 DHD_ERROR(("%s: max H2D queues %d\n", in dhdpcie_readshared()
9870 DHD_ERROR(("Dongle EDL support: %u\n", bus->dhd->dongle_edl_support)); in dhdpcie_readshared()
9876 DHD_ERROR(("FW supports debug buf dest ? %s \n", in dhdpcie_readshared()
9887 DHD_ERROR(("FW supports HP2P ? %s \n", in dhdpcie_readshared()
10062 DHD_ERROR(("%s: Console buffer read failed\n", in dhd_bus_init()
10069 DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__)); in dhd_bus_init()
10140 DHD_ERROR(("%s: Supporting vendor %x device %x\n", __FUNCTION__, in dhdpcie_chipmatch()
10143 DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, in dhdpcie_chipmatch()
10302 DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, vendor, device)); in dhdpcie_chipmatch()
10339 DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev)); in dhdpcie_sromotp_customvar()
10347 DHD_ERROR(("%s: supported for chips" in dhdpcie_sromotp_customvar()
10399 DHD_ERROR(("%s: SPROM and OTP could not be found " in dhdpcie_sromotp_customvar()
10408 DHD_ERROR(("%s: SPROM and OTP could not be found " in dhdpcie_sromotp_customvar()
10429 DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n", in dhdpcie_sromotp_customvar()
10434 DHD_ERROR(("ChipCommon Regs. not initialized\n")); in dhdpcie_sromotp_customvar()
10450 DHD_ERROR(("%s: NVM Shadow is not intialized\n", __FUNCTION__)); in dhdpcie_sromotp_customvar()
10455 DHD_ERROR(("%s: Insufficient system memory of size %d\n", in dhdpcie_sromotp_customvar()
10551 DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev)); in dhdpcie_cc_nvmshadow()
10559 DHD_ERROR(("%s: cc_nvmdump cmd. supported for Olympic chips" in dhdpcie_cc_nvmshadow()
10615 DHD_ERROR(("%s: SPROM and OTP could not be found " in dhdpcie_cc_nvmshadow()
10623 DHD_ERROR(("%s: SPROM and OTP could not be found " in dhdpcie_cc_nvmshadow()
10649 DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n", in dhdpcie_cc_nvmshadow()
10655 DHD_ERROR(("ChipCommon Regs. not initialized\n")); in dhdpcie_cc_nvmshadow()
10674 DHD_ERROR(("%s: NVM Shadow is not intialized\n", __FUNCTION__)); in dhdpcie_cc_nvmshadow()
10781 DHD_ERROR(("%s: flowid is invalid %d, max %d\n", __FUNCTION__, in dhd_bus_flow_ring_create_response()
10788 DHD_ERROR(("%s: flow_ring_node is NULL\n", __FUNCTION__)); in dhd_bus_flow_ring_create_response()
10794 DHD_ERROR(("%s: flowid %d is different from the flowid " in dhd_bus_flow_ring_create_response()
10801 DHD_ERROR(("%s Flow create Response failure error status = %d \n", in dhd_bus_flow_ring_create_response()
10858 DHD_ERROR(("%s :Delete Pending flowid %u\n", __FUNCTION__, flow_ring_node->flowid)); in dhd_bus_flow_ring_delete_request()
10888 DHD_ERROR(("%s: flowid is invalid %d, max %d\n", __FUNCTION__, in dhd_bus_flow_ring_delete_response()
10895 DHD_ERROR(("%s: flow_ring_node is NULL\n", __FUNCTION__)); in dhd_bus_flow_ring_delete_response()
10901 DHD_ERROR(("%s: flowid %d is different from the flowid " in dhd_bus_flow_ring_delete_response()
10908 DHD_ERROR(("%s Flow Delete Response failure error status = %d \n", in dhd_bus_flow_ring_delete_response()
10964 DHD_ERROR(("%s Flow flush Response failure error status = %d \n", in dhd_bus_flow_ring_flush_response()
10971 DHD_ERROR(("%s: flowid is invalid %d, max %d\n", __FUNCTION__, in dhd_bus_flow_ring_flush_response()
10978 DHD_ERROR(("%s: flow_ring_node is NULL\n", __FUNCTION__)); in dhd_bus_flow_ring_flush_response()
10984 DHD_ERROR(("%s: flowid %d is different from the flowid " in dhd_bus_flow_ring_flush_response()
11032 DHD_ERROR(("%s :Flow Resume Request flow id %u\n", __FUNCTION__, flow_ring_node->flowid)); in dhd_bus_flow_ring_resume_request()
11055 DHD_ERROR(("%s Error Status = %d \n", in dhd_bus_flow_ring_resume_response()
11122 DHD_ERROR(("\nSuspending flowid %d\n", flow_ring_node->flowid)); in dhd_bus_idle_scan()
11337 DHD_ERROR(("%s: set CTO prevention and recovery enable/disable %d\n", in dhdpcie_cto_init()
11355 DHD_ERROR(("--- CTO Triggered --- %d\n", bus->pwr_req_ref)); in dhdpcie_cto_error_recovery()
11381 DHD_ERROR(("cto recovery fail\n")); in dhdpcie_cto_error_recovery()
11397 DHD_ERROR(("cto recovery reset 0x%x:SPROM_CFG_TO_SB_RST(0x%x) 0x%x\n", in dhdpcie_cto_error_recovery()
11402 DHD_ERROR(("cto recovery success 0x%x:SPROM_CFG_TO_SB_RST(0x%x) 0x%x\n", in dhdpcie_cto_error_recovery()
11435 DHD_ERROR(("%s: update flag bit (H2D_D11_TX_STATUS) failed\n", in dhdpcie_init_d11status()
11490 DHD_ERROR(("Invalid size/addr combination \n")); in dhd_pcie_dump_core_regs()
11492 DHD_ERROR(("[0x%08x]: 0x%08x\n", core_addr, value)); in dhd_pcie_dump_core_regs()
11548 DHD_ERROR(("ENABLING DW:%d\n", dw_option)); in dhdpcie_bus_enab_pcie_dw()
11578 DHD_ERROR(("Invalid size/addr combination \n")); in dhd_bus_readwrite_bp_addr()
11596 DHD_ERROR(("sbreg: Invalid uint addr: 0x%x \n", addr)); in dhd_sbreg_op()
11598 DHD_ERROR(("sbreg: addr:0x%x val:0x%x read:%d\n", addr, *val, read)); in dhd_sbreg_op()
11612 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_get_sssr_fifo_dump()
11615 DHD_ERROR(("%s: buf is NULL\n", __FUNCTION__)); in dhdpcie_get_sssr_fifo_dump()
11620 DHD_ERROR(("%s: fifo_size is 0\n", __FUNCTION__)); in dhdpcie_get_sssr_fifo_dump()
11634 DHD_ERROR(("%s: error in serialized_backplane_access\n", __FUNCTION__)); in dhdpcie_get_sssr_fifo_dump()
11652 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_get_sssr_dig_dump()
11655 DHD_ERROR(("%s: buf is NULL\n", __FUNCTION__)); in dhdpcie_get_sssr_dig_dump()
11660 DHD_ERROR(("%s: fifo_size is 0\n", __FUNCTION__)); in dhdpcie_get_sssr_dig_dump()
11671 DHD_ERROR(("%s: Error reading dig dump from dongle !\n", in dhdpcie_get_sssr_dig_dump()
11688 DHD_ERROR(("%s: Invalid uint addr: 0x%x \n", __FUNCTION__, in dhdpcie_get_sssr_dig_dump()
11756 DHD_ERROR(("%s: etd_evtlog tlv found, num_elements=%x; " in dhdpcie_get_etd_preserve_logs()
11762 DHD_ERROR(("%s: num event logs is zero! \n", __FUNCTION__)); in dhdpcie_get_etd_preserve_logs()
11767 DHD_ERROR(("%s: out of memory !\n", __FUNCTION__)); in dhdpcie_get_etd_preserve_logs()
11775 DHD_ERROR(("%s: Error reading invalid address\n", in dhdpcie_get_etd_preserve_logs()
11785 DHD_ERROR(("%s: Error reading event log array from dongle !\n", in dhdpcie_get_etd_preserve_logs()
11800 DHD_ERROR(("%s: Error reading invalid address\n", in dhdpcie_get_etd_preserve_logs()
11809 DHD_ERROR(("%s: Error reading event log buffer from dongle !\n", in dhdpcie_get_etd_preserve_logs()
11821 DHD_ERROR(("%s: Error getting trap log data in ETD !\n", __FUNCTION__)); in dhdpcie_get_etd_preserve_logs()
11832 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_resume_chipcommon_powerctrl()
11850 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_suspend_chipcommon_powerctrl()
11869 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_clear_intmask_and_timer()
11928 DHD_ERROR(("%s: sssr_d11_outofreset[%d] : %d after AND with " in dhdpcie_update_d11_status_from_trapdata()
11943 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_d11_check_outofreset()
11949 DHD_ERROR(("%s: skipping for core[%d] as 'addr' is NULL\n", in dhdpcie_d11_check_outofreset()
11959 DHD_ERROR(("%s: sssr_d11_outofreset[%d] : %d\n", in dhdpcie_d11_check_outofreset()
11974 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_d11_clear_clk_req()
11999 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_arm_clear_clk_req()
12024 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_pcie_clear_clk_req()
12044 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_pcie_send_ltrsleep()
12059 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_clear_clk_req()
12077 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_bring_d11_outofreset()
12118 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_sssr_dump_get_before_sr()
12148 DHD_ERROR(("%s\n", __FUNCTION__)); in dhdpcie_sssr_dump_get_after_sr()
12179 DHD_ERROR(("%s: SSSR not inited\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12184 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12190 DHD_ERROR(("%s: Collecting Dump before SR\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12192 DHD_ERROR(("%s: dhdpcie_sssr_dump_get_before_sr failed\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12207 DHD_ERROR(("%s: Collecting Dump after SR\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12209 DHD_ERROR(("%s: dhdpcie_sssr_dump_get_after_sr failed\n", __FUNCTION__)); in dhdpcie_sssr_dump()
12222 DHD_ERROR(("%s: SSSR not inited\n", __FUNCTION__)); in dhdpcie_fis_trigger()
12227 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__)); in dhdpcie_fis_trigger()
12251 DHD_ERROR(("%s: SSSR not inited\n", __FUNCTION__)); in dhdpcie_fis_dump()
12256 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__)); in dhdpcie_fis_dump()
12277 DHD_ERROR(("%s: Collecting Dump after SR\n", __FUNCTION__)); in dhdpcie_fis_dump()
12279 DHD_ERROR(("%s: dhdpcie_sssr_dump_get_after_sr failed\n", __FUNCTION__)); in dhdpcie_fis_dump()
12335 DHD_ERROR(("%s: use stored .rnd.in content\n", __FUNCTION__)); in dhdpcie_wrt_rnd()
12369 DHD_ERROR(("\n ------- DUMPING INTR enable/disable counters ------- \r\n")); in dhd_pcie_intr_count_dump()
12370 DHD_ERROR(("resume_intr_enable_count=%lu dpc_intr_enable_count=%lu\n", in dhd_pcie_intr_count_dump()
12372 DHD_ERROR(("isr_intr_disable_count=%lu suspend_intr_disable_count=%lu\n", in dhd_pcie_intr_count_dump()
12375 DHD_ERROR(("oob_intr_count=%lu oob_intr_enable_count=%lu oob_intr_disable_count=%lu\n", in dhd_pcie_intr_count_dump()
12378 DHD_ERROR(("oob_irq_num=%d last_oob_irq_time="SEC_USEC_FMT"\n", in dhd_pcie_intr_count_dump()
12381 DHD_ERROR(("last_oob_irq_enable_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12385 DHD_ERROR(("oob_irq_enabled=%d oob_gpio_level=%d\n", in dhd_pcie_intr_count_dump()
12389 DHD_ERROR(("dpc_return_busdown_count=%lu non_ours_irq_count=%lu\n", in dhd_pcie_intr_count_dump()
12393 DHD_ERROR(("\ncurrent_time="SEC_USEC_FMT"\n", in dhd_pcie_intr_count_dump()
12395 DHD_ERROR(("isr_entry_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12399 DHD_ERROR(("dpc_sched_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12403 DHD_ERROR(("dpc_entry_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12407 DHD_ERROR(("last_process_flowring_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12411 DHD_ERROR(("last_process_rxcpl_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12417 DHD_ERROR(("dpc_exit_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12421 DHD_ERROR(("last_d3_inform_time="SEC_USEC_FMT"\n", in dhd_pcie_intr_count_dump()
12424 DHD_ERROR(("\nlast_suspend_start_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12428 DHD_ERROR(("last_resume_start_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12434 DHD_ERROR(("logtrace_thread_entry_time="SEC_USEC_FMT in dhd_pcie_intr_count_dump()
12473 DHD_ERROR(("%s: Master wrapper Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12478 DHD_ERROR(("sbreg: addr:0x%x val:0x%x\n", wrapper_dump_list[i], val)); in dhd_pcie_dump_wrapper_regs()
12483 DHD_ERROR(("%s: ARM CR4 wrapper Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12486 DHD_ERROR(("sbreg: addr:0x%x val:0x%x\n", wrapper_dump_list[i], val)); in dhd_pcie_dump_wrapper_regs()
12488 DHD_ERROR(("%s: ARM CR4 core Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12490 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corecontrol), val)); in dhd_pcie_dump_wrapper_regs()
12492 DHD_ERROR(("reg:0x%x val:0x%x\n", in dhd_pcie_dump_wrapper_regs()
12495 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corestatus), val)); in dhd_pcie_dump_wrapper_regs()
12497 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmiisrst), val)); in dhd_pcie_dump_wrapper_regs()
12499 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmimask), val)); in dhd_pcie_dump_wrapper_regs()
12501 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, isrmask), val)); in dhd_pcie_dump_wrapper_regs()
12503 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, swintreg), val)); in dhd_pcie_dump_wrapper_regs()
12505 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, intstatus), val)); in dhd_pcie_dump_wrapper_regs()
12507 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, cyclecnt), val)); in dhd_pcie_dump_wrapper_regs()
12509 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, inttimer), val)); in dhd_pcie_dump_wrapper_regs()
12511 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, clk_ctl_st), val)); in dhd_pcie_dump_wrapper_regs()
12513 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, powerctl), val)); in dhd_pcie_dump_wrapper_regs()
12517 DHD_ERROR(("%s: ARM CA7 core Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12519 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(ca7regs_t, corecontrol), val)); in dhd_pcie_dump_wrapper_regs()
12521 DHD_ERROR(("reg:0x%x val:0x%x\n", in dhd_pcie_dump_wrapper_regs()
12524 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(ca7regs_t, corestatus), val)); in dhd_pcie_dump_wrapper_regs()
12526 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(ca7regs_t, tracecontrol), val)); in dhd_pcie_dump_wrapper_regs()
12528 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(ca7regs_t, clk_ctl_st), val)); in dhd_pcie_dump_wrapper_regs()
12530 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(ca7regs_t, powerctl), val)); in dhd_pcie_dump_wrapper_regs()
12533 DHD_ERROR(("%s: OOBR Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12544 DHD_ERROR(("reg: addr:%p val:0x%x\n", reg, val)); in dhd_pcie_dump_wrapper_regs()
12546 DHD_ERROR(("reg: addr:%p val:0x%x\n", reg, val)); in dhd_pcie_dump_wrapper_regs()
12548 DHD_ERROR(("reg: addr:%p val:0x%x\n", reg, val)); in dhd_pcie_dump_wrapper_regs()
12550 DHD_ERROR(("reg: addr:%p val:0x%x\n", reg, val)); in dhd_pcie_dump_wrapper_regs()
12554 DHD_ERROR(("%s: Second OOBR Reg\n", __FUNCTION__)); in dhd_pcie_dump_wrapper_regs()
12571 DHD_ERROR(("\n ------- SKIP DUMPING DMA Registers " in dhd_pcie_dma_info_dump()
12576 DHD_ERROR(("\n ------- DUMPING DMA Registers ------- \r\n")); in dhd_pcie_dma_info_dump()
12579 DHD_ERROR(("HostToDev TX: XmtCtrl=0x%08x XmtPtr=0x%08x\n", in dhd_pcie_dma_info_dump()
12582 DHD_ERROR((" : XmtAddrLow=0x%08x XmtAddrHigh=0x%08x\n", in dhd_pcie_dma_info_dump()
12585 DHD_ERROR((" : XmtStatus0=0x%08x XmtStatus1=0x%08x\n", in dhd_pcie_dma_info_dump()
12589 DHD_ERROR(("HostToDev RX: RcvCtrl=0x%08x RcvPtr=0x%08x\n", in dhd_pcie_dma_info_dump()
12592 DHD_ERROR((" : RcvAddrLow=0x%08x RcvAddrHigh=0x%08x\n", in dhd_pcie_dma_info_dump()
12595 DHD_ERROR((" : RcvStatus0=0x%08x RcvStatus1=0x%08x\n", in dhd_pcie_dma_info_dump()
12600 DHD_ERROR(("DevToHost TX: XmtCtrl=0x%08x XmtPtr=0x%08x\n", in dhd_pcie_dma_info_dump()
12603 DHD_ERROR((" : XmtAddrLow=0x%08x XmtAddrHigh=0x%08x\n", in dhd_pcie_dma_info_dump()
12606 DHD_ERROR((" : XmtStatus0=0x%08x XmtStatus1=0x%08x\n", in dhd_pcie_dma_info_dump()
12610 DHD_ERROR(("DevToHost RX: RcvCtrl=0x%08x RcvPtr=0x%08x\n", in dhd_pcie_dma_info_dump()
12613 DHD_ERROR((" : RcvAddrLow=0x%08x RcvAddrHigh=0x%08x\n", in dhd_pcie_dma_info_dump()
12616 DHD_ERROR((" : RcvStatus0=0x%08x RcvStatus1=0x%08x\n", in dhd_pcie_dma_info_dump()
12631 DHD_ERROR(("\n ------- DUMPING INTR Status and Masks ------- \r\n")); in dhd_pcie_dump_int_regs()
12635 DHD_ERROR(("intstatus=0x%x \n", intstatus)); in dhd_pcie_dump_int_regs()
12642 DHD_ERROR(("intstatus=0x%x intmask=0x%x \n", intstatus, intmask)); in dhd_pcie_dump_int_regs()
12649 DHD_ERROR(("intstatus=0x%x intmask=0x%x d2h_db0=0x%x\n", in dhd_pcie_dump_int_regs()
12654 DHD_ERROR(("intstatus=0x%x intmask=0x%x d2h_db0=0x%x\n", in dhd_pcie_dump_int_regs()
12657 DHD_ERROR(("d2h_mb_data=0x%x def_intmask=0x%x \r\n", d2h_mb_data, in dhd_pcie_dump_int_regs()
12666 DHD_ERROR(("\n ------- DUMPING PCIE RC config space Registers ------- \r\n")); in dhd_pcie_dump_rc_conf_space_cap()
12667 DHD_ERROR(("Pcie RC Uncorrectable Error Status Val=0x%x\n", in dhd_pcie_dump_rc_conf_space_cap()
12671 DHD_ERROR(("hdrlog0 =0x%08x hdrlog1 =0x%08x hdrlog2 =0x%08x hdrlog3 =0x%08x\n", in dhd_pcie_dump_rc_conf_space_cap()
12688 DHD_ERROR(("bus->bus_low_power_state = %d\n", dhd->bus->bus_low_power_state)); in dhd_pcie_debug_info_dump()
12690 DHD_ERROR(("host pcie_irq disabled = %d\n", host_irq_disabled)); in dhd_pcie_debug_info_dump()
12694 DHD_ERROR(("\n ------- DUMPING PCIE EP Resouce Info ------- \r\n")); in dhd_pcie_debug_info_dump()
12699 DHD_ERROR(("RootPort PCIe linkcap=0x%08x\n", in dhd_pcie_debug_info_dump()
12703 DHD_ERROR(("Skip dumping the PCIe Config and Core registers. " in dhd_pcie_debug_info_dump()
12708 DHD_ERROR(("\n ------- DUMPING PCIE EP config space Registers ------- \r\n")); in dhd_pcie_debug_info_dump()
12709 DHD_ERROR(("Status Command(0x%x)=0x%x, BaseAddress0(0x%x)=0x%x BaseAddress1(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12719 DHD_ERROR(("LinkCtl(0x%x)=0x%x DeviceStatusControl2(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12728 DHD_ERROR(("Pcie EP Uncorrectable Error Status Val=0x%x\n", in dhd_pcie_debug_info_dump()
12731 DHD_ERROR(("hdrlog0(0x%x)=0x%08x hdrlog1(0x%x)=0x%08x hdrlog2(0x%x)=0x%08x " in dhd_pcie_debug_info_dump()
12741 DHD_ERROR(("DeviceStatusControl(0x%x)=0x%x SubsystemControl(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12754 DHD_ERROR(("Skip dumping the PCIe Core registers. link may be DOWN\n")); in dhd_pcie_debug_info_dump()
12758 DHD_ERROR(("\n ------- DUMPING PCIE core Registers ------- \r\n")); in dhd_pcie_debug_info_dump()
12760 DHD_ERROR(("ClkReq0(0x%x)=0x%x ClkReq1(0x%x)=0x%x ClkReq2(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12773 DHD_ERROR(("ltssm_hist_0(0x%x)=0x%x ltssm_hist_1(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12784 DHD_ERROR(("trefup(0x%x)=0x%x trefup_ext(0x%x)=0x%x\n", in dhd_pcie_debug_info_dump()
12789 DHD_ERROR(("errlog(0x%x)=0x%x errlog_addr(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12811 DHD_ERROR(("err_hdrlog1(0x%x)=0x%x err_hdrlog2(0x%x)=0x%x " in dhd_pcie_debug_info_dump()
12825 DHD_ERROR(("err_code(0x%x)=0x%x\n", in dhd_pcie_debug_info_dump()
12881 DHD_ERROR(("%s: bus is NULL !\n", __FUNCTION__)); in dhd_bus_tcm_test()
12888 DHD_ERROR(("%s: MALLOC of read_buf failed\n", __FUNCTION__)); in dhd_bus_tcm_test()
12896 DHD_ERROR(("%s: MALLOC of write_buf failed\n", __FUNCTION__)); in dhd_bus_tcm_test()
12900 DHD_ERROR(("%s: start %x, size: %x\n", __FUNCTION__, bus->dongle_ram_base, bus->ramsize)); in dhd_bus_tcm_test()
12901 DHD_ERROR(("%s: memblock size %d, #pattern %d\n", __FUNCTION__, MEMBLOCK, NUM_PATTERNS)); in dhd_bus_tcm_test()
12915 DHD_ERROR(("%s: Write Error membytes %d\n", __FUNCTION__, ret)); in dhd_bus_tcm_test()
12923 DHD_ERROR(("%s: Read Error membytes %d\n", __FUNCTION__, ret)); in dhd_bus_tcm_test()
12931 DHD_ERROR(("%s: Mismatch at %x, iter : %d\n", in dhd_bus_tcm_test()
12950 DHD_ERROR(("%s: Success iter : %d\n", __FUNCTION__, num)); in dhd_bus_tcm_test()