Lines Matching full:bus
2 * DHD Bus Module for PCIE
120 #define DHD_PCIE_SHARED_MEMBER_ADDR(bus, member) \ argument
121 (bus)->shared_addr + OFFSETOF(pciedev_shared_t, member)
124 #define DHD_RING_INFO_MEMBER_ADDR(bus, member) \ argument
125 (bus)->pcie_sh->rings_info_ptr + OFFSETOF(ring_info_t, member)
128 #define DHD_RING_MEM_MEMBER_ADDR(bus, ringid, member) \ argument
129 (bus)->ring_sh[ringid].ring_mem_addr + OFFSETOF(ring_mem_t, member)
161 static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size);
162 static int dhdpcie_bus_readconsole(dhd_bus_t *bus);
164 static int dhdpcie_mem_dump(dhd_bus_t *bus);
165 static int dhdpcie_get_mem_dump(dhd_bus_t *bus);
168 static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size);
169 static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
172 static int dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 intval);
173 static int dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus,
176 static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter);
190 static int dhdpcie_dongle_host_post_varswrite(dhd_bus_t *bus, hs_addrs_t *addr);
191 static int _dhdpcie_download_firmware(struct dhd_bus *bus);
192 static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh);
193 static int dhdpcie_bus_write_vars(dhd_bus_t *bus);
194 static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus);
195 static bool dhdpci_bus_read_frames(dhd_bus_t *bus);
196 static int dhdpcie_readshared_console(dhd_bus_t *bus);
197 static int dhdpcie_readshared(dhd_bus_t *bus);
198 static void dhdpcie_init_shared_addr(dhd_bus_t *bus);
199 static bool dhdpcie_dongle_attach(dhd_bus_t *bus);
200 static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size);
201 static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh,
203 static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh);
204 static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len);
205 static void dhdpcie_setbar1win(dhd_bus_t *bus, uint32 addr);
206 static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset);
207 static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
208 static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
209 static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset);
210 static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
211 static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset);
213 static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data) __attribute__ ((used));
214 static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset) __attribute__ ((used));
216 static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data);
218 static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b);
219 static int dhdpcie_sromotp_customvar(dhd_bus_t *bus, uint32 *customvar1, uint32 *customvar2);
220 static void dhdpcie_fw_trap(dhd_bus_t *bus);
221 static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info);
222 static void dhdpcie_handle_mb_data(dhd_bus_t *bus);
227 static void dhd_bus_check_idle_scan(dhd_bus_t *bus);
228 static void dhd_bus_idle_scan(dhd_bus_t *bus);
236 static void dhdpci_bus_rte_log_time_sync_poll(dhd_bus_t *bus);
248 static int dhdpcie_cto_error_recovery(struct dhd_bus *bus);
250 static int dhdpcie_init_d11status(struct dhd_bus *bus);
252 static int dhdpcie_wrt_rnd(struct dhd_bus *bus);
259 static uint16 dhd_bus_set_hp2p_ring_max_size(struct dhd_bus *bus, bool tx, uint16 val);
262 static bool dhd_bus_tcm_test(struct dhd_bus *bus);
450 /** the GDB debugger layer will call back into this (bus) layer to read/write dongle memory */
459 dhd_bus_get_flr_force_fail(struct dhd_bus *bus) in dhd_bus_get_flr_force_fail() argument
461 return bus->flr_force_fail; in dhd_bus_get_flr_force_fail()
466 * link with the bus driver, in order to look for or await the device.
504 dhd_bus_db0_addr_get(struct dhd_bus *bus) in dhd_bus_db0_addr_get() argument
507 uint dar_addr = DAR_PCIH2D_DB0_0(bus->sih->buscorerev); in dhd_bus_db0_addr_get()
509 return ((DAR_ACTIVE(bus->dhd)) ? dar_addr : addr); in dhd_bus_db0_addr_get()
513 dhd_bus_db0_addr_2_get(struct dhd_bus *bus) in dhd_bus_db0_addr_2_get() argument
515 return ((DAR_ACTIVE(bus->dhd)) ? DAR_PCIH2D_DB2_0(bus->sih->buscorerev) : PCIH2D_MailBox_2); in dhd_bus_db0_addr_2_get()
519 dhd_bus_db1_addr_get(struct dhd_bus *bus) in dhd_bus_db1_addr_get() argument
521 return ((DAR_ACTIVE(bus->dhd)) ? DAR_PCIH2D_DB0_1(bus->sih->buscorerev) : PCIH2D_DB1); in dhd_bus_db1_addr_get()
525 dhd_bus_db1_addr_1_get(struct dhd_bus *bus) in dhd_bus_db1_addr_1_get() argument
527 return ((DAR_ACTIVE(bus->dhd)) ? DAR_PCIH2D_DB1_1(bus->sih->buscorerev) : PCIH2D_DB1_1); in dhd_bus_db1_addr_1_get()
534 dhd_bus_pcie_pwr_req_wl_domain(struct dhd_bus *bus, bool enable) in dhd_bus_pcie_pwr_req_wl_domain() argument
537 si_corereg(bus->sih, bus->sih->buscoreidx, in dhd_bus_pcie_pwr_req_wl_domain()
538 DAR_PCIE_PWR_CTRL((bus->sih)->buscorerev), in dhd_bus_pcie_pwr_req_wl_domain()
542 si_corereg(bus->sih, bus->sih->buscoreidx, in dhd_bus_pcie_pwr_req_wl_domain()
543 DAR_PCIE_PWR_CTRL((bus->sih)->buscorerev), in dhd_bus_pcie_pwr_req_wl_domain()
549 _dhd_bus_pcie_pwr_req_clear_cmn(struct dhd_bus *bus) in _dhd_bus_pcie_pwr_req_clear_cmn() argument
558 if (bus->pwr_req_ref > 1) { in _dhd_bus_pcie_pwr_req_clear_cmn()
559 bus->pwr_req_ref--; in _dhd_bus_pcie_pwr_req_clear_cmn()
563 ASSERT(bus->pwr_req_ref == 1); in _dhd_bus_pcie_pwr_req_clear_cmn()
565 if (MULTIBP_ENAB(bus->sih)) { in _dhd_bus_pcie_pwr_req_clear_cmn()
572 si_srpwr_request(bus->sih, mask, 0); in _dhd_bus_pcie_pwr_req_clear_cmn()
573 bus->pwr_req_ref = 0; in _dhd_bus_pcie_pwr_req_clear_cmn()
577 dhd_bus_pcie_pwr_req_clear(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req_clear() argument
581 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_clear()
582 _dhd_bus_pcie_pwr_req_clear_cmn(bus); in dhd_bus_pcie_pwr_req_clear()
583 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_clear()
587 dhd_bus_pcie_pwr_req_clear_nolock(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req_clear_nolock() argument
589 _dhd_bus_pcie_pwr_req_clear_cmn(bus); in dhd_bus_pcie_pwr_req_clear_nolock()
593 _dhd_bus_pcie_pwr_req_cmn(struct dhd_bus *bus) in _dhd_bus_pcie_pwr_req_cmn() argument
598 if (bus->pwr_req_ref > 0) { in _dhd_bus_pcie_pwr_req_cmn()
599 bus->pwr_req_ref++; in _dhd_bus_pcie_pwr_req_cmn()
603 ASSERT(bus->pwr_req_ref == 0); in _dhd_bus_pcie_pwr_req_cmn()
605 if (MULTIBP_ENAB(bus->sih)) { in _dhd_bus_pcie_pwr_req_cmn()
614 si_srpwr_request(bus->sih, mask, val); in _dhd_bus_pcie_pwr_req_cmn()
616 bus->pwr_req_ref = 1; in _dhd_bus_pcie_pwr_req_cmn()
620 dhd_bus_pcie_pwr_req(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req() argument
624 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req()
625 _dhd_bus_pcie_pwr_req_cmn(bus); in dhd_bus_pcie_pwr_req()
626 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req()
630 _dhd_bus_pcie_pwr_req_pd0123_cmn(struct dhd_bus *bus) in _dhd_bus_pcie_pwr_req_pd0123_cmn() argument
634 mask = SRPWR_DMN_ALL_MASK(bus->sih); in _dhd_bus_pcie_pwr_req_pd0123_cmn()
635 val = SRPWR_DMN_ALL_MASK(bus->sih); in _dhd_bus_pcie_pwr_req_pd0123_cmn()
637 si_srpwr_request(bus->sih, mask, val); in _dhd_bus_pcie_pwr_req_pd0123_cmn()
641 dhd_bus_pcie_pwr_req_reload_war(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req_reload_war() argument
645 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_reload_war()
646 _dhd_bus_pcie_pwr_req_pd0123_cmn(bus); in dhd_bus_pcie_pwr_req_reload_war()
647 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_reload_war()
651 _dhd_bus_pcie_pwr_req_clear_pd0123_cmn(struct dhd_bus *bus) in _dhd_bus_pcie_pwr_req_clear_pd0123_cmn() argument
655 mask = SRPWR_DMN_ALL_MASK(bus->sih); in _dhd_bus_pcie_pwr_req_clear_pd0123_cmn()
657 si_srpwr_request(bus->sih, mask, 0); in _dhd_bus_pcie_pwr_req_clear_pd0123_cmn()
661 dhd_bus_pcie_pwr_req_clear_reload_war(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req_clear_reload_war() argument
665 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_clear_reload_war()
666 _dhd_bus_pcie_pwr_req_clear_pd0123_cmn(bus); in dhd_bus_pcie_pwr_req_clear_reload_war()
667 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_pcie_pwr_req_clear_reload_war()
671 dhd_bus_pcie_pwr_req_nolock(struct dhd_bus *bus) in dhd_bus_pcie_pwr_req_nolock() argument
673 _dhd_bus_pcie_pwr_req_cmn(bus); in dhd_bus_pcie_pwr_req_nolock()
677 dhdpcie_chip_support_msi(dhd_bus_t *bus) in dhdpcie_chip_support_msi() argument
680 __FUNCTION__, bus->sih->buscorerev, si_chipid(bus->sih))); in dhdpcie_chip_support_msi()
681 if (bus->sih->buscorerev <= 14 || in dhdpcie_chip_support_msi()
682 si_chipid(bus->sih) == BCM4375_CHIP_ID || in dhdpcie_chip_support_msi()
683 si_chipid(bus->sih) == BCM4362_CHIP_ID || in dhdpcie_chip_support_msi()
684 si_chipid(bus->sih) == BCM43751_CHIP_ID || in dhdpcie_chip_support_msi()
685 si_chipid(bus->sih) == BCM4361_CHIP_ID || in dhdpcie_chip_support_msi()
686 si_chipid(bus->sih) == CYW55560_CHIP_ID) { in dhdpcie_chip_support_msi()
705 dhd_bus_t *bus = NULL; in dhdpcie_bus_attach() local
718 if (!(bus = MALLOCZ(osh, sizeof(dhd_bus_t)))) { in dhdpcie_bus_attach()
724 bus->regs = regs; in dhdpcie_bus_attach()
725 bus->tcm = tcm; in dhdpcie_bus_attach()
726 bus->osh = osh; in dhdpcie_bus_attach()
728 bus->dev = (struct pci_dev *)pci_dev; in dhdpcie_bus_attach()
730 dll_init(&bus->flowring_active_list); in dhdpcie_bus_attach()
732 bus->active_list_last_process_ts = OSL_SYSUPTIME(); in dhdpcie_bus_attach()
736 if (!(bus->pcie_sh = MALLOCZ(osh, sizeof(pciedev_shared_t)))) { in dhdpcie_bus_attach()
737 DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__)); in dhdpcie_bus_attach()
744 if (dhdpcie_dongle_attach(bus)) { in dhdpcie_bus_attach()
756 if (dhdpcie_sromotp_customvar(bus, &customvar1, &customvar2)) { in dhdpcie_bus_attach()
784 if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) { in dhdpcie_bus_attach()
790 bus->dhd->busstate = DHD_BUS_DOWN; in dhdpcie_bus_attach()
791 bus->dhd->hostrdy_after_init = TRUE; in dhdpcie_bus_attach()
792 bus->db1_for_mb = TRUE; in dhdpcie_bus_attach()
793 bus->dhd->hang_report = TRUE; in dhdpcie_bus_attach()
794 bus->use_mailbox = FALSE; in dhdpcie_bus_attach()
795 bus->use_d0_inform = FALSE; in dhdpcie_bus_attach()
796 bus->intr_enabled = FALSE; in dhdpcie_bus_attach()
797 bus->flr_force_fail = FALSE; in dhdpcie_bus_attach()
799 bus->hwa_enab_bmap = 0; in dhdpcie_bus_attach()
802 dhdpcie_set_dma_ring_indices(bus->dhd, dma_ring_indices); in dhdpcie_bus_attach()
805 bus->dhd->h2d_phase_supported = h2d_phase ? TRUE : FALSE; in dhdpcie_bus_attach()
807 bus->dhd->force_dongletrap_on_bad_h2d_phase = in dhdpcie_bus_attach()
810 bus->enable_idle_flowring_mgmt = FALSE; in dhdpcie_bus_attach()
812 bus->irq_registered = FALSE; in dhdpcie_bus_attach()
816 bus->d2h_intr_method = PCIE_MSI; in dhdpcie_bus_attach()
818 bus->d2h_intr_method = enable_msi && dhdpcie_chip_support_msi(bus) ? in dhdpcie_bus_attach()
822 bus->d2h_intr_method = PCIE_INTX; in dhdpcie_bus_attach()
826 bus->hp2p_txcpl_max_items = DHD_MAX_ITEMS_HPP_TXCPL_RING; in dhdpcie_bus_attach()
827 bus->hp2p_rxcpl_max_items = DHD_MAX_ITEMS_HPP_RXCPL_RING; in dhdpcie_bus_attach()
832 g_dhd_bus = bus; in dhdpcie_bus_attach()
833 *bus_ptr = bus; in dhdpcie_bus_attach()
839 if (bus && bus->pcie_sh) { in dhdpcie_bus_attach()
840 MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t)); in dhdpcie_bus_attach()
843 if (bus) { in dhdpcie_bus_attach()
844 MFREE(osh, bus, sizeof(dhd_bus_t)); in dhdpcie_bus_attach()
862 dhd_bus_chip(struct dhd_bus *bus) in dhd_bus_chip() argument
864 ASSERT(bus->sih != NULL); in dhd_bus_chip()
865 return bus->sih->chip; in dhd_bus_chip()
869 dhd_bus_chiprev(struct dhd_bus *bus) in dhd_bus_chiprev() argument
871 ASSERT(bus); in dhd_bus_chiprev()
872 ASSERT(bus->sih != NULL); in dhd_bus_chiprev()
873 return bus->sih->chiprev; in dhd_bus_chiprev()
877 dhd_bus_pub(struct dhd_bus *bus) in dhd_bus_pub() argument
879 return bus->dhd; in dhd_bus_pub()
883 dhd_bus_sih(struct dhd_bus *bus) in dhd_bus_sih() argument
885 return (void *)bus->sih; in dhd_bus_sih()
889 dhd_bus_txq(struct dhd_bus *bus) in dhd_bus_txq() argument
891 return &bus->txq; in dhd_bus_txq()
897 dhd_bus_t *bus = dhdp->bus; in dhd_bus_chip_id() local
898 return bus->sih->chip; in dhd_bus_chip_id()
904 dhd_bus_t *bus = dhdp->bus; in dhd_bus_chiprev_id() local
905 return bus->sih->chiprev; in dhd_bus_chiprev_id()
919 dhd_bus_t *bus = dhdp->bus; in dhd_bus_chippkg_id() local
920 return bus->sih->chippkg; in dhd_bus_chippkg_id()
964 dhdp->bus->dpc_sched_time = OSL_LOCALTIME_NS(); in dhd_bus_set_dpc_sched_time()
971 dhd_bus_t *bus = dhdp->bus; in dhd_bus_query_dpc_sched_errors() local
974 if (bus->dpc_entry_time < bus->isr_exit_time) { in dhd_bus_query_dpc_sched_errors()
977 } else if (bus->dpc_entry_time < bus->resched_dpc_time) { in dhd_bus_query_dpc_sched_errors()
994 GET_SEC_USEC(bus->isr_entry_time), in dhd_bus_query_dpc_sched_errors()
995 GET_SEC_USEC(bus->isr_exit_time), in dhd_bus_query_dpc_sched_errors()
996 GET_SEC_USEC(bus->dpc_entry_time), in dhd_bus_query_dpc_sched_errors()
997 GET_SEC_USEC(bus->dpc_exit_time), in dhd_bus_query_dpc_sched_errors()
998 GET_SEC_USEC(bus->dpc_sched_time), in dhd_bus_query_dpc_sched_errors()
999 GET_SEC_USEC(bus->resched_dpc_time))); in dhd_bus_query_dpc_sched_errors()
1007 dhdpcie_bus_intstatus(dhd_bus_t *bus) in dhdpcie_bus_intstatus() argument
1012 if (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED) { in dhdpcie_bus_intstatus()
1016 if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) || in dhdpcie_bus_intstatus()
1017 (bus->sih->buscorerev == 2)) { in dhdpcie_bus_intstatus()
1018 intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); in dhdpcie_bus_intstatus()
1019 dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus); in dhdpcie_bus_intstatus()
1023 intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_int, 0, 0); in dhdpcie_bus_intstatus()
1026 intmask = si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_mask, 0, 0); in dhdpcie_bus_intstatus()
1032 bus->is_linkdown = TRUE; in dhdpcie_bus_intstatus()
1033 dhd_pcie_debug_info_dump(bus->dhd); in dhdpcie_bus_intstatus()
1038 bus->no_cfg_restore = 1; in dhdpcie_bus_intstatus()
1041 bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN_EP_DETECT; in dhdpcie_bus_intstatus()
1042 dhd_os_send_hang_message(bus->dhd); in dhdpcie_bus_intstatus()
1056 si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_int, bus->def_intmask, in dhdpcie_bus_intstatus()
1059 intstatus &= bus->def_intmask; in dhdpcie_bus_intstatus()
1068 dhd_bus_t *bus = dhd->bus; in dhdpcie_cto_recovery_handler() local
1083 ret = dhdpcie_cto_error_recovery(bus); in dhdpcie_cto_recovery_handler()
1088 dhd_prot_debug_info_print(bus->dhd); in dhdpcie_cto_recovery_handler()
1090 dhd_bus_dump_console_buffer(bus); in dhdpcie_cto_recovery_handler()
1093 if (!bus->is_linkdown && bus->dhd->memdump_enabled) { in dhdpcie_cto_recovery_handler()
1095 bus->dhd->collect_sssr = TRUE; in dhdpcie_cto_recovery_handler()
1097 bus->dhd->memdump_type = DUMP_TYPE_CTO_RECOVERY; in dhdpcie_cto_recovery_handler()
1098 dhdpcie_mem_dump(bus); in dhdpcie_cto_recovery_handler()
1105 bus->no_cfg_restore = 1; in dhdpcie_cto_recovery_handler()
1108 bus->is_linkdown = TRUE; in dhdpcie_cto_recovery_handler()
1109 bus->dhd->hang_reason = HANG_REASON_PCIE_CTO_DETECT; in dhdpcie_cto_recovery_handler()
1111 dhd_os_send_hang_message(bus->dhd); in dhdpcie_cto_recovery_handler()
1128 dhdpcie_bus_isr(dhd_bus_t *bus) in dhdpcie_bus_isr() argument
1135 if (!bus) { in dhdpcie_bus_isr()
1136 DHD_LOG_MEM(("%s : bus is null pointer, exit \n", __FUNCTION__)); in dhdpcie_bus_isr()
1140 if (bus->dhd->dongle_reset) { in dhdpcie_bus_isr()
1145 if (bus->dhd->busstate == DHD_BUS_DOWN) { in dhdpcie_bus_isr()
1146 DHD_LOG_MEM(("%s : bus is down \n", __FUNCTION__)); in dhdpcie_bus_isr()
1151 if (!bus->intr_enabled) { in dhdpcie_bus_isr()
1156 if (PCIECTO_ENAB(bus)) { in dhdpcie_bus_isr()
1158 intstatus = dhdpcie_bus_cfg_read_dword(bus, PCI_INT_STATUS, 4); in dhdpcie_bus_isr()
1163 intstatus, bus->cto_enable)); in dhdpcie_bus_isr()
1164 bus->cto_triggered = 1; in dhdpcie_bus_isr()
1168 dhd_bus_dump_dar_registers(bus); in dhdpcie_bus_isr()
1171 dhdpcie_disable_irq_nosync(bus); /* Disable interrupt!! */ in dhdpcie_bus_isr()
1173 dhd_bus_stop_queue(bus); in dhdpcie_bus_isr()
1176 dhd_schedule_cto_recovery(bus->dhd); in dhdpcie_bus_isr()
1182 if (bus->d2h_intr_method == PCIE_MSI) { in dhdpcie_bus_isr()
1187 intstatus = dhdpcie_bus_intstatus(bus); in dhdpcie_bus_isr()
1195 bus->non_ours_irq_count++; in dhdpcie_bus_isr()
1196 bus->last_non_ours_irq_time = OSL_LOCALTIME_NS(); in dhdpcie_bus_isr()
1202 bus->intstatus = intstatus; in dhdpcie_bus_isr()
1208 dhdpcie_disable_irq_nosync(bus); in dhdpcie_bus_isr()
1221 bus->intrcount++; in dhdpcie_bus_isr()
1223 bus->ipend = TRUE; in dhdpcie_bus_isr()
1225 bus->isr_intr_disable_count++; in dhdpcie_bus_isr()
1232 dhdpcie_bus_intr_disable(bus); in dhdpcie_bus_isr()
1233 dhdpcie_disable_irq_nosync(bus); /* Disable interrupt!! */ in dhdpcie_bus_isr()
1235 bus->intdis = TRUE; in dhdpcie_bus_isr()
1240 DHD_OS_WAKE_LOCK(bus->dhd); in dhdpcie_bus_isr()
1241 while (dhd_bus_dpc(bus)); in dhdpcie_bus_isr()
1242 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhdpcie_bus_isr()
1244 bus->dpc_sched = TRUE; in dhdpcie_bus_isr()
1245 dhd_sched_dpc(bus->dhd); /* queue DPC now!! */ in dhdpcie_bus_isr()
1258 dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state) in dhdpcie_set_pwr_state() argument
1262 osl_t *osh = bus->osh; in dhdpcie_set_pwr_state()
1314 dhdpcie_config_check(dhd_bus_t *bus) in dhdpcie_config_check() argument
1320 val = OSL_PCI_READ_CONFIG(bus->osh, PCI_CFG_VID, sizeof(uint32)); in dhdpcie_config_check()
1332 dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr) in dhdpcie_config_restore() argument
1335 osl_t *osh = bus->osh; in dhdpcie_config_restore()
1337 if (BCME_OK != dhdpcie_config_check(bus)) { in dhdpcie_config_restore()
1342 OSL_PCI_WRITE_CONFIG(osh, i << 2, sizeof(uint32), bus->saved_config.header[i]); in dhdpcie_config_restore()
1344 OSL_PCI_WRITE_CONFIG(osh, PCI_CFG_CMD, sizeof(uint32), bus->saved_config.header[1]); in dhdpcie_config_restore()
1348 sizeof(uint32), bus->saved_config.pmcsr); in dhdpcie_config_restore()
1350 OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_CAP, sizeof(uint32), bus->saved_config.msi_cap); in dhdpcie_config_restore()
1352 bus->saved_config.msi_addr0); in dhdpcie_config_restore()
1354 sizeof(uint32), bus->saved_config.msi_addr1); in dhdpcie_config_restore()
1356 sizeof(uint32), bus->saved_config.msi_data); in dhdpcie_config_restore()
1359 sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat); in dhdpcie_config_restore()
1361 sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat2); in dhdpcie_config_restore()
1363 sizeof(uint32), bus->saved_config.exp_link_ctrl_stat); in dhdpcie_config_restore()
1365 sizeof(uint32), bus->saved_config.exp_link_ctrl_stat2); in dhdpcie_config_restore()
1368 sizeof(uint32), bus->saved_config.l1pm0); in dhdpcie_config_restore()
1370 sizeof(uint32), bus->saved_config.l1pm1); in dhdpcie_config_restore()
1372 OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, sizeof(uint32), in dhdpcie_config_restore()
1373 bus->saved_config.bar0_win); in dhdpcie_config_restore()
1374 dhdpcie_setbar1win(bus, bus->saved_config.bar1_win); in dhdpcie_config_restore()
1380 dhdpcie_config_save(dhd_bus_t *bus) in dhdpcie_config_save() argument
1383 osl_t *osh = bus->osh; in dhdpcie_config_save()
1385 if (BCME_OK != dhdpcie_config_check(bus)) { in dhdpcie_config_save()
1390 bus->saved_config.header[i] = OSL_PCI_READ_CONFIG(osh, i << 2, sizeof(uint32)); in dhdpcie_config_save()
1393 bus->saved_config.pmcsr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32)); in dhdpcie_config_save()
1395 bus->saved_config.msi_cap = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_CAP, in dhdpcie_config_save()
1397 bus->saved_config.msi_addr0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_L, in dhdpcie_config_save()
1399 bus->saved_config.msi_addr1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_H, in dhdpcie_config_save()
1401 bus->saved_config.msi_data = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_DATA, in dhdpcie_config_save()
1404 bus->saved_config.exp_dev_ctrl_stat = OSL_PCI_READ_CONFIG(osh, in dhdpcie_config_save()
1406 bus->saved_config.exp_dev_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh, in dhdpcie_config_save()
1408 bus->saved_config.exp_link_ctrl_stat = OSL_PCI_READ_CONFIG(osh, in dhdpcie_config_save()
1410 bus->saved_config.exp_link_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh, in dhdpcie_config_save()
1413 bus->saved_config.l1pm0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL1, in dhdpcie_config_save()
1415 bus->saved_config.l1pm1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL2, in dhdpcie_config_save()
1418 bus->saved_config.bar0_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, in dhdpcie_config_save()
1420 bus->saved_config.bar1_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR1_WIN, in dhdpcie_config_save()
1431 dhdpcie_bus_intr_init(dhd_bus_t *bus) in dhdpcie_bus_intr_init() argument
1433 uint buscorerev = bus->sih->buscorerev; in dhdpcie_bus_intr_init()
1434 bus->pcie_mailbox_int = PCIMailBoxInt(buscorerev); in dhdpcie_bus_intr_init()
1435 bus->pcie_mailbox_mask = PCIMailBoxMask(buscorerev); in dhdpcie_bus_intr_init()
1436 bus->d2h_mb_mask = PCIE_MB_D2H_MB_MASK(buscorerev); in dhdpcie_bus_intr_init()
1437 bus->def_intmask = PCIE_MB_D2H_MB_MASK(buscorerev); in dhdpcie_bus_intr_init()
1439 bus->def_intmask |= PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1; in dhdpcie_bus_intr_init()
1444 dhdpcie_cc_watchdog_reset(dhd_bus_t *bus) in dhdpcie_cc_watchdog_reset() argument
1446 uint32 wd_en = (bus->sih->buscorerev >= 66) ? WD_SSRESET_PCIE_F0_EN : in dhdpcie_cc_watchdog_reset()
1448 pcie_watchdog_reset(bus->osh, bus->sih, WD_ENABLE_MASK, wd_en); in dhdpcie_cc_watchdog_reset()
1452 dhdpcie_dongle_reset(dhd_bus_t *bus) in dhdpcie_dongle_reset() argument
1457 if (bus->is_linkdown) { in dhdpcie_dongle_reset()
1462 if (dhd_bus_perform_flr(bus, FALSE) == BCME_UNSUPPORTED) { in dhdpcie_dongle_reset()
1465 dhd_bus_perform_bp_reset(bus); in dhdpcie_dongle_reset()
1468 dhdpcie_cc_watchdog_reset(bus); in dhdpcie_dongle_reset()
1475 dhdpcie_bus_mpu_disable(dhd_bus_t *bus) in dhdpcie_bus_mpu_disable() argument
1478 if (BCM4378_CHIP(bus->sih->chip)) { in dhdpcie_bus_mpu_disable()
1479 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_mpu_disable()
1484 if (R_REG(bus->osh, cr4_regs + ARMCR4REG_CORECAP) & ACC_MPU_MASK) { in dhdpcie_bus_mpu_disable()
1485 /* bus mpu is supported */ in dhdpcie_bus_mpu_disable()
1486 W_REG(bus->osh, cr4_regs + ARMCR4REG_MPUCTRL, 0); in dhdpcie_bus_mpu_disable()
1493 dhdpcie_dongle_attach(dhd_bus_t *bus) in dhdpcie_dongle_attach() argument
1495 osl_t *osh = bus->osh; in dhdpcie_dongle_attach()
1496 volatile void *regsva = (volatile void*)bus->regs; in dhdpcie_dongle_attach()
1508 link_recovery = bus->dhd; in dhdpcie_dongle_attach()
1511 bus->alp_only = TRUE; in dhdpcie_dongle_attach()
1512 bus->sih = NULL; in dhdpcie_dongle_attach()
1514 /* Checking PCIe bus status with reading configuration space */ in dhdpcie_dongle_attach()
1521 bus->cl_devid = devid; in dhdpcie_dongle_attach()
1524 dhdpcie_bus_cfg_set_bar0_win(bus, si_enum_base(devid)); in dhdpcie_dongle_attach()
1544 dhdpcie_bus_cfg_set_bar0_win(bus, si_pcie_enum_base(devid)); in dhdpcie_dongle_attach()
1545 sbpcieregs = (sbpcieregs_t*)(bus->regs); in dhdpcie_dongle_attach()
1551 if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus, in dhdpcie_dongle_attach()
1552 &bus->vars, &bus->varsz))) { in dhdpcie_dongle_attach()
1556 dhdpcie_dongle_reset(bus); in dhdpcie_dongle_attach()
1571 dhdpcie_bus_cfg_set_bar0_win(bus, si_enum_base(devid)); in dhdpcie_dongle_attach()
1575 if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus, in dhdpcie_dongle_attach()
1576 &bus->vars, &bus->varsz))) { in dhdpcie_dongle_attach()
1584 bus->cto_enable = FALSE; in dhdpcie_dongle_attach()
1587 if (bus->sih->buscorerev >= 24) { in dhdpcie_dongle_attach()
1589 bus->cto_enable = TRUE; in dhdpcie_dongle_attach()
1594 bus->cto_enable = FALSE; in dhdpcie_dongle_attach()
1598 if (PCIECTO_ENAB(bus)) { in dhdpcie_dongle_attach()
1599 dhdpcie_cto_init(bus, TRUE); in dhdpcie_dongle_attach()
1603 bus->sih->secureboot = isset(&secureboot, PCIECFGREG_SECURE_MODE_SHIFT); in dhdpcie_dongle_attach()
1605 if (MULTIBP_ENAB(bus->sih) && (bus->sih->buscorerev >= 66)) { in dhdpcie_dongle_attach()
1611 if (PCIE_ENUM_RESET_WAR_ENAB(bus->sih->buscorerev)) { in dhdpcie_dongle_attach()
1612 dhdpcie_ssreset_dis_enum_rst(bus); in dhdpcie_dongle_attach()
1619 bus->pwr_req_ref = 0; in dhdpcie_dongle_attach()
1622 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_dongle_attach()
1623 dhd_bus_pcie_pwr_req_nolock(bus); in dhdpcie_dongle_attach()
1628 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) || in dhdpcie_dongle_attach()
1629 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) || in dhdpcie_dongle_attach()
1630 (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) || in dhdpcie_dongle_attach()
1631 (si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { in dhdpcie_dongle_attach()
1632 bus->armrev = si_corerev(bus->sih); in dhdpcie_dongle_attach()
1633 bus->coreid = si_coreid(bus->sih); in dhdpcie_dongle_attach()
1640 if (bus->coreid == ARMCA7_CORE_ID) { in dhdpcie_dongle_attach()
1641 val = dhdpcie_bus_cfg_read_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL, 4); in dhdpcie_dongle_attach()
1642 dhdpcie_bus_cfg_write_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL, 4, in dhdpcie_dongle_attach()
1650 if (!dhdpcie_is_arm_halted(bus)) { in dhdpcie_dongle_attach()
1664 dhdpcie_clkreq(bus->osh, 1, 1); in dhdpcie_dongle_attach()
1668 * bus->dhd will be NULL if it is called from dhd_bus_attach, so need to reset in dhdpcie_dongle_attach()
1673 if (bus->dhd == NULL) { in dhdpcie_dongle_attach()
1677 dongle_isolation = bus->dhd->dongle_isolation; in dhdpcie_dongle_attach()
1687 dhdpcie_dongle_reset(bus); in dhdpcie_dongle_attach()
1694 bus->force_bt_quiesce = TRUE; in dhdpcie_dongle_attach()
1699 if (bus->sih->buscorerev >= 66) { in dhdpcie_dongle_attach()
1700 bus->force_bt_quiesce = FALSE; in dhdpcie_dongle_attach()
1703 dhdpcie_dongle_flr_or_pwr_toggle(bus); in dhdpcie_dongle_attach()
1706 dhdpcie_bus_mpu_disable(bus); in dhdpcie_dongle_attach()
1709 si_setcore(bus->sih, PCIE2_CORE_ID, 0); in dhdpcie_dongle_attach()
1710 sbpcieregs = (sbpcieregs_t*)(bus->regs); in dhdpcie_dongle_attach()
1717 if (si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) { in dhdpcie_dongle_attach()
1721 if (!bus->ramsize_adjusted) { in dhdpcie_dongle_attach()
1722 if (!(bus->orig_ramsize = si_sysmem_size(bus->sih))) { in dhdpcie_dongle_attach()
1726 switch ((uint16)bus->sih->chip) { in dhdpcie_dongle_attach()
1729 bus->dongle_ram_base = CA7_4368_RAM_BASE; in dhdpcie_dongle_attach()
1730 bus->orig_ramsize = 0x1c0000; in dhdpcie_dongle_attach()
1733 bus->dongle_ram_base = CA7_4367_RAM_BASE; in dhdpcie_dongle_attach()
1734 bus->orig_ramsize = 0x1e0000; in dhdpcie_dongle_attach()
1739 bus->dongle_ram_base = CA7_4365_RAM_BASE; in dhdpcie_dongle_attach()
1740 bus->orig_ramsize = 0x1c0000; /* Reserve 1.75MB for CA7 */ in dhdpcie_dongle_attach()
1744 } else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { in dhdpcie_dongle_attach()
1745 if (!(bus->orig_ramsize = si_socram_size(bus->sih))) { in dhdpcie_dongle_attach()
1751 if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) { in dhdpcie_dongle_attach()
1756 switch ((uint16)bus->sih->chip) { in dhdpcie_dongle_attach()
1759 bus->dongle_ram_base = CR4_4335_RAM_BASE; in dhdpcie_dongle_attach()
1767 bus->dongle_ram_base = CR4_4350_RAM_BASE; in dhdpcie_dongle_attach()
1770 bus->dongle_ram_base = CR4_4360_RAM_BASE; in dhdpcie_dongle_attach()
1774 bus->dongle_ram_base = CR4_4364_RAM_BASE; in dhdpcie_dongle_attach()
1778 bus->dongle_ram_base = (bus->sih->chiprev < 6) /* changed at 4345C0 */ in dhdpcie_dongle_attach()
1782 bus->dongle_ram_base = CR4_43602_RAM_BASE; in dhdpcie_dongle_attach()
1786 bus->dongle_ram_base = ((bus->sih->chiprev < 9) ? in dhdpcie_dongle_attach()
1792 bus->dongle_ram_base = CR4_4347_RAM_BASE; in dhdpcie_dongle_attach()
1795 bus->dongle_ram_base = CR4_4362_RAM_BASE; in dhdpcie_dongle_attach()
1798 bus->dongle_ram_base = CR4_43751_RAM_BASE; in dhdpcie_dongle_attach()
1802 bus->dongle_ram_base = CR4_4373_RAM_BASE; in dhdpcie_dongle_attach()
1806 bus->dongle_ram_base = CR4_4378_RAM_BASE; in dhdpcie_dongle_attach()
1809 bus->dongle_ram_base = CR4_4377_RAM_BASE; in dhdpcie_dongle_attach()
1814 bus->dongle_ram_base = CR4_4369_RAM_BASE; in dhdpcie_dongle_attach()
1817 bus->dongle_ram_base = CR4_55560_RAM_BASE; in dhdpcie_dongle_attach()
1820 bus->dongle_ram_base = 0; in dhdpcie_dongle_attach()
1822 __FUNCTION__, bus->dongle_ram_base)); in dhdpcie_dongle_attach()
1828 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_dongle_attach()
1829 bus->orig_ramsize -= (CR4_55560_TCAM_SZ + CR4_55560_TRX_HDR_SZ); in dhdpcie_dongle_attach()
1832 bus->ramsize = bus->orig_ramsize; in dhdpcie_dongle_attach()
1834 dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize); in dhdpcie_dongle_attach()
1836 if (bus->ramsize > DONGLE_TCM_MAP_SIZE) { in dhdpcie_dongle_attach()
1838 __FUNCTION__, bus->ramsize, bus->ramsize)); in dhdpcie_dongle_attach()
1843 bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base)); in dhdpcie_dongle_attach()
1845 bus->srmemsize = si_socram_srmem_size(bus->sih); in dhdpcie_dongle_attach()
1847 dhdpcie_bus_intr_init(bus); in dhdpcie_dongle_attach()
1850 bus->intr = (bool)dhd_intr; in dhdpcie_dongle_attach()
1852 bus->idma_enabled = TRUE; in dhdpcie_dongle_attach()
1853 bus->ifrm_enabled = TRUE; in dhdpcie_dongle_attach()
1856 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_dongle_attach()
1857 dhd_bus_pcie_pwr_req_clear_nolock(bus); in dhdpcie_dongle_attach()
1865 si_srpwr_request(bus->sih, SRPWR_DMN0_PCIE_MASK, 0); in dhdpcie_dongle_attach()
1871 if (bus->sih->buscorerev >= 68) { in dhdpcie_dongle_attach()
1872 dhd_bus_pcie_pwr_req_wl_domain(bus, TRUE); in dhdpcie_dongle_attach()
1879 if (bus->sih != NULL) { in dhdpcie_dongle_attach()
1880 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_dongle_attach()
1881 dhd_bus_pcie_pwr_req_clear_nolock(bus); in dhdpcie_dongle_attach()
1886 si_detach(bus->sih); in dhdpcie_dongle_attach()
1887 bus->sih = NULL; in dhdpcie_dongle_attach()
1894 dhpcie_bus_unmask_interrupt(dhd_bus_t *bus) in dhpcie_bus_unmask_interrupt() argument
1896 dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB); in dhpcie_bus_unmask_interrupt()
1900 dhpcie_bus_mask_interrupt(dhd_bus_t *bus) in dhpcie_bus_mask_interrupt() argument
1902 dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0); in dhpcie_bus_mask_interrupt()
1908 dhdpcie_bus_intr_enable(dhd_bus_t *bus) in dhdpcie_bus_intr_enable() argument
1911 if (bus) { in dhdpcie_bus_intr_enable()
1912 if (bus->sih && !bus->is_linkdown) { in dhdpcie_bus_intr_enable()
1914 if (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED) { in dhdpcie_bus_intr_enable()
1917 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhdpcie_bus_intr_enable()
1918 (bus->sih->buscorerev == 4)) { in dhdpcie_bus_intr_enable()
1919 dhpcie_bus_unmask_interrupt(bus); in dhdpcie_bus_intr_enable()
1922 dhd_bus_mmio_trace(bus, bus->pcie_mailbox_mask, in dhdpcie_bus_intr_enable()
1923 bus->def_intmask, TRUE); in dhdpcie_bus_intr_enable()
1925 si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_mask, in dhdpcie_bus_intr_enable()
1926 bus->def_intmask, bus->def_intmask); in dhdpcie_bus_intr_enable()
1937 dhdpcie_bus_intr_disable(dhd_bus_t *bus) in dhdpcie_bus_intr_disable() argument
1940 if (bus && bus->sih && !bus->is_linkdown) { in dhdpcie_bus_intr_disable()
1942 if (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED) { in dhdpcie_bus_intr_disable()
1945 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhdpcie_bus_intr_disable()
1946 (bus->sih->buscorerev == 4)) { in dhdpcie_bus_intr_disable()
1947 dhpcie_bus_mask_interrupt(bus); in dhdpcie_bus_intr_disable()
1949 si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_mask, in dhdpcie_bus_intr_disable()
1950 bus->def_intmask, 0); in dhdpcie_bus_intr_disable()
1959 * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
1960 * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
1997 dhdpcie_bus_remove_prep(dhd_bus_t *bus) in dhdpcie_bus_remove_prep() argument
2002 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_remove_prep()
2004 bus->dhd->busstate = DHD_BUS_DOWN; in dhdpcie_bus_remove_prep()
2005 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_remove_prep()
2007 dhd_os_sdlock(bus->dhd); in dhdpcie_bus_remove_prep()
2009 if (bus->sih && !bus->dhd->dongle_isolation) { in dhdpcie_bus_remove_prep()
2010 if (PCIE_RELOAD_WAR_ENAB(bus->sih->buscorerev) && in dhdpcie_bus_remove_prep()
2011 bus->sih->chip != CYW55560_CHIP_ID) { in dhdpcie_bus_remove_prep()
2012 dhd_bus_pcie_pwr_req_reload_war(bus); in dhdpcie_bus_remove_prep()
2018 if ((bus->sih->buscorerev == 19) || (bus->sih->buscorerev == 23)) { in dhdpcie_bus_remove_prep()
2020 pcie_set_trefup_time_100us(bus->sih); in dhdpcie_bus_remove_prep()
2027 if ((PMUREV(bus->sih->pmurev) > 31) && in dhdpcie_bus_remove_prep()
2028 (bus->sih->buscorerev != 66) && in dhdpcie_bus_remove_prep()
2029 (bus->sih->buscorerev != 68) && in dhdpcie_bus_remove_prep()
2030 (bus->sih->buscorerev != 69) && in dhdpcie_bus_remove_prep()
2031 (bus->sih->buscorerev != 70)) { in dhdpcie_bus_remove_prep()
2032 si_pmu_fast_lpo_disable(bus->sih); in dhdpcie_bus_remove_prep()
2040 if (!bus->is_linkdown) { in dhdpcie_bus_remove_prep()
2047 dhdpcie_dongle_reset(bus); in dhdpcie_bus_remove_prep()
2051 bus->dhd->is_pcie_watchdog_reset = TRUE; in dhdpcie_bus_remove_prep()
2054 dhd_os_sdunlock(bus->dhd); in dhdpcie_bus_remove_prep()
2060 dhd_init_bus_lock(dhd_bus_t *bus) in dhd_init_bus_lock() argument
2062 if (!bus->bus_lock) { in dhd_init_bus_lock()
2063 bus->bus_lock = dhd_os_spin_lock_init(bus->dhd->osh); in dhd_init_bus_lock()
2068 dhd_deinit_bus_lock(dhd_bus_t *bus) in dhd_deinit_bus_lock() argument
2070 if (bus->bus_lock) { in dhd_deinit_bus_lock()
2071 dhd_os_spin_lock_deinit(bus->dhd->osh, bus->bus_lock); in dhd_deinit_bus_lock()
2072 bus->bus_lock = NULL; in dhd_deinit_bus_lock()
2077 dhd_init_backplane_access_lock(dhd_bus_t *bus) in dhd_init_backplane_access_lock() argument
2079 if (!bus->backplane_access_lock) { in dhd_init_backplane_access_lock()
2080 bus->backplane_access_lock = dhd_os_spin_lock_init(bus->dhd->osh); in dhd_init_backplane_access_lock()
2085 dhd_deinit_backplane_access_lock(dhd_bus_t *bus) in dhd_deinit_backplane_access_lock() argument
2087 if (bus->backplane_access_lock) { in dhd_deinit_backplane_access_lock()
2088 dhd_os_spin_lock_deinit(bus->dhd->osh, bus->backplane_access_lock); in dhd_deinit_backplane_access_lock()
2089 bus->backplane_access_lock = NULL; in dhd_deinit_backplane_access_lock()
2095 dhdpcie_bus_release(dhd_bus_t *bus) in dhdpcie_bus_release() argument
2106 if (bus) { in dhdpcie_bus_release()
2108 osh = bus->osh; in dhdpcie_bus_release()
2111 if (bus->dhd) { in dhdpcie_bus_release()
2115 dhdpcie_advertise_bus_cleanup(bus->dhd); in dhdpcie_bus_release()
2116 dongle_isolation = bus->dhd->dongle_isolation; in dhdpcie_bus_release()
2117 bus->dhd->is_pcie_watchdog_reset = FALSE; in dhdpcie_bus_release()
2118 dhdpcie_bus_remove_prep(bus); in dhdpcie_bus_release()
2120 if (bus->intr) { in dhdpcie_bus_release()
2121 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_release()
2122 dhdpcie_bus_intr_disable(bus); in dhdpcie_bus_release()
2123 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_release()
2124 dhdpcie_free_irq(bus); in dhdpcie_bus_release()
2126 dhd_deinit_bus_lock(bus); in dhdpcie_bus_release()
2127 dhd_deinit_backplane_access_lock(bus); in dhdpcie_bus_release()
2129 if (IDMA_ACTIVE(bus->dhd)) { in dhdpcie_bus_release()
2135 buscorerev = bus->sih->buscorerev; in dhdpcie_bus_release()
2136 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_bus_release()
2141 * dhdpcie_bus_release_dongle free bus->sih handle, which is needed to in dhdpcie_bus_release()
2146 dhd_detach(bus->dhd); in dhdpcie_bus_release()
2147 dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE); in dhdpcie_bus_release()
2148 dhd_free(bus->dhd); in dhdpcie_bus_release()
2149 bus->dhd = NULL; in dhdpcie_bus_release()
2152 if (bus->regs) { in dhdpcie_bus_release()
2153 dhdpcie_bus_reg_unmap(osh, bus->regs, DONGLE_REG_MAP_SIZE); in dhdpcie_bus_release()
2154 bus->regs = NULL; in dhdpcie_bus_release()
2156 if (bus->tcm) { in dhdpcie_bus_release()
2157 dhdpcie_bus_reg_unmap(osh, bus->tcm, DONGLE_TCM_MAP_SIZE); in dhdpcie_bus_release()
2158 bus->tcm = NULL; in dhdpcie_bus_release()
2161 dhdpcie_bus_release_malloc(bus, osh); in dhdpcie_bus_release()
2163 if (bus->pcie_sh) { in dhdpcie_bus_release()
2164 MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t)); in dhdpcie_bus_release()
2165 bus->pcie_sh = NULL; in dhdpcie_bus_release()
2168 if (bus->console.buf != NULL) { in dhdpcie_bus_release()
2169 MFREE(osh, bus->console.buf, bus->console.bufsize); in dhdpcie_bus_release()
2172 /* Finally free bus info */ in dhdpcie_bus_release()
2173 MFREE(osh, bus, sizeof(dhd_bus_t)); in dhdpcie_bus_release()
2182 dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag) in dhdpcie_bus_release_dongle() argument
2184 DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__, in dhdpcie_bus_release_dongle()
2185 bus->dhd, bus->dhd->dongle_reset)); in dhdpcie_bus_release_dongle()
2187 if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) { in dhdpcie_bus_release_dongle()
2192 if (bus->is_linkdown) { in dhdpcie_bus_release_dongle()
2197 if (bus->sih) { in dhdpcie_bus_release_dongle()
2200 (bus->dhd && !bus->dhd->is_pcie_watchdog_reset)) { in dhdpcie_bus_release_dongle()
2201 dhdpcie_dongle_reset(bus); in dhdpcie_bus_release_dongle()
2204 dhdpcie_dongle_flr_or_pwr_toggle(bus); in dhdpcie_bus_release_dongle()
2206 if (bus->ltrsleep_on_unload) { in dhdpcie_bus_release_dongle()
2207 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_bus_release_dongle()
2211 if (bus->sih->buscorerev == 13) in dhdpcie_bus_release_dongle()
2212 pcie_serdes_iddqdisable(bus->osh, bus->sih, in dhdpcie_bus_release_dongle()
2213 (sbpcieregs_t *) bus->regs); in dhdpcie_bus_release_dongle()
2221 dhdpcie_clkreq(bus->osh, 1, 0); in dhdpcie_bus_release_dongle()
2225 dhdpcie_bus_clock_stop(bus); in dhdpcie_bus_release_dongle()
2228 if (bus->sih != NULL) { in dhdpcie_bus_release_dongle()
2229 si_detach(bus->sih); in dhdpcie_bus_release_dongle()
2230 bus->sih = NULL; in dhdpcie_bus_release_dongle()
2232 if (bus->vars && bus->varsz) in dhdpcie_bus_release_dongle()
2233 MFREE(osh, bus->vars, bus->varsz); in dhdpcie_bus_release_dongle()
2234 bus->vars = NULL; in dhdpcie_bus_release_dongle()
2241 dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size) in dhdpcie_bus_cfg_read_dword() argument
2243 uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size); in dhdpcie_bus_cfg_read_dword()
2249 dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data) in dhdpcie_bus_cfg_write_dword() argument
2251 OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data); in dhdpcie_bus_cfg_write_dword()
2255 dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data) in dhdpcie_bus_cfg_set_bar0_win() argument
2257 OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data); in dhdpcie_bus_cfg_set_bar0_win()
2261 dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size) in dhdpcie_bus_dongle_setmemsize() argument
2268 (dhd_dongle_memsize < (int32)bus->orig_ramsize)) in dhdpcie_bus_dongle_setmemsize()
2269 bus->ramsize = dhd_dongle_memsize; in dhdpcie_bus_dongle_setmemsize()
2273 dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh) in dhdpcie_bus_release_malloc() argument
2277 if (bus->dhd && bus->dhd->dongle_reset) in dhdpcie_bus_release_malloc()
2280 if (bus->vars && bus->varsz) { in dhdpcie_bus_release_malloc()
2281 MFREE(osh, bus->vars, bus->varsz); in dhdpcie_bus_release_malloc()
2282 bus->vars = NULL; in dhdpcie_bus_release_malloc()
2290 /** Stop bus module: clear pending frames, disable data flow */
2291 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) in dhd_bus_stop() argument
2297 if (!bus->dhd) in dhd_bus_stop()
2300 if (bus->dhd->busstate == DHD_BUS_DOWN) { in dhd_bus_stop()
2305 DHD_DISABLE_RUNTIME_PM(bus->dhd); in dhd_bus_stop()
2307 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_stop()
2309 bus->dhd->busstate = DHD_BUS_DOWN; in dhd_bus_stop()
2310 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_stop()
2313 atomic_set(&bus->dhd->block_bus, TRUE); in dhd_bus_stop()
2316 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhd_bus_stop()
2317 dhdpcie_bus_intr_disable(bus); in dhd_bus_stop()
2318 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhd_bus_stop()
2320 if (!bus->is_linkdown) { in dhd_bus_stop()
2322 status = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); in dhd_bus_stop()
2323 dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status); in dhd_bus_stop()
2327 dhd_dpc_kill(bus->dhd); in dhd_bus_stop()
2331 pm_runtime_disable(dhd_bus_to_dev(bus)); in dhd_bus_stop()
2332 pm_runtime_set_suspended(dhd_bus_to_dev(bus)); in dhd_bus_stop()
2333 pm_runtime_enable(dhd_bus_to_dev(bus)); in dhd_bus_stop()
2338 dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_BUS_STOP); in dhd_bus_stop()
2351 dhd_bus_t *bus = dhd->bus; in dhd_bus_watchdog() local
2369 bus->bus_low_power_state == DHD_BUS_NO_LOW_POWER_STATE) { in dhd_bus_watchdog()
2370 bus->console.count += dhd_watchdog_ms; in dhd_bus_watchdog()
2371 if (bus->console.count >= dhd->dhd_console_ms) { in dhd_bus_watchdog()
2372 bus->console.count -= dhd->dhd_console_ms; in dhd_bus_watchdog()
2374 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_watchdog()
2375 dhd_bus_pcie_pwr_req(bus); in dhd_bus_watchdog()
2379 if (dhdpcie_bus_readconsole(bus) < 0) { in dhd_bus_watchdog()
2383 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_watchdog()
2384 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_watchdog()
2398 static int concate_revision_bcm4358(dhd_bus_t *bus, char *fw_path, char *nv_path) in concate_revision_bcm4358() argument
2407 chiprev = dhd_bus_chiprev(bus); in concate_revision_bcm4358()
2451 static int concate_revision_bcm4359(dhd_bus_t *bus, char *fw_path, char *nv_path) in concate_revision_bcm4359() argument
2460 chip_ver = bus->sih->chiprev; in concate_revision_bcm4359()
2662 dhd_parse_board_information_bcm(dhd_bus_t *bus, int *boardtype, in dhd_parse_board_information_bcm() argument
2680 if (si_backplane_access(bus->sih, boardtype_backplane_addr[i], sizeof(int), in dhd_parse_board_information_bcm()
2686 if (si_backplane_access(bus->sih, boardtype_backplane_addr[i], sizeof(int), in dhd_parse_board_information_bcm()
2698 if (si_backplane_access(bus->sih, CIS_TUPLE_START_ADDRESS + i * sizeof(uint32), in dhd_parse_board_information_bcm()
2749 dhd_bus_t *bus, bool *is_murata_fem) in dhd_find_naming_info_by_chip_rev() argument
2756 if (!bus || !bus->sih) { in dhd_find_naming_info_by_chip_rev()
2757 DHD_ERROR(("%s:bus(%p) or bus->sih is NULL\n", __FUNCTION__, bus)); in dhd_find_naming_info_by_chip_rev()
2760 chip_rev = bus->sih->chiprev; in dhd_find_naming_info_by_chip_rev()
2762 if (dhd_parse_board_information_bcm(bus, &board_type, vid, &vid_length) in dhd_find_naming_info_by_chip_rev()
2805 concate_revision_bcm4361(dhd_bus_t *bus, char *fw_path, char *nv_path) in concate_revision_bcm4361() argument
2822 ARRAYSIZE(bcm4361_naming_table), bus, &is_murata_fem); in concate_revision_bcm4361()
2850 concate_revision_bcm4375(dhd_bus_t *bus, char *fw_path, char *nv_path) in concate_revision_bcm4375() argument
2867 ARRAYSIZE(bcm4375_naming_table), bus, &is_murata_fem); in concate_revision_bcm4375()
2888 concate_revision(dhd_bus_t *bus, char *fw_path, char *nv_path) in concate_revision() argument
2892 if (!bus || !bus->sih) { in concate_revision()
2893 DHD_ERROR(("%s:Bus is Invalid\n", __FUNCTION__)); in concate_revision()
2902 switch (si_chipid(bus->sih)) { in concate_revision()
2906 res = concate_revision_bcm4358(bus, fw_path, nv_path); in concate_revision()
2910 res = concate_revision_bcm4359(bus, fw_path, nv_path); in concate_revision()
2914 res = concate_revision_bcm4361(bus, fw_path, nv_path); in concate_revision()
2917 res = concate_revision_bcm4375(bus, fw_path, nv_path); in concate_revision()
2931 dhd_bus_t *bus = dhd->bus; in dhd_get_chipid() local
2933 if (bus && bus->sih) in dhd_get_chipid()
2934 return (uint16)si_chipid(bus->sih); in dhd_get_chipid()
2947 * If bus->fw_path is empty, or if the download of bus->fw_path failed, firmware contained in header
2953 dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, in dhd_bus_download_firmware() argument
2958 bus->fw_path = pfw_path; in dhd_bus_download_firmware()
2959 bus->nv_path = pnv_path; in dhd_bus_download_firmware()
2962 if (concate_revision(bus, bus->fw_path, bus->nv_path) != 0) { in dhd_bus_download_firmware()
2970 dhd_set_blob_support(bus->dhd, bus->fw_path); in dhd_bus_download_firmware()
2974 __FUNCTION__, bus->fw_path, bus->nv_path)); in dhd_bus_download_firmware()
2975 dhdpcie_dump_resource(bus); in dhd_bus_download_firmware()
2977 ret = dhdpcie_download_firmware(bus, osh); in dhd_bus_download_firmware()
2983 * Loads firmware given by 'bus->fw_path' into PCIe dongle.
2990 * If bus->fw_path is empty, or if the download of bus->fw_path failed, firmware contained in header
2996 dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh) in dhdpcie_download_firmware() argument
3000 uint chipid = bus->sih->chip; in dhdpcie_download_firmware()
3001 uint revid = bus->sih->chiprev; in dhdpcie_download_firmware()
3004 bus->fw_path = fw_path; in dhdpcie_download_firmware()
3005 bus->nv_path = nv_path; in dhdpcie_download_firmware()
3028 snprintf(bus->nv_path, sizeof(nv_path), "%s.nvm", fw_path); in dhdpcie_download_firmware()
3030 snprintf(bus->fw_path, sizeof(fw_path), "%s-firmware.bin", fw_path); in dhdpcie_download_firmware()
3033 DHD_OS_WAKE_LOCK(bus->dhd); in dhdpcie_download_firmware()
3034 ret = _dhdpcie_download_firmware(bus); in dhdpcie_download_firmware()
3036 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhdpcie_download_firmware()
3049 dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path) in dhdpcie_download_code_file() argument
3057 int offset_end = bus->ramsize; in dhdpcie_download_code_file()
3063 if (dhd_bus_get_fw_mode(bus->dhd) == DHD_FLAG_MFG_MODE) { in dhdpcie_download_code_file()
3071 if (dhd_tcm_test_enable && !dhd_bus_tcm_test(bus)) { in dhdpcie_download_code_file()
3081 imgbuf = dhd_os_open_image1(bus->dhd, pfw_path); in dhdpcie_download_code_file()
3092 memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); in dhdpcie_download_code_file()
3103 store_reset = (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || in dhdpcie_download_code_file()
3104 si_setcore(bus->sih, ARMCA7_CORE_ID, 0)); in dhdpcie_download_code_file()
3123 bus->resetinstr = *(((uint32*)memptr)); in dhdpcie_download_code_file()
3125 offset += bus->dongle_ram_base; in dhdpcie_download_code_file()
3140 bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len); in dhdpcie_download_code_file()
3161 MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); in dhdpcie_download_code_file()
3165 dhd_os_close_image1(bus->dhd, imgbuf); in dhdpcie_download_code_file()
3176 dhdpcie_download_nvram(struct dhd_bus *bus) in dhdpcie_download_nvram() argument
3186 pnv_path = bus->nv_path; in dhdpcie_download_nvram()
3192 dhd_get_download_buffer(bus->dhd, NULL, NVRAM, &memblock, (int *)&len); in dhdpcie_download_nvram()
3199 dhd_get_download_buffer(bus->dhd, pnv_path, NVRAM, &memblock, (int *)&len); in dhdpcie_download_nvram()
3240 bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1); in dhdpcie_download_nvram()
3250 MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE); in dhdpcie_download_nvram()
3252 dhd_free_download_buffer(bus->dhd, memblock, MAX_NVRAMBUF_SIZE); in dhdpcie_download_nvram()
3260 dhdpcie_ramsize_read_image(struct dhd_bus *bus, char *buf, int len) in dhdpcie_ramsize_read_image() argument
3269 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) { in dhdpcie_ramsize_read_image()
3271 imgbuf = dhd_os_open_image1(bus->dhd, bus->fw_path); in dhdpcie_ramsize_read_image()
3288 dhd_os_close_image1(bus->dhd, imgbuf); in dhdpcie_ramsize_read_image()
3298 dhdpcie_ramsize_adj(struct dhd_bus *bus) in dhdpcie_ramsize_adj() argument
3310 if (bus->ramsize_adjusted) { in dhdpcie_ramsize_adj()
3317 bus->ramsize_adjusted = TRUE; in dhdpcie_ramsize_adj()
3327 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) { in dhdpcie_ramsize_adj()
3346 memptr = MALLOC(bus->dhd->osh, search_len); in dhdpcie_ramsize_adj()
3353 if (dhdpcie_ramsize_read_image(bus, (char *)memptr, search_len) != BCME_OK) { in dhdpcie_ramsize_adj()
3374 bus->orig_ramsize = LTOH32(ramsize_info.ram_size); in dhdpcie_ramsize_adj()
3375 bus->ramsize = LTOH32(ramsize_info.ram_size); in dhdpcie_ramsize_adj()
3377 bus->ramsize)); in dhdpcie_ramsize_adj()
3385 MFREE(bus->dhd->osh, memptr, search_len); in dhdpcie_ramsize_adj()
3391 * Downloads firmware file given by 'bus->fw_path' into PCIe dongle
3394 * If bus->fw_path is empty, or if the download of bus->fw_path failed, firmware contained in header
3399 _dhdpcie_download_firmware(struct dhd_bus *bus) in _dhdpcie_download_firmware() argument
3407 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) { in _dhdpcie_download_firmware()
3412 dhdpcie_ramsize_adj(bus); in _dhdpcie_download_firmware()
3415 if (dhdpcie_bus_download_state(bus, TRUE)) { in _dhdpcie_download_firmware()
3421 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) { in _dhdpcie_download_firmware()
3422 if (dhdpcie_download_code_file(bus, bus->fw_path)) { in _dhdpcie_download_firmware()
3440 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */ in _dhdpcie_download_firmware()
3443 if (dhdpcie_download_nvram(bus)) { in _dhdpcie_download_firmware()
3449 if (dhdpcie_bus_download_state(bus, FALSE)) { in _dhdpcie_download_firmware()
3461 dhdpcie_bus_readconsole(dhd_bus_t *bus) in dhdpcie_bus_readconsole() argument
3463 dhd_console_t *c = &bus->console; in dhdpcie_bus_readconsole()
3474 if (bus->console_addr == 0) in dhdpcie_bus_readconsole()
3478 addr = bus->console_addr + OFFSETOF(hnd_cons_t, log); in dhdpcie_bus_readconsole()
3487 MFREE(bus->dhd->osh, c->buf, c->bufsize); in dhdpcie_bus_readconsole()
3494 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0) in dhdpcie_bus_readconsole()
3500 if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL) in dhdpcie_bus_readconsole()
3527 if ((rv = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_bus_readconsole()
3533 if ((rv = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_bus_readconsole()
3543 if ((rv = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_bus_readconsole()
3575 dhd_bus_dump_console_buffer(dhd_bus_t *bus) in dhd_bus_dump_console_buffer() argument
3586 if (bus->is_linkdown) { in dhd_bus_dump_console_buffer()
3591 addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log); in dhd_bus_dump_console_buffer()
3592 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, in dhd_bus_dump_console_buffer()
3597 addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size); in dhd_bus_dump_console_buffer()
3598 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, in dhd_bus_dump_console_buffer()
3603 addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx); in dhd_bus_dump_console_buffer()
3604 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, in dhd_bus_dump_console_buffer()
3614 !(console_buffer = MALLOC(bus->dhd->osh, console_size))) { in dhd_bus_dump_console_buffer()
3618 if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr, in dhd_bus_dump_console_buffer()
3646 MFREE(bus->dhd->osh, console_buffer, console_size); in dhd_bus_dump_console_buffer()
3651 * Opens the file given by bus->fw_path, reads part of the file into a buffer and closes the file.
3656 dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size) in dhdpcie_checkdied() argument
3663 pciedev_shared_t *local_pciedev_shared = bus->pcie_sh; in dhdpcie_checkdied()
3680 mbuffer = data = MALLOC(bus->dhd->osh, msize); in dhdpcie_checkdied()
3689 if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) { in dhdpcie_checkdied()
3694 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_checkdied()
3695 DHD_BUS_BUSY_SET_IN_CHECKDIED(bus->dhd); in dhdpcie_checkdied()
3696 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_checkdied()
3698 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_checkdied()
3699 dhd_bus_pcie_pwr_req(bus); in dhdpcie_checkdied()
3701 if ((bcmerror = dhdpcie_readshared(bus)) < 0) { in dhdpcie_checkdied()
3717 if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) { in dhdpcie_checkdied()
3722 (bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT) in dhdpcie_checkdied()
3725 if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) { in dhdpcie_checkdied()
3728 if (bus->pcie_sh->assert_exp_addr != 0) { in dhdpcie_checkdied()
3730 if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_checkdied()
3731 bus->pcie_sh->assert_exp_addr, in dhdpcie_checkdied()
3740 if (bus->pcie_sh->assert_file_addr != 0) { in dhdpcie_checkdied()
3742 if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_checkdied()
3743 bus->pcie_sh->assert_file_addr, in dhdpcie_checkdied()
3752 bcm_bprintf(&strbuf, " line %d ", bus->pcie_sh->assert_line); in dhdpcie_checkdied()
3755 if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) { in dhdpcie_checkdied()
3756 trap_t *tr = &bus->dhd->last_trap_info; in dhdpcie_checkdied()
3758 if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, in dhdpcie_checkdied()
3759 bus->pcie_sh->trap_addr, (uint8*)tr, sizeof(trap_t))) < 0) { in dhdpcie_checkdied()
3760 bus->dhd->dongle_trap_occured = TRUE; in dhdpcie_checkdied()
3763 dhd_bus_dump_trap_info(bus, &strbuf); in dhdpcie_checkdied()
3767 if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) { in dhdpcie_checkdied()
3770 dhd_bus_dump_console_buffer(bus); in dhdpcie_checkdied()
3771 dhd_prot_debug_info_print(bus->dhd); in dhdpcie_checkdied()
3775 if (bus->dhd->memdump_enabled) { in dhdpcie_checkdied()
3777 bus->dhd->collect_sssr = TRUE; in dhdpcie_checkdied()
3779 bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP; in dhdpcie_checkdied()
3780 dhdpcie_mem_dump(bus); in dhdpcie_checkdied()
3788 bus->dhd->dongle_trap_occured = TRUE; in dhdpcie_checkdied()
3792 dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_TRAP); in dhdpcie_checkdied()
3795 copy_hang_info_trap(bus->dhd); in dhdpcie_checkdied()
3797 dhd_schedule_reset(bus->dhd); in dhdpcie_checkdied()
3802 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_checkdied()
3803 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_checkdied()
3806 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_checkdied()
3807 DHD_BUS_BUSY_CLEAR_IN_CHECKDIED(bus->dhd); in dhdpcie_checkdied()
3808 dhd_os_busbusy_wake(bus->dhd); in dhdpcie_checkdied()
3809 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_checkdied()
3812 MFREE(bus->dhd->osh, mbuffer, msize); in dhdpcie_checkdied()
3814 MFREE(bus->dhd->osh, str, maxstrlen); in dhdpcie_checkdied()
3820 void dhdpcie_mem_dump_bugcheck(dhd_bus_t *bus, uint8 *buf) in dhdpcie_mem_dump_bugcheck() argument
3828 if (bus == NULL) { in dhdpcie_mem_dump_bugcheck()
3832 start = bus->dongle_ram_base; in dhdpcie_mem_dump_bugcheck()
3834 /* check for dead bus */ in dhdpcie_mem_dump_bugcheck()
3837 ret = dhdpcie_bus_membytes(bus, FALSE, start, (uint8*)&test_word, read_size); in dhdpcie_mem_dump_bugcheck()
3838 /* if read error or bus timeout */ in dhdpcie_mem_dump_bugcheck()
3845 size = bus->ramsize; in dhdpcie_mem_dump_bugcheck()
3850 if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) { in dhdpcie_mem_dump_bugcheck()
3859 bus->dhd->soc_ram = buf; in dhdpcie_mem_dump_bugcheck()
3860 bus->dhd->soc_ram_length = bus->ramsize; in dhdpcie_mem_dump_bugcheck()
3866 dhdpcie_get_mem_dump(dhd_bus_t *bus) in dhdpcie_get_mem_dump() argument
3874 if (!bus) { in dhdpcie_get_mem_dump()
3875 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__)); in dhdpcie_get_mem_dump()
3879 if (!bus->dhd) { in dhdpcie_get_mem_dump()
3884 size = bus->ramsize; /* Full mem size */ in dhdpcie_get_mem_dump()
3885 start = bus->dongle_ram_base; /* Start address */ in dhdpcie_get_mem_dump()
3888 p_buf = dhd_get_fwdump_buf(bus->dhd, size); in dhdpcie_get_mem_dump()
3900 ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size); in dhdpcie_get_mem_dump()
3904 bus->dhd->memdump_success = FALSE; in dhdpcie_get_mem_dump()
3920 dhdpcie_mem_dump(dhd_bus_t *bus) in dhdpcie_mem_dump() argument
3930 if (bus->is_linkdown) { in dhdpcie_mem_dump()
3933 ASSERT(bus->dhd->memdump_enabled != DUMP_MEMFILE_BUGON); in dhdpcie_mem_dump()
3938 dhdp = bus->dhd; in dhdpcie_mem_dump()
3945 DHD_ERROR(("%s: bus is down! can't collect mem dump. \n", __FUNCTION__)); in dhdpcie_mem_dump()
3950 if (pm_runtime_get_sync(dhd_bus_to_dev(bus)) < 0) in dhdpcie_mem_dump()
3954 ret = dhdpcie_get_mem_dump(bus); in dhdpcie_mem_dump()
3965 pm_runtime_mark_last_busy(dhd_bus_to_dev(bus)); in dhdpcie_mem_dump()
3966 pm_runtime_put_autosuspend(dhd_bus_to_dev(bus)); in dhdpcie_mem_dump()
3980 return dhdpcie_get_mem_dump(dhdp->bus); in dhd_bus_get_mem_dump()
3986 dhd_bus_t *bus = dhdp->bus; in dhd_bus_mem_dump() local
3990 DHD_ERROR(("%s bus is down\n", __FUNCTION__)); in dhd_bus_mem_dump()
4001 DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state, so skip\n", in dhd_bus_mem_dump()
4007 ret = dhdpcie_mem_dump(bus); in dhd_bus_mem_dump()
4014 dhd_socram_dump(dhd_bus_t *bus) in dhd_socram_dump() argument
4017 DHD_OS_WAKE_LOCK(bus->dhd); in dhd_socram_dump()
4018 dhd_bus_mem_dump(bus->dhd); in dhd_socram_dump()
4019 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhd_socram_dump()
4031 dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size) in dhdpcie_bus_membytes() argument
4037 if (write && bus->is_linkdown) { in dhdpcie_bus_membytes()
4042 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_bus_membytes()
4043 dhd_bus_pcie_pwr_req(bus); in dhdpcie_bus_membytes()
4065 dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data)); in dhdpcie_bus_membytes()
4069 dhdpcie_bus_wtcm32(bus, address, *((uint32*)data)); in dhdpcie_bus_membytes()
4074 dhdpcie_bus_wtcm8(bus, address, *data); in dhdpcie_bus_membytes()
4088 *(uint64 *)data = dhdpcie_bus_rtcm64(bus, address); in dhdpcie_bus_membytes()
4093 *(uint32 *)data = dhdpcie_bus_rtcm32(bus, address); in dhdpcie_bus_membytes()
4098 *data = dhdpcie_bus_rtcm8(bus, address); in dhdpcie_bus_membytes()
4108 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_bus_membytes()
4109 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_bus_membytes()
4119 dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs) in dhd_bus_schedule_queue() argument
4124 dhd_pub_t *dhdp = bus->dhd; in dhd_bus_schedule_queue()
4129 if (flow_id >= bus->max_submission_rings) { in dhd_bus_schedule_queue()
4131 flow_id, bus->max_submission_rings)); in dhd_bus_schedule_queue()
4135 flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id); in dhd_bus_schedule_queue()
4168 while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { in dhd_bus_schedule_queue()
4180 if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_HOLD) { in dhd_bus_schedule_queue()
4181 ret = dhd_tcpack_check_xmit(bus->dhd, txp); in dhd_bus_schedule_queue()
4200 ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex); in dhd_bus_schedule_queue()
4203 dhd_prot_txdata_write_flush(bus->dhd, flow_id); in dhd_bus_schedule_queue()
4205 dhd_flow_queue_reinsert(bus->dhd, queue, txp); in dhd_bus_schedule_queue()
4215 dhd_prot_txdata_write_flush(bus->dhd, flow_id); in dhd_bus_schedule_queue()
4218 dhd_prot_txdata_write_flush(bus->dhd, flow_id); in dhd_bus_schedule_queue()
4228 dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx) in dhd_bus_txdata() argument
4240 if (!bus->dhd->flowid_allocator) { in dhd_bus_txdata()
4247 flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); in dhd_bus_txdata()
4253 if ((flowid >= bus->dhd->num_flow_rings) || in dhd_bus_txdata()
4278 if (bus->enable_idle_flowring_mgmt) { in dhd_bus_txdata()
4280 dhd_flow_ring_move_to_active_list_head(bus, flow_ring_node); in dhd_bus_txdata()
4287 dhd_bus_flow_ring_resume_request(bus, in dhd_bus_txdata()
4312 if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK) in dhd_bus_txdata()
4327 ret = dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */ in dhd_bus_txdata()
4333 if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) { in dhd_bus_txdata()
4346 PKTCFREE(bus->dhd->osh, txp, TRUE); in dhd_bus_txdata()
4351 dhd_bus_stop_queue(struct dhd_bus *bus) in dhd_bus_stop_queue() argument
4353 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON); in dhd_bus_stop_queue()
4357 dhd_bus_start_queue(struct dhd_bus *bus) in dhd_bus_start_queue() argument
4361 * bus is not in a state to turn on. in dhd_bus_start_queue()
4367 if (dhd_prot_check_tx_resource(bus->dhd)) { in dhd_bus_start_queue()
4372 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF); in dhd_bus_start_queue()
4378 dhd_bus_t *bus = dhd->bus; in dhd_bus_console_in() local
4382 if (bus->console_addr == 0) in dhd_bus_console_in()
4386 if (bus->dhd->dongle_reset) { in dhd_bus_console_in()
4391 addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx); in dhd_bus_console_in()
4393 if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) in dhd_bus_console_in()
4397 addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf); in dhd_bus_console_in()
4398 if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0) in dhd_bus_console_in()
4402 addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in); in dhd_bus_console_in()
4404 if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) in dhd_bus_console_in()
4408 dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT); in dhd_bus_console_in()
4418 dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count) in dhd_bus_rx_frame() argument
4420 dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0); in dhd_bus_rx_frame()
4424 dhdpcie_setbar1win(dhd_bus_t *bus, uint32 addr) in dhdpcie_setbar1win() argument
4426 dhdpcie_os_setbar1win(bus, addr); in dhdpcie_setbar1win()
4431 dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data) in dhdpcie_bus_wtcm8() argument
4433 if (bus->is_linkdown) { in dhdpcie_bus_wtcm8()
4437 dhdpcie_os_wtcm8(bus, offset, data); in dhdpcie_bus_wtcm8()
4442 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset) in dhdpcie_bus_rtcm8() argument
4445 if (bus->is_linkdown) { in dhdpcie_bus_rtcm8()
4449 data = dhdpcie_os_rtcm8(bus, offset); in dhdpcie_bus_rtcm8()
4455 dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data) in dhdpcie_bus_wtcm32() argument
4457 if (bus->is_linkdown) { in dhdpcie_bus_wtcm32()
4461 dhdpcie_os_wtcm32(bus, offset, data); in dhdpcie_bus_wtcm32()
4465 dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data) in dhdpcie_bus_wtcm16() argument
4467 if (bus->is_linkdown) { in dhdpcie_bus_wtcm16()
4471 dhdpcie_os_wtcm16(bus, offset, data); in dhdpcie_bus_wtcm16()
4476 dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data) in dhdpcie_bus_wtcm64() argument
4478 if (bus->is_linkdown) { in dhdpcie_bus_wtcm64()
4482 dhdpcie_os_wtcm64(bus, offset, data); in dhdpcie_bus_wtcm64()
4488 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset) in dhdpcie_bus_rtcm16() argument
4491 if (bus->is_linkdown) { in dhdpcie_bus_rtcm16()
4495 data = dhdpcie_os_rtcm16(bus, offset); in dhdpcie_bus_rtcm16()
4501 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset) in dhdpcie_bus_rtcm32() argument
4504 if (bus->is_linkdown) { in dhdpcie_bus_rtcm32()
4508 data = dhdpcie_os_rtcm32(bus, offset); in dhdpcie_bus_rtcm32()
4515 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset) in dhdpcie_bus_rtcm64() argument
4518 if (bus->is_linkdown) { in dhdpcie_bus_rtcm64()
4522 data = dhdpcie_os_rtcm64(bus, offset); in dhdpcie_bus_rtcm64()
4530 dhd_bus_cmn_writeshared(dhd_bus_t *bus, void *data, uint32 len, uint8 type, uint16 ringid) in dhd_bus_cmn_writeshared() argument
4537 if (bus->is_linkdown) { in dhd_bus_cmn_writeshared()
4542 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_cmn_writeshared()
4543 dhd_bus_pcie_pwr_req(bus); in dhd_bus_cmn_writeshared()
4547 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_dma_scratch_buffer); in dhd_bus_cmn_writeshared()
4549 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4556 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_dma_scratch_buffer_len); in dhd_bus_cmn_writeshared()
4557 dhdpcie_bus_wtcm32(bus, addr, (uint32) HTOL32(*(uint32 *)data)); in dhd_bus_cmn_writeshared()
4565 addr = DHD_RING_INFO_MEMBER_ADDR(bus, h2d_w_idx_hostaddr); in dhd_bus_cmn_writeshared()
4566 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4574 addr = DHD_RING_INFO_MEMBER_ADDR(bus, h2d_r_idx_hostaddr); in dhd_bus_cmn_writeshared()
4575 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4583 addr = DHD_RING_INFO_MEMBER_ADDR(bus, d2h_w_idx_hostaddr); in dhd_bus_cmn_writeshared()
4584 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4592 addr = DHD_RING_INFO_MEMBER_ADDR(bus, d2h_r_idx_hostaddr); in dhd_bus_cmn_writeshared()
4593 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4601 addr = DHD_RING_INFO_MEMBER_ADDR(bus, ifrm_w_idx_hostaddr); in dhd_bus_cmn_writeshared()
4602 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8*) &long_data, len); in dhd_bus_cmn_writeshared()
4609 addr = DHD_RING_MEM_MEMBER_ADDR(bus, ringid, len_items); in dhd_bus_cmn_writeshared()
4610 dhdpcie_bus_wtcm16(bus, addr, (uint16) HTOL16(*(uint16 *)data)); in dhd_bus_cmn_writeshared()
4614 addr = DHD_RING_MEM_MEMBER_ADDR(bus, ringid, max_item); in dhd_bus_cmn_writeshared()
4615 dhdpcie_bus_wtcm16(bus, addr, (uint16) HTOL16(*(uint16 *)data)); in dhd_bus_cmn_writeshared()
4620 addr = DHD_RING_MEM_MEMBER_ADDR(bus, ringid, base_addr); in dhd_bus_cmn_writeshared()
4621 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *) &long_data, len); in dhd_bus_cmn_writeshared()
4628 addr = bus->ring_sh[ringid].ring_state_w; in dhd_bus_cmn_writeshared()
4629 dhdpcie_bus_wtcm16(bus, addr, (uint16) HTOL16(*(uint16 *)data)); in dhd_bus_cmn_writeshared()
4633 addr = bus->ring_sh[ringid].ring_state_r; in dhd_bus_cmn_writeshared()
4634 dhdpcie_bus_wtcm16(bus, addr, (uint16) HTOL16(*(uint16 *)data)); in dhd_bus_cmn_writeshared()
4638 addr = bus->d2h_mb_data_ptr_addr; in dhd_bus_cmn_writeshared()
4639 dhdpcie_bus_wtcm32(bus, addr, (uint32) HTOL32(*(uint32 *)data)); in dhd_bus_cmn_writeshared()
4643 addr = bus->h2d_mb_data_ptr_addr; in dhd_bus_cmn_writeshared()
4644 dhdpcie_bus_wtcm32(bus, addr, (uint32) HTOL32(*(uint32 *)data)); in dhd_bus_cmn_writeshared()
4648 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_cap); in dhd_bus_cmn_writeshared()
4649 dhdpcie_bus_wtcm32(bus, addr, (uint32) HTOL32(*(uint32 *)data)); in dhd_bus_cmn_writeshared()
4654 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_trap_addr); in dhd_bus_cmn_writeshared()
4655 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *) &long_data, len); in dhd_bus_cmn_writeshared()
4660 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_scb_addr); in dhd_bus_cmn_writeshared()
4662 dhdpcie_bus_wtcm64(bus, addr, (uint64) HTOL64(*(uint64 *)data)); in dhd_bus_cmn_writeshared()
4664 dhdpcie_bus_wtcm32(bus, addr, *((uint32*)data)); in dhd_bus_cmn_writeshared()
4673 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_cmn_writeshared()
4674 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_cmn_writeshared()
4680 dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid) in dhd_bus_cmn_readshared() argument
4684 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_cmn_readshared()
4685 dhd_bus_pcie_pwr_req(bus); in dhd_bus_cmn_readshared()
4689 addr = bus->ring_sh[ringid].ring_state_w; in dhd_bus_cmn_readshared()
4690 *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, addr)); in dhd_bus_cmn_readshared()
4694 addr = bus->ring_sh[ringid].ring_state_r; in dhd_bus_cmn_readshared()
4695 *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, addr)); in dhd_bus_cmn_readshared()
4699 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, total_lfrag_pkt_cnt); in dhd_bus_cmn_readshared()
4700 *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, addr)); in dhd_bus_cmn_readshared()
4704 addr = bus->h2d_mb_data_ptr_addr; in dhd_bus_cmn_readshared()
4705 *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, addr)); in dhd_bus_cmn_readshared()
4709 addr = bus->d2h_mb_data_ptr_addr; in dhd_bus_cmn_readshared()
4710 *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, addr)); in dhd_bus_cmn_readshared()
4714 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, max_host_rxbufs); in dhd_bus_cmn_readshared()
4715 *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, addr)); in dhd_bus_cmn_readshared()
4719 addr = DHD_PCIE_SHARED_MEMBER_ADDR(bus, host_scb_size); in dhd_bus_cmn_readshared()
4720 *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, addr)); in dhd_bus_cmn_readshared()
4726 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_cmn_readshared()
4727 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_cmn_readshared()
4731 uint32 dhd_bus_get_sharedflags(dhd_bus_t *bus) in dhd_bus_get_sharedflags() argument
4733 return ((pciedev_shared_t*)bus->pcie_sh)->flags; in dhd_bus_get_sharedflags()
4750 dhd_bus_t *bus = dhdp->bus; in dhd_bus_iovar_op() local
4781 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_iovar_op()
4785 dhd_bus_pcie_pwr_req(bus); in dhd_bus_iovar_op()
4806 bcmerror = dhdpcie_bus_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size); in dhd_bus_iovar_op()
4817 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_iovar_op()
4821 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_iovar_op()
5036 int dhd_buzzz_dump_dngl(dhd_bus_t *bus) in dhd_buzzz_dump_dngl() argument
5044 if (bus->dhd->busstate != DHD_BUS_DATA) { in dhd_buzzz_dump_dngl()
5047 if ((page_p = (char *)MALLOC(bus->dhd->osh, 4096)) == NULL) { in dhd_buzzz_dump_dngl()
5051 if ((buzzz_p = MALLOC(bus->dhd->osh, sizeof(bcm_buzzz_t))) == NULL) { in dhd_buzzz_dump_dngl()
5056 ret = dhdpcie_readshared(bus); in dhd_buzzz_dump_dngl()
5062 sh = bus->pcie_sh; in dhd_buzzz_dump_dngl()
5068 dhdpcie_bus_membytes(bus, FALSE, (ulong)sh->buzz_dbg_ptr, in dhd_buzzz_dump_dngl()
5086 buffer_p = MALLOC(bus->dhd->osh, buzzz_p->buffer_sz); in dhd_buzzz_dump_dngl()
5093 dhdpcie_bus_membytes(bus, FALSE, (uint32)buzzz_p->log, /* Trace */ in dhd_buzzz_dump_dngl()
5110 MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); buffer_p = NULL; in dhd_buzzz_dump_dngl()
5115 if (page_p) MFREE(bus->dhd->osh, page_p, 4096); in dhd_buzzz_dump_dngl()
5116 if (buzzz_p) MFREE(bus->dhd->osh, buzzz_p, sizeof(bcm_buzzz_t)); in dhd_buzzz_dump_dngl()
5117 if (buffer_p) MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); in dhd_buzzz_dump_dngl()
5127 pcie2_mdiosetblock(dhd_bus_t *bus, uint blk) in pcie2_mdiosetblock() argument
5135 si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdioctrl); in pcie2_mdiosetblock()
5136 si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0, mdiodata); in pcie2_mdiosetblock()
5141 uint mdioctrl_read = si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, in pcie2_mdiosetblock()
5177 dhdpcie_enum_reg_init(dhd_bus_t *bus) in dhdpcie_enum_reg_init() argument
5180 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5185 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5188 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5190 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5194 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5197 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5200 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5202 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5206 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5209 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5211 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5215 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5218 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5220 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_enum_reg_init()
5225 dhd_bus_perform_flr(dhd_bus_t *bus, bool force_fail) in dhd_bus_perform_flr() argument
5233 if (PCIE_ENUM_RESET_WAR_ENAB(bus->sih->buscorerev)) { in dhd_bus_perform_flr()
5234 if (bus->pcie_mailbox_mask != 0) { in dhd_bus_perform_flr()
5235 dhdpcie_bus_intr_disable(bus); in dhd_bus_perform_flr()
5238 dhdpcie_enum_reg_init(bus); in dhd_bus_perform_flr()
5242 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_DEVICE_CAPABILITY, sizeof(val)); in dhd_bus_perform_flr()
5251 else if ((bus->sih->chip == CYW55560_CHIP_ID) || (bus->sih->chip == BCM4375_CHIP_ID)) { in dhd_bus_perform_flr()
5258 DHD_PCIE_CONFIG_SAVE(bus); in dhd_bus_perform_flr()
5263 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_DEVICE_CONTROL, sizeof(val)); in dhd_bus_perform_flr()
5267 OSL_PCI_WRITE_CONFIG(bus->osh, PCIE_CFG_DEVICE_CONTROL, sizeof(val), val); in dhd_bus_perform_flr()
5276 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_SUBSYSTEM_CONTROL, sizeof(val)); in dhd_bus_perform_flr()
5282 OSL_PCI_WRITE_CONFIG(bus->osh, PCIE_CFG_SUBSYSTEM_CONTROL, sizeof(val), val); in dhd_bus_perform_flr()
5284 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_SUBSYSTEM_CONTROL, sizeof(val)); in dhd_bus_perform_flr()
5292 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_DEVICE_CONTROL, sizeof(val)); in dhd_bus_perform_flr()
5296 OSL_PCI_WRITE_CONFIG(bus->osh, PCIE_CFG_DEVICE_CONTROL, sizeof(val), val); in dhd_bus_perform_flr()
5302 val = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_SUBSYSTEM_CONTROL, sizeof(val)); in dhd_bus_perform_flr()
5314 bus->flr_force_fail = FALSE; in dhd_bus_perform_flr()
5322 DHD_PCIE_CONFIG_RESTORE(bus); in dhd_bus_perform_flr()
5338 dhd_bus_perform_bp_reset(struct dhd_bus *bus) in dhd_bus_perform_bp_reset() argument
5342 uint dar_clk_ctrl_status_reg = DAR_CLK_CTRL(bus->sih->buscorerev); in dhd_bus_perform_bp_reset()
5351 val = OSL_PCI_READ_CONFIG(bus->osh, PCIECFGREG_LINK_STATUS_CTRL, sizeof(val)); in dhd_bus_perform_bp_reset()
5355 OSL_PCI_WRITE_CONFIG(bus->osh, PCIECFGREG_LINK_STATUS_CTRL, sizeof(val), val); in dhd_bus_perform_bp_reset()
5364 val = OSL_PCI_READ_CONFIG(bus->osh, PCIECFGREG_SPROM_CTRL, sizeof(val)); in dhd_bus_perform_bp_reset()
5368 OSL_PCI_WRITE_CONFIG(bus->osh, PCIECFGREG_SPROM_CTRL, sizeof(val), val); in dhd_bus_perform_bp_reset()
5379 val = OSL_PCI_READ_CONFIG(bus->osh, PCIECFGREG_SPROM_CTRL, sizeof(val)); in dhd_bus_perform_bp_reset()
5397 val = si_corereg(bus->sih, bus->sih->buscoreidx, in dhd_bus_perform_bp_reset()
5415 val = OSL_PCI_READ_CONFIG(bus->osh, PCIECFGREG_LINK_STATUS_CTRL, sizeof(val)); in dhd_bus_perform_bp_reset()
5419 OSL_PCI_WRITE_CONFIG(bus->osh, PCIECFGREG_LINK_STATUS_CTRL, sizeof(val), val); in dhd_bus_perform_bp_reset()
5430 dhd_bus_t *bus = dhdp->bus; in dhd_bus_devreset() local
5442 bus->dhd->up = FALSE; in dhd_bus_devreset()
5448 dhdpcie_advertise_bus_cleanup(bus->dhd); in dhd_bus_devreset()
5450 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhd_bus_devreset()
5452 atomic_set(&bus->dhd->block_bus, TRUE); in dhd_bus_devreset()
5453 dhd_flush_rx_tx_wq(bus->dhd); in dhd_bus_devreset()
5458 dhd_bus_oob_intr_set(bus->dhd, FALSE); in dhd_bus_devreset()
5459 dhd_bus_oob_intr_unregister(bus->dhd); in dhd_bus_devreset()
5462 dhd_bus_stop(bus, TRUE); in dhd_bus_devreset()
5463 if (bus->intr) { in dhd_bus_devreset()
5464 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhd_bus_devreset()
5465 dhdpcie_bus_intr_disable(bus); in dhd_bus_devreset()
5466 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhd_bus_devreset()
5467 dhdpcie_free_irq(bus); in dhd_bus_devreset()
5469 dhd_deinit_bus_lock(bus); in dhd_bus_devreset()
5470 dhd_deinit_backplane_access_lock(bus); in dhd_bus_devreset()
5471 dhd_bus_release_dongle(bus); in dhd_bus_devreset()
5472 dhdpcie_bus_free_resource(bus); in dhd_bus_devreset()
5473 bcmerror = dhdpcie_bus_disable_device(bus); in dhd_bus_devreset()
5478 atomic_set(&bus->dhd->block_bus, FALSE); in dhd_bus_devreset()
5481 /* Clean up protocol data after Bus Master Enable bit clear in dhd_bus_devreset()
5495 bcmerror = dhdpcie_bus_clock_stop(bus); in dhd_bus_devreset()
5500 atomic_set(&bus->dhd->block_bus, FALSE); in dhd_bus_devreset()
5505 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_devreset()
5507 bus->dhd->busstate = DHD_BUS_DOWN; in dhd_bus_devreset()
5508 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_devreset()
5510 atomic_set(&bus->dhd->block_bus, FALSE); in dhd_bus_devreset()
5513 if (bus->intr) { in dhd_bus_devreset()
5514 dhdpcie_free_irq(bus); in dhd_bus_devreset()
5518 dhd_bus_oob_intr_set(bus->dhd, FALSE); in dhd_bus_devreset()
5519 dhd_bus_oob_intr_unregister(bus->dhd); in dhd_bus_devreset()
5521 dhd_dpc_kill(bus->dhd); in dhd_bus_devreset()
5522 if (!bus->no_bus_init) { in dhd_bus_devreset()
5523 dhd_bus_release_dongle(bus); in dhd_bus_devreset()
5524 dhdpcie_bus_free_resource(bus); in dhd_bus_devreset()
5525 bcmerror = dhdpcie_bus_disable_device(bus); in dhd_bus_devreset()
5531 /* Clean up protocol data after Bus Master Enable bit clear in dhd_bus_devreset()
5546 bus->no_bus_init = FALSE; in dhd_bus_devreset()
5549 bcmerror = dhdpcie_bus_clock_stop(bus); in dhd_bus_devreset()
5558 bus->dhd->dongle_reset = TRUE; in dhd_bus_devreset()
5562 if (bus->dhd->busstate == DHD_BUS_DOWN) { in dhd_bus_devreset()
5567 bcmerror = dhdpcie_bus_clock_start(bus); in dhd_bus_devreset()
5583 dhd_bus_aspm_enable_rc_ep(bus, FALSE); in dhd_bus_devreset()
5586 bus->is_linkdown = 0; in dhd_bus_devreset()
5587 bus->cto_triggered = 0; in dhd_bus_devreset()
5589 bus->read_shm_fail = FALSE; in dhd_bus_devreset()
5591 bcmerror = dhdpcie_bus_enable_device(bus); in dhd_bus_devreset()
5598 bcmerror = dhdpcie_bus_alloc_resource(bus); in dhd_bus_devreset()
5605 bcmerror = dhdpcie_bus_dongle_attach(bus); in dhd_bus_devreset()
5612 bcmerror = dhd_bus_request_irq(bus); in dhd_bus_devreset()
5619 bus->dhd->dongle_reset = FALSE; in dhd_bus_devreset()
5622 dhd_irq_set_affinity(bus->dhd, cpumask_of(1)); in dhd_bus_devreset()
5632 bus->dhd->up = TRUE; in dhd_bus_devreset()
5634 if (bus->dhd->dhd_watchdog_ms_backup) { in dhd_bus_devreset()
5637 dhd_os_wd_timer(bus->dhd, bus->dhd->dhd_watchdog_ms_backup); in dhd_bus_devreset()
5648 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_devreset()
5650 bus->dhd->busstate = DHD_BUS_DOWN; in dhd_bus_devreset()
5651 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_devreset()
5658 pcie2_mdioop(dhd_bus_t *bus, uint physmedia, uint regaddr, bool write, uint *val, in pcie2_mdioop() argument
5664 pcie2_mdiosetblock(bus, physmedia); in pcie2_mdioop()
5676 si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdio_ctrl); in pcie2_mdioop()
5680 si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0, in pcie2_mdioop()
5687 uint done_val = si_corereg(bus->sih, bus->sih->buscoreidx, reg32, 0, 0); in pcie2_mdioop()
5690 *val = si_corereg(bus->sih, bus->sih->buscoreidx, in pcie2_mdioop()
5720 serialized_backplane_access(dhd_bus_t *bus, uint addr, uint size, uint *val, bool read) in serialized_backplane_access() argument
5724 DHD_BACKPLANE_ACCESS_LOCK(bus->backplane_access_lock, flags); in serialized_backplane_access()
5725 ret = si_backplane_access(bus->sih, addr, size, val, read); in serialized_backplane_access()
5726 DHD_BACKPLANE_ACCESS_UNLOCK(bus->backplane_access_lock, flags); in serialized_backplane_access()
5755 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_set_dma_ring_indices()
5764 * IOVAR handler of the DHD bus layer (in this case, the PCIe bus).
5773 dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name, in dhdpcie_bus_doiovar() argument
5800 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) || in dhdpcie_bus_doiovar()
5809 bcmerror = dhdpcie_downloadvars(bus, arg, len); in dhdpcie_bus_doiovar()
5813 si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, in dhdpcie_bus_doiovar()
5815 si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0, in dhdpcie_bus_doiovar()
5820 si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, in dhdpcie_bus_doiovar()
5822 int_val = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_bus_doiovar()
5828 si_corereg(bus->sih, bus->sih->buscoreidx, int_val, ~0, int_val2); in dhdpcie_bus_doiovar()
5840 if (serialized_backplane_access(bus, addr, size, (uint *)&int_val, TRUE) != BCME_OK) in dhdpcie_bus_doiovar()
5859 if (serialized_backplane_access(bus, addr, size, in dhdpcie_bus_doiovar()
5874 addr = sdreg.offset | SI_ENUM_BASE(bus->sih); in dhdpcie_bus_doiovar()
5877 if (serialized_backplane_access(bus, addr, size, (uint *)&int_val, TRUE) != BCME_OK) in dhdpcie_bus_doiovar()
5894 addr = sdreg.offset | SI_ENUM_BASE(bus->sih); in dhdpcie_bus_doiovar()
5896 if (serialized_backplane_access(bus, addr, size, in dhdpcie_bus_doiovar()
5907 if (!PCIE_GEN2(bus->sih)) { in dhdpcie_bus_doiovar()
5913 if (!pcie2_mdioop(bus, int_val, int_val2, FALSE, &val, FALSE)) { in dhdpcie_bus_doiovar()
5923 if (!PCIE_GEN2(bus->sih)) { in dhdpcie_bus_doiovar()
5928 if (pcie2_mdioop(bus, int_val, int_val2, TRUE, (uint *)&int_val3, FALSE)) { in dhdpcie_bus_doiovar()
5934 int_val = si_corereg(bus->sih, bus->sih->buscoreidx, int_val, 0, 0); in dhdpcie_bus_doiovar()
5939 OSL_PCI_WRITE_CONFIG(bus->osh, int_val, 4, int_val2); in dhdpcie_bus_doiovar()
5943 int_val = OSL_PCI_READ_CONFIG(bus->osh, int_val, 4); in dhdpcie_bus_doiovar()
5948 bcmerror = dhdpcie_bus_lpback_req(bus, int_val); in dhdpcie_bus_doiovar()
5962 bcmerror = dhdpcie_bus_dmaxfer_req(bus, dmaxfer->num_bytes, in dhdpcie_bus_doiovar()
5968 bcmerror = dhdmsgbuf_dmaxfer_status(bus->dhd, dmaxfer); in dhdpcie_bus_doiovar()
5982 bcmerror = dhdmsgbuf_dmaxfer_status(bus->dhd, dmaxfer); in dhdpcie_bus_doiovar()
5987 int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0; in dhdpcie_bus_doiovar()
6000 ret = dhd_os_busbusy_wait_condition(bus->dhd, in dhdpcie_bus_doiovar()
6001 &bus->dhd->dhd_bus_busy_state, DHD_BUS_BUSY_IN_DHD_IOVAR); in dhdpcie_bus_doiovar()
6004 __FUNCTION__, bus->dhd->dhd_bus_busy_state)); in dhdpcie_bus_doiovar()
6008 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6009 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd); in dhdpcie_bus_doiovar()
6010 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6012 dhdpcie_bus_suspend(bus, TRUE, TRUE); in dhdpcie_bus_doiovar()
6014 dhdpcie_bus_suspend(bus, TRUE); in dhdpcie_bus_doiovar()
6017 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6018 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd); in dhdpcie_bus_doiovar()
6019 dhd_os_busbusy_wake(bus->dhd); in dhdpcie_bus_doiovar()
6020 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6023 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6024 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd); in dhdpcie_bus_doiovar()
6025 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6027 dhdpcie_bus_suspend(bus, FALSE); in dhdpcie_bus_doiovar()
6029 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6030 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd); in dhdpcie_bus_doiovar()
6031 dhd_os_busbusy_wake(bus->dhd); in dhdpcie_bus_doiovar()
6032 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_doiovar()
6037 int_val = (int32)bus->ramsize; in dhdpcie_bus_doiovar()
6069 if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || in dhdpcie_bus_doiovar()
6070 si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) { in dhdpcie_bus_doiovar()
6072 if (set && address == bus->dongle_ram_base) { in dhdpcie_bus_doiovar()
6073 bus->resetinstr = *(((uint32*)params) + 2); in dhdpcie_bus_doiovar()
6077 if ((bus->orig_ramsize) && in dhdpcie_bus_doiovar()
6078 ((address > bus->orig_ramsize) || (address + size > bus->orig_ramsize))) in dhdpcie_bus_doiovar()
6081 si_socdevram(bus->sih, FALSE, &enable, &protect, &remap); in dhdpcie_bus_doiovar()
6084 __FUNCTION__, bus->orig_ramsize, size, address)); in dhdpcie_bus_doiovar()
6091 if (!REMAP_ENAB(bus) && (address >= SOCDEVRAM_ARM_ADDR)) { in dhdpcie_bus_doiovar()
6092 uint32 devramsize = si_socdevram_size(bus->sih); in dhdpcie_bus_doiovar()
6107 } else if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address) && remap) { in dhdpcie_bus_doiovar()
6123 bcmerror = dhdpcie_bus_membytes(bus, set, address, data, size); in dhdpcie_bus_doiovar()
6146 if (si_setcoreidx(bus->sih, ddi.index) == NULL) { in dhdpcie_bus_doiovar()
6150 ddo->address = si_addrspace(bus->sih, CORE_SLAVE_PORT_0, CORE_BASE_ADDR_0); in dhdpcie_bus_doiovar()
6153 ddo->id = si_coreid(bus->sih); in dhdpcie_bus_doiovar()
6154 ddo->rev = si_corerev(bus->sih); in dhdpcie_bus_doiovar()
6158 *p++ = si_corereg(bus->sih, ddi.index, ddi.offset, 0, 0); in dhdpcie_bus_doiovar()
6174 strncpy(arg, bus->dhd->fw_capabilities, in dhdpcie_bus_doiovar()
6175 MIN(strlen(bus->dhd->fw_capabilities), (size_t)len)); in dhdpcie_bus_doiovar()
6183 DHD_PERIM_UNLOCK(bus->dhd); in dhdpcie_bus_doiovar()
6185 debugger_init((void *) bus, &bus_ops, int_val, SI_ENUM_BASE(bus->sih)); in dhdpcie_bus_doiovar()
6189 DHD_PERIM_LOCK(bus->dhd); in dhdpcie_bus_doiovar()
6196 bcmerror = dhd_buzzz_dump_dngl(bus); in dhdpcie_bus_doiovar()
6201 bcmerror = dhdpcie_bus_download_state(bus, bool_val); in dhdpcie_bus_doiovar()
6205 int_val = (int32)bus->ramsize; in dhdpcie_bus_doiovar()
6210 bus->ramsize = int_val; in dhdpcie_bus_doiovar()
6211 bus->orig_ramsize = int_val; in dhdpcie_bus_doiovar()
6215 int_val = (int32)bus->dongle_ram_base; in dhdpcie_bus_doiovar()
6224 bcmerror = dhdpcie_cc_nvmshadow(bus, &dump_b); in dhdpcie_bus_doiovar()
6229 bool_val = bus->sleep_allowed; in dhdpcie_bus_doiovar()
6234 bus->sleep_allowed = bool_val; in dhdpcie_bus_doiovar()
6238 int_val = bus->dhd->dongle_isolation; in dhdpcie_bus_doiovar()
6243 bus->dhd->dongle_isolation = bool_val; in dhdpcie_bus_doiovar()
6247 int_val = bus->ltrsleep_on_unload; in dhdpcie_bus_doiovar()
6252 bus->ltrsleep_on_unload = bool_val; in dhdpcie_bus_doiovar()
6259 bcmerror = dhd_prot_ringupd_dump(bus->dhd, &dump_b); in dhdpcie_bus_doiovar()
6264 int_val = dhdpcie_get_dma_ring_indices(bus->dhd); in dhdpcie_bus_doiovar()
6269 bcmerror = dhdpcie_set_dma_ring_indices(bus->dhd, int_val); in dhdpcie_bus_doiovar()
6273 int_val = dhd_prot_metadata_dbg_get(bus->dhd); in dhdpcie_bus_doiovar()
6277 dhd_prot_metadata_dbg_set(bus->dhd, (int_val != 0)); in dhdpcie_bus_doiovar()
6281 int_val = dhd_prot_metadatalen_get(bus->dhd, TRUE); in dhdpcie_bus_doiovar()
6290 dhd_prot_metadatalen_set(bus->dhd, int_val, TRUE); in dhdpcie_bus_doiovar()
6294 dhd_prot_txp_threshold(bus->dhd, TRUE, int_val); in dhdpcie_bus_doiovar()
6298 int_val = dhd_prot_txp_threshold(bus->dhd, FALSE, int_val); in dhdpcie_bus_doiovar()
6304 bus->db1_for_mb = TRUE; in dhdpcie_bus_doiovar()
6306 bus->db1_for_mb = FALSE; in dhdpcie_bus_doiovar()
6310 if (bus->db1_for_mb) in dhdpcie_bus_doiovar()
6318 int_val = dhd_prot_metadatalen_get(bus->dhd, FALSE); in dhdpcie_bus_doiovar()
6327 dhd_prot_metadatalen_set(bus->dhd, int_val, FALSE); in dhdpcie_bus_doiovar()
6333 bcmerror = dhd_bus_devreset(bus->dhd, (uint8)int_val); in dhdpcie_bus_doiovar()
6336 bcmerror = dhd_bus_devreset(bus->dhd, (uint8)int_val); in dhdpcie_bus_doiovar()
6339 bcmerror = dhd_bus_perform_flr(bus, bus->flr_force_fail); in dhdpcie_bus_doiovar()
6342 bus->flr_force_fail = TRUE; in dhdpcie_bus_doiovar()
6350 if (bus->dhd->busstate == DHD_BUS_DATA) in dhdpcie_bus_doiovar()
6351 dhdpcie_fw_trap(bus); in dhdpcie_bus_doiovar()
6353 DHD_ERROR(("%s: Bus is NOT up\n", __FUNCTION__)); in dhdpcie_bus_doiovar()
6358 int_val = bus->dhd->flow_prio_map_type; in dhdpcie_bus_doiovar()
6363 int_val = (int32)dhd_update_flow_prio_map(bus->dhd, (uint8)int_val); in dhdpcie_bus_doiovar()
6369 if (!(bus->dhd->op_mode & DHD_FLAG_MFG_MODE)) { in dhdpcie_bus_doiovar()
6370 int_val = bus->idletime; in dhdpcie_bus_doiovar()
6381 bus->idletime = int_val; in dhdpcie_bus_doiovar()
6382 if (bus->idletime) { in dhdpcie_bus_doiovar()
6383 DHD_ENABLE_RUNTIME_PM(bus->dhd); in dhdpcie_bus_doiovar()
6385 DHD_DISABLE_RUNTIME_PM(bus->dhd); in dhdpcie_bus_doiovar()
6401 dhdpcie_send_mb_data(bus, (uint)int_val); in dhdpcie_bus_doiovar()
6405 dhd_prot_init_info_rings(bus->dhd); in dhdpcie_bus_doiovar()
6409 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6410 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6416 bus->dhd->h2d_phase_supported = TRUE; in dhdpcie_bus_doiovar()
6418 bus->dhd->h2d_phase_supported = FALSE; in dhdpcie_bus_doiovar()
6422 int_val = (int32) bus->dhd->h2d_phase_supported; in dhdpcie_bus_doiovar()
6427 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6428 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6434 bus->dhd->force_dongletrap_on_bad_h2d_phase = TRUE; in dhdpcie_bus_doiovar()
6436 bus->dhd->force_dongletrap_on_bad_h2d_phase = FALSE; in dhdpcie_bus_doiovar()
6440 int_val = (int32) bus->dhd->force_dongletrap_on_bad_h2d_phase; in dhdpcie_bus_doiovar()
6445 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6446 DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", in dhdpcie_bus_doiovar()
6451 dhd_prot_set_h2d_max_txpost(bus->dhd, (uint16)int_val); in dhdpcie_bus_doiovar()
6455 int_val = dhd_prot_get_h2d_max_txpost(bus->dhd); in dhdpcie_bus_doiovar()
6472 bcmerror = dhd_prot_dump_extended_trap(bus->dhd, &dump_b, FALSE); in dhdpcie_bus_doiovar()
6480 bcmerror = dhd_prot_dump_extended_trap(bus->dhd, &dump_b, TRUE); in dhdpcie_bus_doiovar()
6494 clkreq = dhdpcie_clkreq(bus->dhd->osh, 0, 0); in dhdpcie_bus_doiovar()
6495 aspm = dhdpcie_lcreg(bus->dhd->osh, 0, 0); in dhdpcie_bus_doiovar()
6505 tmp = dhdpcie_lcreg(bus->dhd->osh, 0, 0); in dhdpcie_bus_doiovar()
6506 dhdpcie_lcreg(bus->dhd->osh, PCIE_ASPM_ENAB, in dhdpcie_bus_doiovar()
6509 dhdpcie_clkreq(bus->dhd->osh, 1, ((int_val & 0x100) >> 8)); in dhdpcie_bus_doiovar()
6514 bus->dhd->hang_report = bool_val; in dhdpcie_bus_doiovar()
6516 __FUNCTION__, bus->dhd->hang_report)); in dhdpcie_bus_doiovar()
6520 int_val = (int32)bus->dhd->hang_report; in dhdpcie_bus_doiovar()
6525 bcmerror = dhdpcie_cto_init(bus, bool_val); in dhdpcie_bus_doiovar()
6529 if (bus->sih->buscorerev < 19) { in dhdpcie_bus_doiovar()
6533 int_val = (int32)bus->cto_enable; in dhdpcie_bus_doiovar()
6539 if (bus->sih->buscorerev < 19) { in dhdpcie_bus_doiovar()
6543 bus->cto_threshold = (uint32)int_val; in dhdpcie_bus_doiovar()
6548 if (bus->sih->buscorerev < 19) { in dhdpcie_bus_doiovar()
6552 if (bus->cto_threshold) in dhdpcie_bus_doiovar()
6553 int_val = (int32)bus->cto_threshold; in dhdpcie_bus_doiovar()
6563 dhdpcie_cc_watchdog_reset(bus); in dhdpcie_bus_doiovar()
6568 int_val = bus->hwa_enab_bmap; in dhdpcie_bus_doiovar()
6572 bus->hwa_enab_bmap = (uint8)int_val; in dhdpcie_bus_doiovar()
6575 int_val = bus->idma_enabled; in dhdpcie_bus_doiovar()
6579 bus->idma_enabled = (bool)int_val; in dhdpcie_bus_doiovar()
6582 int_val = bus->ifrm_enabled; in dhdpcie_bus_doiovar()
6586 bus->ifrm_enabled = (bool)int_val; in dhdpcie_bus_doiovar()
6590 dhd_flow_rings_flush(bus->dhd, 0); in dhdpcie_bus_doiovar()
6593 int_val = bus->dar_enabled; in dhdpcie_bus_doiovar()
6597 bus->dar_enabled = (bool)int_val; in dhdpcie_bus_doiovar()
6600 bcmerror = dhd_get_hscb_info(bus->dhd, NULL, (uint32 *)arg); in dhdpcie_bus_doiovar()
6604 bcmerror = dhd_get_hscb_buff(bus->dhd, int_val, int_val2, (void*)arg); in dhdpcie_bus_doiovar()
6610 dhd_prot_hp2p_enable(bus->dhd, TRUE, int_val); in dhdpcie_bus_doiovar()
6614 int_val = dhd_prot_hp2p_enable(bus->dhd, FALSE, int_val); in dhdpcie_bus_doiovar()
6619 dhd_prot_pkt_threshold(bus->dhd, TRUE, int_val); in dhdpcie_bus_doiovar()
6623 int_val = dhd_prot_pkt_threshold(bus->dhd, FALSE, int_val); in dhdpcie_bus_doiovar()
6628 dhd_prot_time_threshold(bus->dhd, TRUE, int_val); in dhdpcie_bus_doiovar()
6632 int_val = dhd_prot_time_threshold(bus->dhd, FALSE, int_val); in dhdpcie_bus_doiovar()
6637 dhd_prot_pkt_expiry(bus->dhd, TRUE, int_val); in dhdpcie_bus_doiovar()
6641 int_val = dhd_prot_pkt_expiry(bus->dhd, FALSE, int_val); in dhdpcie_bus_doiovar()
6645 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6648 dhd_bus_set_hp2p_ring_max_size(bus, TRUE, int_val); in dhdpcie_bus_doiovar()
6652 int_val = dhd_bus_get_hp2p_ring_max_size(bus, TRUE); in dhdpcie_bus_doiovar()
6656 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6659 dhd_bus_set_hp2p_ring_max_size(bus, FALSE, int_val); in dhdpcie_bus_doiovar()
6663 int_val = dhd_bus_get_hp2p_ring_max_size(bus, FALSE); in dhdpcie_bus_doiovar()
6668 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6672 bus->dhd->extdtxs_in_txcpl = TRUE; in dhdpcie_bus_doiovar()
6674 bus->dhd->extdtxs_in_txcpl = FALSE; in dhdpcie_bus_doiovar()
6678 int_val = bus->dhd->extdtxs_in_txcpl; in dhdpcie_bus_doiovar()
6683 if (bus->dhd->busstate != DHD_BUS_DOWN) { in dhdpcie_bus_doiovar()
6687 bus->dhd->hostrdy_after_init = TRUE; in dhdpcie_bus_doiovar()
6689 bus->dhd->hostrdy_after_init = FALSE; in dhdpcie_bus_doiovar()
6693 int_val = bus->dhd->hostrdy_after_init; in dhdpcie_bus_doiovar()
6708 dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 len) in dhdpcie_bus_lpback_req() argument
6710 if (bus->dhd == NULL) { in dhdpcie_bus_lpback_req()
6711 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_lpback_req()
6714 if (bus->dhd->prot == NULL) { in dhdpcie_bus_lpback_req()
6718 if (bus->dhd->busstate != DHD_BUS_DATA) { in dhdpcie_bus_lpback_req()
6722 dhdmsgbuf_lpbk_req(bus->dhd, len); in dhdpcie_bus_lpback_req()
6727 dhd_bus_dump_dar_registers(struct dhd_bus *bus) in dhd_bus_dump_dar_registers() argument
6734 if (bus->is_linkdown && !bus->cto_triggered) { in dhd_bus_dump_dar_registers()
6739 dar_clk_ctrl_reg = (uint32)DAR_CLK_CTRL(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6740 dar_pwr_ctrl_reg = (uint32)DAR_PCIE_PWR_CTRL(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6741 dar_intstat_reg = (uint32)DAR_INTSTAT(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6742 dar_errlog_reg = (uint32)DAR_ERRLOG(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6743 dar_erraddr_reg = (uint32)DAR_ERRADDR(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6744 dar_pcie_mbint_reg = (uint32)DAR_PCIMailBoxInt(bus->sih->buscorerev); in dhd_bus_dump_dar_registers()
6746 if (bus->sih->buscorerev < 24) { in dhd_bus_dump_dar_registers()
6748 __FUNCTION__, bus->sih->buscorerev)); in dhd_bus_dump_dar_registers()
6752 dar_clk_ctrl_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_clk_ctrl_reg, 0, 0); in dhd_bus_dump_dar_registers()
6753 dar_pwr_ctrl_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_pwr_ctrl_reg, 0, 0); in dhd_bus_dump_dar_registers()
6754 dar_intstat_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_intstat_reg, 0, 0); in dhd_bus_dump_dar_registers()
6755 dar_errlog_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_errlog_reg, 0, 0); in dhd_bus_dump_dar_registers()
6756 dar_erraddr_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_erraddr_reg, 0, 0); in dhd_bus_dump_dar_registers()
6757 dar_pcie_mbint_val = si_corereg(bus->sih, bus->sih->buscoreidx, dar_pcie_mbint_reg, 0, 0); in dhd_bus_dump_dar_registers()
6770 dhd_bus_hostready(struct dhd_bus *bus) in dhd_bus_hostready() argument
6772 if (!bus->dhd->d2h_hostrdy_supported) { in dhd_bus_hostready()
6776 if (bus->is_linkdown) { in dhd_bus_hostready()
6782 dhd_pcie_config_read(bus->osh, PCI_CFG_CMD, sizeof(uint32)))); in dhd_bus_hostready()
6784 if (DAR_PWRREQ(bus)) { in dhd_bus_hostready()
6785 dhd_bus_pcie_pwr_req(bus); in dhd_bus_hostready()
6788 dhd_bus_dump_dar_registers(bus); in dhd_bus_hostready()
6790 si_corereg(bus->sih, bus->sih->buscoreidx, dhd_bus_db1_addr_get(bus), ~0, 0x12345678); in dhd_bus_hostready()
6791 bus->hostready_count ++; in dhd_bus_hostready()
6792 DHD_ERROR(("%s: Ring Hostready:%d\n", __FUNCTION__, bus->hostready_count)); in dhd_bus_hostready()
6797 dhdpcie_bus_clear_intstatus(struct dhd_bus *bus) in dhdpcie_bus_clear_intstatus() argument
6800 if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) || in dhdpcie_bus_clear_intstatus()
6801 (bus->sih->buscorerev == 2)) { in dhdpcie_bus_clear_intstatus()
6802 intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); in dhdpcie_bus_clear_intstatus()
6803 dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus); in dhdpcie_bus_clear_intstatus()
6806 intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_int, 0, 0); in dhdpcie_bus_clear_intstatus()
6807 si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_int, bus->def_intmask, in dhdpcie_bus_clear_intstatus()
6814 dhdpcie_bus_suspend(struct dhd_bus *bus, bool state, bool byint) in dhdpcie_bus_suspend() argument
6816 dhdpcie_bus_suspend(struct dhd_bus *bus, bool state) in dhdpcie_bus_suspend()
6828 if (bus->dhd == NULL) { in dhdpcie_bus_suspend()
6829 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_suspend()
6832 if (bus->dhd->prot == NULL) { in dhdpcie_bus_suspend()
6837 if (dhd_query_bus_erros(bus->dhd)) { in dhdpcie_bus_suspend()
6841 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6842 if (!(bus->dhd->busstate == DHD_BUS_DATA || bus->dhd->busstate == DHD_BUS_SUSPEND)) { in dhdpcie_bus_suspend()
6844 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6847 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6848 if (bus->dhd->dongle_reset) { in dhdpcie_bus_suspend()
6857 if (state == TRUE && bus->dhd->busstate == DHD_BUS_SUSPEND) { in dhdpcie_bus_suspend()
6858 DHD_ERROR(("Bus is already in SUSPEND state.\n")); in dhdpcie_bus_suspend()
6860 } else if (state == FALSE && bus->dhd->busstate == DHD_BUS_DATA) { in dhdpcie_bus_suspend()
6861 DHD_ERROR(("Bus is already in RESUME state.\n")); in dhdpcie_bus_suspend()
6871 if (bus->is_linkdown) { in dhdpcie_bus_suspend()
6880 bus->dhd->dhd_watchdog_ms_backup = dhd_watchdog_ms; in dhdpcie_bus_suspend()
6881 if (bus->dhd->dhd_watchdog_ms_backup) { in dhdpcie_bus_suspend()
6884 dhd_os_wd_timer(bus->dhd, 0); in dhdpcie_bus_suspend()
6887 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6888 if (DHD_BUS_BUSY_CHECK_IN_TX(bus->dhd)) { in dhdpcie_bus_suspend()
6890 bus->dhd->busstate = DHD_BUS_DATA; in dhdpcie_bus_suspend()
6891 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6895 bus->last_suspend_start_time = OSL_LOCALTIME_NS(); in dhdpcie_bus_suspend()
6898 dhd_bus_stop_queue(bus); in dhdpcie_bus_suspend()
6899 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
6903 DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); in dhdpcie_bus_suspend()
6905 bus->wait_for_d3_ack = 0; in dhdpcie_bus_suspend()
6906 dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM); in dhdpcie_bus_suspend()
6908 timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack); in dhdpcie_bus_suspend()
6909 DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); in dhdpcie_bus_suspend()
6912 bus->wait_for_d3_ack = 0; in dhdpcie_bus_suspend()
6913 dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM | H2D_HOST_ACK_NOINT); in dhdpcie_bus_suspend()
6914 while (!bus->wait_for_d3_ack && d3_read_retry < MAX_D3_ACK_TIMEOUT) { in dhdpcie_bus_suspend()
6915 dhdpcie_handle_mb_data(bus); in dhdpcie_bus_suspend()
6921 DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); in dhdpcie_bus_suspend()
6923 bus->wait_for_d3_ack = 0; in dhdpcie_bus_suspend()
6925 * Send H2D_HOST_D3_INFORM to dongle and mark bus->bus_low_power_state in dhdpcie_bus_suspend()
6930 dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM); in dhdpcie_bus_suspend()
6934 timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack); in dhdpcie_bus_suspend()
6937 if (bus->wait_for_d3_ack == 0) { in dhdpcie_bus_suspend()
6939 uint32 intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_bus_suspend()
6940 bus->pcie_mailbox_int, 0, 0); in dhdpcie_bus_suspend()
6941 int host_irq_disabled = dhdpcie_irq_disabled(bus); in dhdpcie_bus_suspend()
6943 (timeleft == 0) && (!dhd_query_bus_erros(bus->dhd))) { in dhdpcie_bus_suspend()
6947 dhd_pcie_intr_count_dump(bus->dhd); in dhdpcie_bus_suspend()
6948 dhd_print_tasklet_status(bus->dhd); in dhdpcie_bus_suspend()
6949 if (bus->api.fw_rev >= PCIE_SHARED_VERSION_6 && in dhdpcie_bus_suspend()
6950 !bus->use_mailbox) { in dhdpcie_bus_suspend()
6951 dhd_prot_process_ctrlbuf(bus->dhd); in dhdpcie_bus_suspend()
6953 dhdpcie_handle_mb_data(bus); in dhdpcie_bus_suspend()
6955 timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack); in dhdpcie_bus_suspend()
6957 dhdpcie_bus_clear_intstatus(bus); in dhdpcie_bus_suspend()
6959 } /* bus->wait_for_d3_ack was 0 */ in dhdpcie_bus_suspend()
6962 DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); in dhdpcie_bus_suspend()
6968 while ((active = dhd_os_check_wakelock_all(bus->dhd)) && in dhdpcie_bus_suspend()
6975 if (bus->wait_for_d3_ack) { in dhdpcie_bus_suspend()
6977 /* Got D3 Ack. Suspend the bus */ in dhdpcie_bus_suspend()
6983 if (bus->dhd->dhd_watchdog_ms_backup) { in dhdpcie_bus_suspend()
6986 dhd_os_wd_timer(bus->dhd, in dhdpcie_bus_suspend()
6987 bus->dhd->dhd_watchdog_ms_backup); in dhdpcie_bus_suspend()
7002 bus->wait_for_d3_ack = 0; in dhdpcie_bus_suspend()
7004 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7005 bus->bus_low_power_state = DHD_BUS_NO_LOW_POWER_STATE; in dhdpcie_bus_suspend()
7009 bus->resume_intr_enable_count++; in dhdpcie_bus_suspend()
7017 dhdpcie_bus_intr_enable(bus); in dhdpcie_bus_suspend()
7019 dhdpcie_enable_irq(bus); in dhdpcie_bus_suspend()
7021 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7023 if (bus->use_d0_inform) { in dhdpcie_bus_suspend()
7024 DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); in dhdpcie_bus_suspend()
7025 dhdpcie_send_mb_data(bus, in dhdpcie_bus_suspend()
7027 DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); in dhdpcie_bus_suspend()
7030 dhd_bus_hostready(bus); in dhdpcie_bus_suspend()
7032 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7033 bus->dhd->busstate = DHD_BUS_DATA; in dhdpcie_bus_suspend()
7035 dhd_bus_start_queue(bus); in dhdpcie_bus_suspend()
7036 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7041 /* At this time bus->bus_low_power_state will be in dhdpcie_bus_suspend()
7045 if (bus->use_d0_inform && in dhdpcie_bus_suspend()
7046 (bus->api.fw_rev < PCIE_SHARED_VERSION_6)) { in dhdpcie_bus_suspend()
7047 DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); in dhdpcie_bus_suspend()
7048 dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM_IN_USE)); in dhdpcie_bus_suspend()
7049 DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); in dhdpcie_bus_suspend()
7053 if (bus->dhd->dhd_induce_error == DHD_INDUCE_DROP_OOB_IRQ) { in dhdpcie_bus_suspend()
7056 dhdpcie_oob_intr_set(bus, TRUE); in dhdpcie_bus_suspend()
7060 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7067 * between DPC and suspend context and bus->bus_low_power_state in dhdpcie_bus_suspend()
7070 bus->dhd->d3ackcnt_timeout = 0; in dhdpcie_bus_suspend()
7071 bus->dhd->busstate = DHD_BUS_SUSPEND; in dhdpcie_bus_suspend()
7072 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7073 dhdpcie_dump_resource(bus); in dhdpcie_bus_suspend()
7075 rc = dhdpcie_pci_suspend_resume(bus, state); in dhdpcie_bus_suspend()
7077 bus->last_suspend_end_time = OSL_LOCALTIME_NS(); in dhdpcie_bus_suspend()
7084 uint32 cur_memdump_mode = bus->dhd->memdump_enabled; in dhdpcie_bus_suspend()
7088 bus->dhd->is_sched_error = !dhd_query_bus_erros(bus->dhd) && in dhdpcie_bus_suspend()
7089 bus->isr_entry_time > bus->last_d3_inform_time && in dhdpcie_bus_suspend()
7090 dhd_bus_query_dpc_sched_errors(bus->dhd); in dhdpcie_bus_suspend()
7091 bus->dhd->d3ack_timeout_occured = TRUE; in dhdpcie_bus_suspend()
7093 bus->dhd->d3ackcnt_timeout++; in dhdpcie_bus_suspend()
7095 __FUNCTION__, bus->dhd->is_sched_error ? in dhdpcie_bus_suspend()
7096 " due to scheduling problem" : "", bus->dhd->d3ackcnt_timeout)); in dhdpcie_bus_suspend()
7098 if (bus->dhd->is_sched_error && cur_memdump_mode == DUMP_MEMFILE_BUGON) { in dhdpcie_bus_suspend()
7105 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7106 bus->bus_low_power_state = DHD_BUS_NO_LOW_POWER_STATE; in dhdpcie_bus_suspend()
7107 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7108 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7109 bus->dhd->busstate = DHD_BUS_DATA; in dhdpcie_bus_suspend()
7111 dhd_bus_start_queue(bus); in dhdpcie_bus_suspend()
7112 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7113 if (!bus->dhd->dongle_trap_occured && in dhdpcie_bus_suspend()
7114 !bus->is_linkdown && in dhdpcie_bus_suspend()
7115 !bus->cto_triggered) { in dhdpcie_bus_suspend()
7118 /* Check if PCIe bus status is valid */ in dhdpcie_bus_suspend()
7119 intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_bus_suspend()
7120 bus->pcie_mailbox_int, 0, 0); in dhdpcie_bus_suspend()
7122 /* Invalidate PCIe bus status */ in dhdpcie_bus_suspend()
7123 bus->is_linkdown = 1; in dhdpcie_bus_suspend()
7126 dhd_bus_dump_console_buffer(bus); in dhdpcie_bus_suspend()
7127 dhd_prot_debug_info_print(bus->dhd); in dhdpcie_bus_suspend()
7131 bus->dhd->memdump_type = DUMP_TYPE_D3_ACK_TIMEOUT; in dhdpcie_bus_suspend()
7132 dhdpcie_mem_dump(bus); in dhdpcie_bus_suspend()
7141 bus->no_cfg_restore = 1; in dhdpcie_bus_suspend()
7144 dhd_os_check_hang(bus->dhd, 0, -ETIMEDOUT); in dhdpcie_bus_suspend()
7148 dhd_schedule_reset(bus->dhd); in dhdpcie_bus_suspend()
7155 bus->last_resume_start_time = OSL_LOCALTIME_NS(); in dhdpcie_bus_suspend()
7167 si_invalidate_second_bar0win(bus->sih); in dhdpcie_bus_suspend()
7170 DHD_OS_OOB_IRQ_WAKE_UNLOCK(bus->dhd); in dhdpcie_bus_suspend()
7173 rc = dhdpcie_pci_suspend_resume(bus, state); in dhdpcie_bus_suspend()
7174 dhdpcie_dump_resource(bus); in dhdpcie_bus_suspend()
7176 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7178 bus->bus_low_power_state = DHD_BUS_NO_LOW_POWER_STATE; in dhdpcie_bus_suspend()
7179 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_suspend()
7181 if (!rc && bus->dhd->busstate == DHD_BUS_SUSPEND) { in dhdpcie_bus_suspend()
7182 if (bus->use_d0_inform) { in dhdpcie_bus_suspend()
7183 DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); in dhdpcie_bus_suspend()
7184 dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM)); in dhdpcie_bus_suspend()
7185 DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); in dhdpcie_bus_suspend()
7188 dhd_bus_hostready(bus); in dhdpcie_bus_suspend()
7190 DHD_GENERAL_LOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7191 bus->dhd->busstate = DHD_BUS_DATA; in dhdpcie_bus_suspend()
7193 if (DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(bus->dhd)) { in dhdpcie_bus_suspend()
7194 bus->bus_wake = 1; in dhdpcie_bus_suspend()
7196 wake_up_interruptible(&bus->rpm_queue); in dhdpcie_bus_suspend()
7200 dhd_bus_start_queue(bus); in dhdpcie_bus_suspend()
7203 bus->resume_intr_enable_count++; in dhdpcie_bus_suspend()
7209 dhdpcie_bus_intr_enable(bus); /* Enable back interrupt using Intmask!! */ in dhdpcie_bus_suspend()
7210 dhdpcie_enable_irq(bus); /* Enable back interrupt from Host side!! */ in dhdpcie_bus_suspend()
7212 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhdpcie_bus_suspend()
7214 if (bus->dhd->dhd_watchdog_ms_backup) { in dhdpcie_bus_suspend()
7217 dhd_os_wd_timer(bus->dhd, bus->dhd->dhd_watchdog_ms_backup); in dhdpcie_bus_suspend()
7220 bus->last_resume_end_time = OSL_LOCALTIME_NS(); in dhdpcie_bus_suspend()
7222 DHD_EDL_RING_TCM_RD_UPDATE(bus->dhd); in dhdpcie_bus_suspend()
7228 dhdpcie_force_alp(struct dhd_bus *bus, bool enable) in dhdpcie_force_alp() argument
7230 ASSERT(bus && bus->sih); in dhdpcie_force_alp()
7232 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_force_alp()
7235 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_force_alp()
7243 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int l1_entry_time) in dhdpcie_set_l1_entry_time() argument
7247 ASSERT(bus && bus->sih); in dhdpcie_set_l1_entry_time()
7249 si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, in dhdpcie_set_l1_entry_time()
7251 reg_val = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_set_l1_entry_time()
7254 si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0, in dhdpcie_set_l1_entry_time()
7261 dhd_apply_d11_war_length(struct dhd_bus *bus, uint32 len, uint32 d11_lpbk) in dhd_apply_d11_war_length() argument
7263 uint16 chipid = si_chipid(bus->sih); in dhd_apply_d11_war_length()
7277 dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus, in dhdpcie_bus_dmaxfer_req() argument
7283 if (bus->dhd == NULL) { in dhdpcie_bus_dmaxfer_req()
7284 DHD_ERROR(("bus not inited\n")); in dhdpcie_bus_dmaxfer_req()
7287 if (bus->dhd->prot == NULL) { in dhdpcie_bus_dmaxfer_req()
7291 if (bus->dhd->busstate != DHD_BUS_DATA) { in dhdpcie_bus_dmaxfer_req()
7301 len = dhd_apply_d11_war_length(bus, len, d11_lpbk); in dhdpcie_bus_dmaxfer_req()
7303 bus->dmaxfer_complete = FALSE; in dhdpcie_bus_dmaxfer_req()
7304 ret = dhdmsgbuf_dmaxfer_req(bus->dhd, len, srcdelay, destdelay, in dhdpcie_bus_dmaxfer_req()
7310 ret = dhd_os_dmaxfer_wait(bus->dhd, &bus->dmaxfer_complete); in dhdpcie_bus_dmaxfer_req()
7320 dhd_bus_is_multibp_capable(struct dhd_bus *bus) in dhd_bus_is_multibp_capable() argument
7322 return MULTIBP_CAP(bus->sih); in dhd_bus_is_multibp_capable()
7329 dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter) in dhdpcie_bus_download_state() argument
7336 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7338 bcmerror = dhdpcie_dongle_host_get_handshake_address(bus->sih, bus->osh, in dhdpcie_bus_download_state()
7346 if (!bus->sih) { in dhdpcie_bus_download_state()
7351 do_flr = ((bus->sih->buscorerev != PCIE_REV_FOR_4378A0) && in dhdpcie_bus_download_state()
7352 (bus->sih->buscorerev != PCIE_REV_FOR_4378B0)); in dhdpcie_bus_download_state()
7354 if (MULTIBP_ENAB(bus->sih) && !do_flr) { in dhdpcie_bus_download_state()
7355 dhd_bus_pcie_pwr_req(bus); in dhdpcie_bus_download_state()
7366 dhdpcie_setbar1win(bus, 0x00000000); in dhdpcie_bus_download_state()
7367 bus->alp_only = TRUE; in dhdpcie_bus_download_state()
7370 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_download_state()
7372 if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && in dhdpcie_bus_download_state()
7373 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) && in dhdpcie_bus_download_state()
7374 !(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7380 if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { in dhdpcie_bus_download_state()
7382 si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT); in dhdpcie_bus_download_state()
7383 if (!(si_setcore(bus->sih, SYSMEM_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7388 si_core_reset(bus->sih, 0, 0); in dhdpcie_bus_download_state()
7390 dhdpcie_init_shared_addr(bus); in dhdpcie_bus_download_state()
7392 si_core_disable(bus->sih, 0); in dhdpcie_bus_download_state()
7394 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7400 si_core_reset(bus->sih, 0, 0); in dhdpcie_bus_download_state()
7403 if (bus->ramsize) { in dhdpcie_bus_download_state()
7405 if (dhdpcie_bus_membytes(bus, TRUE, bus->ramsize - 4, in dhdpcie_bus_download_state()
7421 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7426 if ((bcmerror = dhdpcie_dongle_host_pre_handshake(bus->sih, in dhdpcie_bus_download_state()
7427 bus->osh, &bl_hs_addrs))) { in dhdpcie_bus_download_state()
7437 if ((bcmerror = dhdpcie_readshared_console(bus)) < 0) { in dhdpcie_bus_download_state()
7443 if ((bcmerror = dhdpcie_bus_readconsole(bus)) < 0) { in dhdpcie_bus_download_state()
7449 si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT); in dhdpcie_bus_download_state()
7450 if (BCM43602_CHIP(bus->sih->chip)) { in dhdpcie_bus_download_state()
7451 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, in dhdpcie_bus_download_state()
7453 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, in dhdpcie_bus_download_state()
7455 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, in dhdpcie_bus_download_state()
7457 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, in dhdpcie_bus_download_state()
7461 dhdpcie_init_shared_addr(bus); in dhdpcie_bus_download_state()
7465 if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { in dhdpcie_bus_download_state()
7467 if ((bcmerror = dhdpcie_bus_write_vars(bus))) { in dhdpcie_bus_download_state()
7474 if ((bcmerror = dhdpcie_wrt_rnd(bus)) != BCME_OK) { in dhdpcie_bus_download_state()
7480 if (!(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7486 bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0, in dhdpcie_bus_download_state()
7487 (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr)); in dhdpcie_bus_download_state()
7489 } else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { in dhdpcie_bus_download_state()
7490 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7496 if (!si_iscoreup(bus->sih)) { in dhdpcie_bus_download_state()
7505 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) && in dhdpcie_bus_download_state()
7506 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) { in dhdpcie_bus_download_state()
7512 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && in dhdpcie_bus_download_state()
7513 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7519 if (BCM43602_CHIP(bus->sih->chip)) { in dhdpcie_bus_download_state()
7521 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7527 si_core_reset(bus->sih, 0, 0); in dhdpcie_bus_download_state()
7528 si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_download_state()
7531 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7533 if ((bcmerror = dhdpcie_bus_readconsole(bus)) < 0) { in dhdpcie_bus_download_state()
7539 if ((bcmerror = dhdpcie_dongle_host_post_handshake(bus->sih, in dhdpcie_bus_download_state()
7540 bus->osh, &bl_hs_addrs))) { in dhdpcie_bus_download_state()
7556 if ((bcmerror = dhdpcie_dongle_host_chk_validation(bus->sih, in dhdpcie_bus_download_state()
7557 bus->osh, &bl_hs_addrs))) { in dhdpcie_bus_download_state()
7565 if ((bcmerror = dhdpcie_bus_write_vars(bus))) { in dhdpcie_bus_download_state()
7573 if ((bcmerror = dhdpcie_wrt_rnd(bus)) != BCME_OK) { in dhdpcie_bus_download_state()
7580 if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) { in dhdpcie_bus_download_state()
7587 if (bus->sih->chip != CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7588 bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0, in dhdpcie_bus_download_state()
7589 (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr)); in dhdpcie_bus_download_state()
7594 bcmerror = dhdpcie_bus_membytes(bus, FALSE, 0, in dhdpcie_bus_download_state()
7597 if (bcmerror == BCME_OK && tmp != bus->resetinstr) { in dhdpcie_bus_download_state()
7599 __FUNCTION__, bus->resetinstr)); in dhdpcie_bus_download_state()
7611 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7613 if ((bcmerror = dhdpcie_bus_readconsole(bus)) < 0) { in dhdpcie_bus_download_state()
7619 if ((bcmerror = dhdpcie_dongle_host_post_varswrite(bus, &bl_hs_addrs))) { in dhdpcie_bus_download_state()
7627 si_core_reset(bus->sih, 0, 0); in dhdpcie_bus_download_state()
7630 bus->alp_only = FALSE; in dhdpcie_bus_download_state()
7632 bus->dhd->busstate = DHD_BUS_LOAD; in dhdpcie_bus_download_state()
7638 if (bus->sih->chip == CYW55560_CHIP_ID) { in dhdpcie_bus_download_state()
7640 if (dhdpcie_readshared_console(bus) < 0) { in dhdpcie_bus_download_state()
7645 if (dhdpcie_bus_readconsole(bus) < 0) { in dhdpcie_bus_download_state()
7654 si_setcore(bus->sih, PCIE2_CORE_ID, 0); in dhdpcie_bus_download_state()
7656 if (MULTIBP_ENAB(bus->sih) && !do_flr) { in dhdpcie_bus_download_state()
7657 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_bus_download_state()
7954 dhdpcie_dongle_host_post_varswrite(dhd_bus_t *bus, hs_addrs_t *addr) in dhdpcie_dongle_host_post_varswrite() argument
7962 bcmerror = dhdpcie_handshake_msg_reg_write(bus->sih, bus->osh, addr->h2d, &h2d_reg); in dhdpcie_dongle_host_post_varswrite()
7968 dhdpcie_bus_write_vars(dhd_bus_t *bus) in dhdpcie_bus_write_vars() argument
7980 varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0; in dhdpcie_bus_write_vars()
7981 varaddr = (bus->ramsize - 4) - varsize; in dhdpcie_bus_write_vars()
7983 varaddr += bus->dongle_ram_base; in dhdpcie_bus_write_vars()
7985 if (bus->vars) { in dhdpcie_bus_write_vars()
7987 vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize); in dhdpcie_bus_write_vars()
7992 bcopy(bus->vars, vbuffer, bus->varsz); in dhdpcie_bus_write_vars()
7994 bcmerror = dhdpcie_bus_membytes(bus, TRUE, varaddr, vbuffer, varsize); in dhdpcie_bus_write_vars()
8000 nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize); in dhdpcie_bus_write_vars()
8002 MFREE(bus->dhd->osh, vbuffer, varsize); in dhdpcie_bus_write_vars()
8010 bcmerror = dhdpcie_bus_membytes(bus, FALSE, varaddr, nvram_ularray, varsize); in dhdpcie_bus_write_vars()
8023 MFREE(bus->dhd->osh, nvram_ularray, varsize); in dhdpcie_bus_write_vars()
8026 MFREE(bus->dhd->osh, vbuffer, varsize); in dhdpcie_bus_write_vars()
8029 phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize; in dhdpcie_bus_write_vars()
8031 phys_size += bus->dongle_ram_base; in dhdpcie_bus_write_vars()
8035 phys_size, bus->ramsize)); in dhdpcie_bus_write_vars()
8046 bus->nvram_csm = varsizew; in dhdpcie_bus_write_vars()
8050 bus->nvram_csm = varsizew; in dhdpcie_bus_write_vars()
8057 bcmerror = dhdpcie_bus_membytes(bus, TRUE, (phys_size - 4), in dhdpcie_bus_write_vars()
8064 dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len) in dhdpcie_downloadvars() argument
8071 if (bus->dhd->up) { in dhdpcie_downloadvars()
8081 if (bus->vars) in dhdpcie_downloadvars()
8082 MFREE(bus->dhd->osh, bus->vars, bus->varsz); in dhdpcie_downloadvars()
8084 bus->vars = MALLOC(bus->dhd->osh, len); in dhdpcie_downloadvars()
8085 bus->varsz = bus->vars ? len : 0; in dhdpcie_downloadvars()
8086 if (bus->vars == NULL) { in dhdpcie_downloadvars()
8092 bcopy(arg, bus->vars, bus->varsz); in dhdpcie_downloadvars()
8095 if (dhd_bus_get_fw_mode(bus->dhd) == DHD_FLAG_MFG_MODE) { in dhdpcie_downloadvars()
8103 sp = strnstr(bus->vars, tag[i], bus->varsz); in dhdpcie_downloadvars()
8106 __FUNCTION__, bus->nv_path)); in dhdpcie_downloadvars()
8291 dhd_bus_t *bus; in dhd_dump_intr_counters() local
8299 bus = dhd->bus; in dhd_dump_intr_counters()
8300 if (!bus) { in dhd_dump_intr_counters()
8301 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__)); in dhd_dump_intr_counters()
8309 bus->resume_intr_enable_count, bus->dpc_intr_enable_count, in dhd_dump_intr_counters()
8310 bus->isr_intr_disable_count, bus->suspend_intr_disable_count, in dhd_dump_intr_counters()
8311 bus->dpc_return_busdown_count, bus->non_ours_irq_count); in dhd_dump_intr_counters()
8317 bus->oob_intr_count, bus->oob_intr_enable_count, in dhd_dump_intr_counters()
8318 bus->oob_intr_disable_count, dhdpcie_get_oob_irq_num(bus), in dhd_dump_intr_counters()
8319 GET_SEC_USEC(bus->last_oob_irq_time), GET_SEC_USEC(bus->last_oob_irq_enable_time), in dhd_dump_intr_counters()
8320 GET_SEC_USEC(bus->last_oob_irq_disable_time), dhdpcie_get_oob_irq_status(bus), in dhd_dump_intr_counters()
8331 GET_SEC_USEC(current_time), GET_SEC_USEC(bus->isr_entry_time), in dhd_dump_intr_counters()
8332 GET_SEC_USEC(bus->isr_exit_time), GET_SEC_USEC(bus->dpc_sched_time), in dhd_dump_intr_counters()
8333 GET_SEC_USEC(bus->last_non_ours_irq_time), GET_SEC_USEC(bus->dpc_entry_time), in dhd_dump_intr_counters()
8334 GET_SEC_USEC(bus->last_process_ctrlbuf_time), in dhd_dump_intr_counters()
8335 GET_SEC_USEC(bus->last_process_flowring_time), in dhd_dump_intr_counters()
8336 GET_SEC_USEC(bus->last_process_txcpl_time), in dhd_dump_intr_counters()
8337 GET_SEC_USEC(bus->last_process_rxcpl_time), in dhd_dump_intr_counters()
8338 GET_SEC_USEC(bus->last_process_infocpl_time), in dhd_dump_intr_counters()
8339 GET_SEC_USEC(bus->last_process_edl_time), in dhd_dump_intr_counters()
8340 GET_SEC_USEC(bus->dpc_exit_time), GET_SEC_USEC(bus->resched_dpc_time), in dhd_dump_intr_counters()
8341 GET_SEC_USEC(bus->last_d3_inform_time)); in dhd_dump_intr_counters()
8345 SEC_USEC_FMT"\n", GET_SEC_USEC(bus->last_suspend_start_time), in dhd_dump_intr_counters()
8346 GET_SEC_USEC(bus->last_suspend_end_time), in dhd_dump_intr_counters()
8347 GET_SEC_USEC(bus->last_resume_start_time), in dhd_dump_intr_counters()
8348 GET_SEC_USEC(bus->last_resume_end_time)); in dhd_dump_intr_counters()
8371 intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_dump_intr_registers()
8372 dhd->bus->pcie_mailbox_int, 0, 0); in dhd_dump_intr_registers()
8373 intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_dump_intr_registers()
8374 dhd->bus->pcie_mailbox_mask, 0, 0); in dhd_dump_intr_registers()
8375 d2h_db0 = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCID2H_MailBox, 0, 0); in dhd_dump_intr_registers()
8376 dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0); in dhd_dump_intr_registers()
8381 d2h_mb_data, dhd->bus->def_intmask); in dhd_dump_intr_registers()
8383 /** Add bus dump output to a buffer */
8404 bcmpcie_get_total_wake(dhdp->bus), dhdp->bus->wake_counts.rxwake, in dhd_bus_dump()
8405 dhdp->bus->wake_counts.rcwake); in dhd_bus_dump()
8408 dhdp->bus->wake_counts.rx_ucast, dhdp->bus->wake_counts.rx_mcast, in dhd_bus_dump()
8409 dhdp->bus->wake_counts.rx_bcast, dhdp->bus->wake_counts.rx_arp); in dhd_bus_dump()
8411 dhdp->bus->wake_counts.rx_multi_ipv4, dhdp->bus->wake_counts.rx_multi_ipv6, in dhd_bus_dump()
8412 dhdp->bus->wake_counts.rx_icmpv6, dhdp->bus->wake_counts.rx_multi_other); in dhd_bus_dump()
8414 dhdp->bus->wake_counts.rx_icmpv6_ra, dhdp->bus->wake_counts.rx_icmpv6_na, in dhd_bus_dump()
8415 dhdp->bus->wake_counts.rx_icmpv6_ns); in dhd_bus_dump()
8419 if (dhdp->bus->wake_counts.rc_event[flowid] != 0) in dhd_bus_dump()
8421 dhdp->bus->wake_counts.rc_event[flowid]); in dhd_bus_dump()
8430 dhdp->bus->h2d_mb_data_ptr_addr, dhdp->bus->d2h_mb_data_ptr_addr); in dhd_bus_dump()
8541 bcm_bprintf(strbuf, "D3 inform cnt %d\n", dhdp->bus->d3_inform_cnt); in dhd_bus_dump()
8542 bcm_bprintf(strbuf, "D0 inform cnt %d\n", dhdp->bus->d0_inform_cnt); in dhd_bus_dump()
8543 bcm_bprintf(strbuf, "D0 inform in use cnt %d\n", dhdp->bus->d0_inform_in_use_cnt); in dhd_bus_dump()
8545 bcm_bprintf(strbuf, "hostready count:%d\n", dhdp->bus->hostready_count); in dhd_bus_dump()
8548 dhdp->bus->d2h_intr_method ? "PCIE_MSI" : "PCIE_INTX"); in dhd_bus_dump()
8555 uint32 axi_tcm_addr = dhdpcie_bus_rtcm32(dhdp->bus, dhdp->axierror_logbuf_addr); in dhd_axi_sig_match()
8563 __FUNCTION__, axi_tcm_addr, dhdp->bus->dongle_ram_base, in dhd_axi_sig_match()
8564 dhdp->bus->dongle_ram_base + dhdp->bus->ramsize)); in dhd_axi_sig_match()
8565 if (axi_tcm_addr >= dhdp->bus->dongle_ram_base && in dhd_axi_sig_match()
8566 axi_tcm_addr < dhdp->bus->dongle_ram_base + dhdp->bus->ramsize) { in dhd_axi_sig_match()
8567 uint32 axi_signature = dhdpcie_bus_rtcm32(dhdp->bus, (axi_tcm_addr + in dhd_axi_sig_match()
8611 axi_tcm_addr = dhdpcie_bus_rtcm32(dhdp->bus, axi_logbuf_addr); in dhd_axi_error()
8620 err = dhdpcie_bus_membytes(dhdp->bus, FALSE, axi_tcm_addr, p_axi_err, size); in dhd_axi_error()
8713 struct dhd_bus *bus = dhd->bus; in dhd_update_txflowrings() local
8720 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_update_txflowrings()
8721 for (item = dll_head_p(&bus->flowring_active_list); in dhd_update_txflowrings()
8722 (!dhd_is_device_removed(dhd) && !dll_end(&bus->flowring_active_list, item)); in dhd_update_txflowrings()
8739 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_update_txflowrings()
8744 dhd_bus_gen_devmb_intr(struct dhd_bus *bus) in dhd_bus_gen_devmb_intr() argument
8746 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhd_bus_gen_devmb_intr()
8747 (bus->sih->buscorerev == 4)) { in dhd_bus_gen_devmb_intr()
8751 if (bus->db1_for_mb) { in dhd_bus_gen_devmb_intr()
8754 if (DAR_PWRREQ(bus)) { in dhd_bus_gen_devmb_intr()
8755 dhd_bus_pcie_pwr_req(bus); in dhd_bus_gen_devmb_intr()
8757 si_corereg(bus->sih, bus->sih->buscoreidx, dhd_bus_db1_addr_get(bus), in dhd_bus_gen_devmb_intr()
8761 dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0)); in dhd_bus_gen_devmb_intr()
8762 dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0)); in dhd_bus_gen_devmb_intr()
8771 dhdpcie_fw_trap(dhd_bus_t *bus) in dhdpcie_fw_trap() argument
8774 dhdpcie_send_mb_data(bus, H2D_FW_TRAP); in dhdpcie_fw_trap()
8776 (void)dhd_wl_ioctl_set_intiovar(bus->dhd, "bus:disconnect", 99, WLC_SET_VAR, TRUE, 0); in dhdpcie_fw_trap()
8781 dhd_bus_ringbell(struct dhd_bus *bus, uint32 value) in dhd_bus_ringbell() argument
8784 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhd_bus_ringbell()
8786 __FUNCTION__, bus->bus_low_power_state)); in dhd_bus_ringbell()
8791 if (bus->is_linkdown) { in dhd_bus_ringbell()
8796 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhd_bus_ringbell()
8797 (bus->sih->buscorerev == 4)) { in dhd_bus_ringbell()
8798 si_corereg(bus->sih, bus->sih->buscoreidx, bus->pcie_mailbox_int, in dhd_bus_ringbell()
8803 if (IDMA_ACTIVE(bus->dhd)) { in dhd_bus_ringbell()
8804 if (DAR_PWRREQ(bus)) { in dhd_bus_ringbell()
8805 dhd_bus_pcie_pwr_req(bus); in dhd_bus_ringbell()
8807 si_corereg(bus->sih, bus->sih->buscoreidx, dhd_bus_db0_addr_2_get(bus), in dhd_bus_ringbell()
8810 if (DAR_PWRREQ(bus)) { in dhd_bus_ringbell()
8811 dhd_bus_pcie_pwr_req(bus); in dhd_bus_ringbell()
8813 si_corereg(bus->sih, bus->sih->buscoreidx, in dhd_bus_ringbell()
8814 dhd_bus_db0_addr_get(bus), ~0, 0x12345678); in dhd_bus_ringbell()
8821 dhd_bus_ringbell_2(struct dhd_bus *bus, uint32 value, bool devwake) in dhd_bus_ringbell_2() argument
8825 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhd_bus_ringbell_2()
8827 __FUNCTION__, bus->bus_low_power_state)); in dhd_bus_ringbell_2()
8832 if (bus->is_linkdown) { in dhd_bus_ringbell_2()
8838 if (DAR_PWRREQ(bus)) { in dhd_bus_ringbell_2()
8839 dhd_bus_pcie_pwr_req(bus); in dhd_bus_ringbell_2()
8841 si_corereg(bus->sih, bus->sih->buscoreidx, dhd_bus_db0_addr_2_get(bus), in dhd_bus_ringbell_2()
8846 dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value) in dhdpcie_bus_ringbell_fast() argument
8849 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhdpcie_bus_ringbell_fast()
8851 __FUNCTION__, bus->bus_low_power_state)); in dhdpcie_bus_ringbell_fast()
8856 if (bus->is_linkdown) { in dhdpcie_bus_ringbell_fast()
8861 if (DAR_PWRREQ(bus)) { in dhdpcie_bus_ringbell_fast()
8862 dhd_bus_pcie_pwr_req(bus); in dhdpcie_bus_ringbell_fast()
8866 if (bus->dhd->db0ts_capable) { in dhdpcie_bus_ringbell_fast()
8876 W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, value); in dhdpcie_bus_ringbell_fast()
8880 dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake) in dhdpcie_bus_ringbell_2_fast() argument
8883 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhdpcie_bus_ringbell_2_fast()
8885 __FUNCTION__, bus->bus_low_power_state)); in dhdpcie_bus_ringbell_2_fast()
8890 if (bus->is_linkdown) { in dhdpcie_bus_ringbell_2_fast()
8895 if (DAR_PWRREQ(bus)) { in dhdpcie_bus_ringbell_2_fast()
8896 dhd_bus_pcie_pwr_req(bus); in dhdpcie_bus_ringbell_2_fast()
8898 W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_2_addr, value); in dhdpcie_bus_ringbell_2_fast()
8902 dhd_bus_ringbell_oldpcie(struct dhd_bus *bus, uint32 value) in dhd_bus_ringbell_oldpcie() argument
8906 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhd_bus_ringbell_oldpcie()
8908 __FUNCTION__, bus->bus_low_power_state)); in dhd_bus_ringbell_oldpcie()
8913 if (bus->is_linkdown) { in dhd_bus_ringbell_oldpcie()
8918 w = (R_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr) & ~PCIE_INTB) | PCIE_INTB; in dhd_bus_ringbell_oldpcie()
8919 W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, w); in dhd_bus_ringbell_oldpcie()
8923 dhd_bus_get_mbintr_fn(struct dhd_bus *bus) in dhd_bus_get_mbintr_fn() argument
8925 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhd_bus_get_mbintr_fn()
8926 (bus->sih->buscorerev == 4)) { in dhd_bus_get_mbintr_fn()
8927 bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx, in dhd_bus_get_mbintr_fn()
8928 bus->pcie_mailbox_int); in dhd_bus_get_mbintr_fn()
8929 if (bus->pcie_mb_intr_addr) { in dhd_bus_get_mbintr_fn()
8930 bus->pcie_mb_intr_osh = si_osh(bus->sih); in dhd_bus_get_mbintr_fn()
8934 bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx, in dhd_bus_get_mbintr_fn()
8935 dhd_bus_db0_addr_get(bus)); in dhd_bus_get_mbintr_fn()
8936 if (bus->pcie_mb_intr_addr) { in dhd_bus_get_mbintr_fn()
8937 bus->pcie_mb_intr_osh = si_osh(bus->sih); in dhd_bus_get_mbintr_fn()
8945 dhd_bus_get_mbintr_2_fn(struct dhd_bus *bus) in dhd_bus_get_mbintr_2_fn() argument
8947 bus->pcie_mb_intr_2_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx, in dhd_bus_get_mbintr_2_fn()
8948 dhd_bus_db0_addr_2_get(bus)); in dhd_bus_get_mbintr_2_fn()
8949 if (bus->pcie_mb_intr_2_addr) { in dhd_bus_get_mbintr_2_fn()
8950 bus->pcie_mb_intr_osh = si_osh(bus->sih); in dhd_bus_get_mbintr_2_fn()
8957 dhd_bus_dpc(struct dhd_bus *bus) in dhd_bus_dpc() argument
8964 bus->dpc_entry_time = OSL_LOCALTIME_NS(); in dhd_bus_dpc()
8966 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_dpc()
8972 if (bus->dhd->busstate == DHD_BUS_DOWN) { in dhd_bus_dpc()
8973 DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__)); in dhd_bus_dpc()
8974 bus->intstatus = 0; in dhd_bus_dpc()
8975 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_dpc()
8976 bus->dpc_return_busdown_count++; in dhd_bus_dpc()
8980 bus->idlecount = 0; in dhd_bus_dpc()
8982 DHD_BUS_BUSY_SET_IN_DPC(bus->dhd); in dhd_bus_dpc()
8983 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_dpc()
8985 resched = dhdpcie_bus_process_mailbox_intr(bus, bus->intstatus); in dhd_bus_dpc()
8987 bus->intstatus = 0; in dhd_bus_dpc()
8988 bus->dpc_intr_enable_count++; in dhd_bus_dpc()
8992 dhdpcie_bus_intr_enable(bus); in dhd_bus_dpc()
8993 dhdpcie_enable_irq(bus); /* Enable back interrupt!! */ in dhd_bus_dpc()
8994 bus->dpc_exit_time = OSL_LOCALTIME_NS(); in dhd_bus_dpc()
8996 bus->resched_dpc_time = OSL_LOCALTIME_NS(); in dhd_bus_dpc()
8999 bus->dpc_sched = resched; in dhd_bus_dpc()
9001 DHD_GENERAL_LOCK(bus->dhd, flags); in dhd_bus_dpc()
9002 DHD_BUS_BUSY_CLEAR_IN_DPC(bus->dhd); in dhd_bus_dpc()
9003 dhd_os_busbusy_wake(bus->dhd); in dhd_bus_dpc()
9004 DHD_GENERAL_UNLOCK(bus->dhd, flags); in dhd_bus_dpc()
9011 dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data) in dhdpcie_send_mb_data() argument
9017 if (bus->is_linkdown) { in dhdpcie_send_mb_data()
9022 if (bus->api.fw_rev >= PCIE_SHARED_VERSION_6 && !bus->use_mailbox) { in dhdpcie_send_mb_data()
9027 if (dhd_prot_h2d_mbdata_send_ctrlmsg(bus->dhd, h2d_mb_data)) { in dhdpcie_send_mb_data()
9036 dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0); in dhdpcie_send_mb_data()
9043 dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0); in dhdpcie_send_mb_data()
9053 dhd_bus_cmn_writeshared(bus, &h2d_mb_data, sizeof(uint32), H2D_MB_DATA, 0); in dhdpcie_send_mb_data()
9054 dhd_bus_gen_devmb_intr(bus); in dhdpcie_send_mb_data()
9059 bus->last_d3_inform_time = OSL_LOCALTIME_NS(); in dhdpcie_send_mb_data()
9060 bus->d3_inform_cnt++; in dhdpcie_send_mb_data()
9064 bus->d0_inform_in_use_cnt++; in dhdpcie_send_mb_data()
9068 bus->d0_inform_cnt++; in dhdpcie_send_mb_data()
9076 dhd_bus_handle_d3_ack(dhd_bus_t *bus) in dhd_bus_handle_d3_ack() argument
9079 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhd_bus_handle_d3_ack()
9080 bus->suspend_intr_disable_count++; in dhd_bus_handle_d3_ack()
9088 dhdpcie_bus_intr_disable(bus); /* Disable interrupt using IntMask!! */ in dhd_bus_handle_d3_ack()
9089 dhdpcie_bus_clear_intstatus(bus); in dhd_bus_handle_d3_ack()
9090 dhdpcie_disable_irq_nosync(bus); /* Disable host interrupt!! */ in dhd_bus_handle_d3_ack()
9092 if (bus->dhd->dhd_induce_error != DHD_INDUCE_D3_ACK_TIMEOUT) { in dhd_bus_handle_d3_ack()
9094 bus->bus_low_power_state = DHD_BUS_D3_ACK_RECIEVED; in dhd_bus_handle_d3_ack()
9097 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhd_bus_handle_d3_ack()
9101 if (bus->dhd->dhd_induce_error != DHD_INDUCE_D3_ACK_TIMEOUT) { in dhd_bus_handle_d3_ack()
9102 bus->wait_for_d3_ack = 1; in dhd_bus_handle_d3_ack()
9103 dhd_os_d3ack_wake(bus->dhd); in dhd_bus_handle_d3_ack()
9109 dhd_bus_handle_mb_data(dhd_bus_t *bus, uint32 d2h_mb_data) in dhd_bus_handle_mb_data() argument
9111 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_handle_mb_data()
9112 dhd_bus_pcie_pwr_req(bus); in dhd_bus_handle_mb_data()
9119 dhdpcie_checkdied(bus, NULL, 0); in dhd_bus_handle_mb_data()
9123 bus->no_cfg_restore = 1; in dhd_bus_handle_mb_data()
9126 dhd_os_check_hang(bus->dhd, 0, -EREMOTEIO); in dhd_bus_handle_mb_data()
9133 if (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED) { in dhd_bus_handle_mb_data()
9136 bus->dhd->busstate = DHD_BUS_DOWN; in dhd_bus_handle_mb_data()
9142 dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK); in dhd_bus_handle_mb_data()
9157 if (!bus->wait_for_d3_ack) { in dhd_bus_handle_mb_data()
9159 if (bus->dhd->req_hang_type == HANG_REASON_D3_ACK_TIMEOUT) { in dhd_bus_handle_mb_data()
9162 dhd_bus_handle_d3_ack(bus); in dhd_bus_handle_mb_data()
9165 dhd_bus_handle_d3_ack(bus); in dhd_bus_handle_mb_data()
9171 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_handle_mb_data()
9172 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_handle_mb_data()
9177 dhdpcie_handle_mb_data(dhd_bus_t *bus) in dhdpcie_handle_mb_data() argument
9182 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_handle_mb_data()
9183 dhd_bus_pcie_pwr_req(bus); in dhdpcie_handle_mb_data()
9186 dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0); in dhdpcie_handle_mb_data()
9193 dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0); in dhdpcie_handle_mb_data()
9198 dhdpcie_checkdied(bus, NULL, 0); in dhdpcie_handle_mb_data()
9199 /* not ready yet dhd_os_ind_firmware_stall(bus->dhd); */ in dhdpcie_handle_mb_data()
9205 dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK); in dhdpcie_handle_mb_data()
9215 if (!bus->wait_for_d3_ack) { in dhdpcie_handle_mb_data()
9217 if (bus->dhd->req_hang_type == HANG_REASON_D3_ACK_TIMEOUT) { in dhdpcie_handle_mb_data()
9220 dhd_bus_handle_d3_ack(bus); in dhdpcie_handle_mb_data()
9223 dhd_bus_handle_d3_ack(bus); in dhdpcie_handle_mb_data()
9229 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_handle_mb_data()
9230 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_handle_mb_data()
9235 dhdpcie_read_handle_mb_data(dhd_bus_t *bus) in dhdpcie_read_handle_mb_data() argument
9240 if (bus->is_linkdown) { in dhdpcie_read_handle_mb_data()
9245 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_read_handle_mb_data()
9246 dhd_bus_pcie_pwr_req(bus); in dhdpcie_read_handle_mb_data()
9249 dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0); in dhdpcie_read_handle_mb_data()
9254 dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0); in dhdpcie_read_handle_mb_data()
9256 dhd_bus_handle_mb_data(bus, d2h_mb_data); in dhdpcie_read_handle_mb_data()
9259 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_read_handle_mb_data()
9260 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_read_handle_mb_data()
9265 dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus) in dhdpcie_bus_process_mailbox_intr() argument
9270 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_bus_process_mailbox_intr()
9271 dhd_bus_pcie_pwr_req(bus); in dhdpcie_bus_process_mailbox_intr()
9273 if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || in dhdpcie_bus_process_mailbox_intr()
9274 (bus->sih->buscorerev == 4)) { in dhdpcie_bus_process_mailbox_intr()
9277 resched = dhdpci_bus_read_frames(bus); in dhdpcie_bus_process_mailbox_intr()
9283 bus->api.handle_mb_data(bus); in dhdpcie_bus_process_mailbox_intr()
9286 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_process_mailbox_intr()
9287 if (bus->bus_low_power_state == DHD_BUS_D3_ACK_RECIEVED) { in dhdpcie_bus_process_mailbox_intr()
9290 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_process_mailbox_intr()
9293 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpcie_bus_process_mailbox_intr()
9296 if ((bus->d2h_intr_method == PCIE_MSI) || in dhdpcie_bus_process_mailbox_intr()
9297 ((bus->d2h_intr_method == PCIE_INTX) && (intstatus & bus->d2h_mb_mask))) { in dhdpcie_bus_process_mailbox_intr()
9299 if (pm_runtime_get(dhd_bus_to_dev(bus)) >= 0) { in dhdpcie_bus_process_mailbox_intr()
9300 resched = dhdpci_bus_read_frames(bus); in dhdpcie_bus_process_mailbox_intr()
9301 pm_runtime_mark_last_busy(dhd_bus_to_dev(bus)); in dhdpcie_bus_process_mailbox_intr()
9302 pm_runtime_put_autosuspend(dhd_bus_to_dev(bus)); in dhdpcie_bus_process_mailbox_intr()
9305 resched = dhdpci_bus_read_frames(bus); in dhdpcie_bus_process_mailbox_intr()
9311 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_bus_process_mailbox_intr()
9312 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_bus_process_mailbox_intr()
9319 dhdpci_bus_rte_log_time_sync_poll(dhd_bus_t *bus) in dhdpci_bus_rte_log_time_sync_poll() argument
9324 if ((bus->dhd->busstate == DHD_BUS_DATA) && in dhdpci_bus_rte_log_time_sync_poll()
9325 (bus->dhd->dhd_rte_time_sync_ms != 0) && in dhdpci_bus_rte_log_time_sync_poll()
9326 (bus->bus_low_power_state == DHD_BUS_NO_LOW_POWER_STATE)) { in dhdpci_bus_rte_log_time_sync_poll()
9327 time_elapsed = OSL_SYSUPTIME_US() - bus->dhd_rte_time_sync_count; in dhdpci_bus_rte_log_time_sync_poll()
9329 if ((time_elapsed / 1000) >= bus->dhd->dhd_rte_time_sync_ms) { in dhdpci_bus_rte_log_time_sync_poll()
9334 bus->dhd_rte_time_sync_count += time_elapsed; in dhdpci_bus_rte_log_time_sync_poll()
9337 dhd_h2d_log_time_sync_deferred_wq_schedule(bus->dhd); in dhdpci_bus_rte_log_time_sync_poll()
9344 dhdpci_bus_read_frames(dhd_bus_t *bus) in dhdpci_bus_read_frames() argument
9350 if ((bus->api.fw_rev >= PCIE_SHARED_VERSION_6) && in dhdpci_bus_read_frames()
9351 (bus->dhd->dongle_trap_data = dhd_prot_process_trapbuf(bus->dhd))) { in dhdpci_bus_read_frames()
9353 if (bus->dhd->axi_error) { in dhdpci_bus_read_frames()
9358 dhd_bus_handle_mb_data(bus, D2H_DEV_FWHALT); in dhdpci_bus_read_frames()
9363 DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); in dhdpci_bus_read_frames()
9365 dhd_prot_process_ctrlbuf(bus->dhd); in dhdpci_bus_read_frames()
9366 bus->last_process_ctrlbuf_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9368 DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); in dhdpci_bus_read_frames()
9370 /* Do not process rest of ring buf once bus enters low power state (D3_INFORM/D3_ACK) */ in dhdpci_bus_read_frames()
9371 DHD_BUS_LOCK(bus->bus_lock, flags_bus); in dhdpci_bus_read_frames()
9372 if (bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) { in dhdpci_bus_read_frames()
9373 DHD_ERROR(("%s: Bus is in power save state (%d). " in dhdpci_bus_read_frames()
9375 __FUNCTION__, bus->bus_low_power_state)); in dhdpci_bus_read_frames()
9376 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpci_bus_read_frames()
9379 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus); in dhdpci_bus_read_frames()
9381 DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); in dhdpci_bus_read_frames()
9383 dhd_update_txflowrings(bus->dhd); in dhdpci_bus_read_frames()
9384 bus->last_process_flowring_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9390 more |= dhd_prot_process_msgbuf_txcpl(bus->dhd, dhd_txbound, DHD_HP2P_RING); in dhdpci_bus_read_frames()
9392 more |= dhd_prot_process_msgbuf_txcpl(bus->dhd, dhd_txbound, DHD_REGULAR_RING); in dhdpci_bus_read_frames()
9393 bus->last_process_txcpl_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9399 more |= dhd_prot_process_msgbuf_rxcpl(bus->dhd, dhd_rxbound, DHD_HP2P_RING); in dhdpci_bus_read_frames()
9401 more |= dhd_prot_process_msgbuf_rxcpl(bus->dhd, dhd_rxbound, DHD_REGULAR_RING); in dhdpci_bus_read_frames()
9402 bus->last_process_rxcpl_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9406 if (!bus->dhd->dongle_edl_support) in dhdpci_bus_read_frames()
9409 more |= dhd_prot_process_msgbuf_infocpl(bus->dhd, DHD_INFORING_BOUND); in dhdpci_bus_read_frames()
9410 bus->last_process_infocpl_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9414 more |= dhd_prot_process_msgbuf_edl(bus->dhd); in dhdpci_bus_read_frames()
9415 bus->last_process_edl_time = OSL_LOCALTIME_NS(); in dhdpci_bus_read_frames()
9420 if (bus->enable_idle_flowring_mgmt) { in dhdpci_bus_read_frames()
9422 dhd_bus_check_idle_scan(bus); in dhdpci_bus_read_frames()
9427 if (bus->dhd->hang_was_sent) { in dhdpci_bus_read_frames()
9430 DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); in dhdpci_bus_read_frames()
9433 if (bus->read_shm_fail) { in dhdpci_bus_read_frames()
9435 int intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpci_bus_read_frames()
9436 bus->pcie_mailbox_int, 0, 0); in dhdpci_bus_read_frames()
9440 if (bus->dhd->memdump_enabled) { in dhdpci_bus_read_frames()
9441 DHD_OS_WAKE_LOCK(bus->dhd); in dhdpci_bus_read_frames()
9442 bus->dhd->memdump_type = DUMP_TYPE_READ_SHM_FAIL; in dhdpci_bus_read_frames()
9443 dhd_bus_mem_dump(bus->dhd); in dhdpci_bus_read_frames()
9444 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhdpci_bus_read_frames()
9450 bus->no_cfg_restore = 1; in dhdpci_bus_read_frames()
9452 bus->is_linkdown = 1; in dhdpci_bus_read_frames()
9455 dhd_prot_debug_info_print(bus->dhd); in dhdpci_bus_read_frames()
9456 bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN_EP_DETECT; in dhdpci_bus_read_frames()
9457 dhd_os_send_hang_message(bus->dhd); in dhdpci_bus_read_frames()
9462 dhdpci_bus_rte_log_time_sync_poll(bus); in dhdpci_bus_read_frames()
9468 dhdpcie_tcm_valid(dhd_bus_t *bus) in dhdpcie_tcm_valid() argument
9475 shaddr = bus->dongle_ram_base + bus->ramsize - 4; in dhdpcie_tcm_valid()
9478 addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr)); in dhdpcie_tcm_valid()
9480 if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) || in dhdpcie_tcm_valid()
9488 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&sh, in dhdpcie_tcm_valid()
9495 if (sh.console_addr != bus->pcie_sh->console_addr) { in dhdpcie_tcm_valid()
9533 dhdpcie_readshared_console(dhd_bus_t *bus) in dhdpcie_readshared_console() argument
9538 pciedev_shared_t *sh = bus->pcie_sh; in dhdpcie_readshared_console()
9541 shaddr = bus->dongle_ram_base + bus->ramsize - 4; in dhdpcie_readshared_console()
9545 while (((addr == 0) || (addr == bus->nvram_csm)) && !dhd_timeout_expired(&tmo)) { in dhdpcie_readshared_console()
9547 addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr)); in dhdpcie_readshared_console()
9550 if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) || in dhdpcie_readshared_console()
9557 bus->shared_addr = (ulong)addr; in dhdpcie_readshared_console()
9563 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)sh, in dhdpcie_readshared_console()
9571 /* load bus console address */ in dhdpcie_readshared_console()
9572 bus->console_addr = sh->console_addr; in dhdpcie_readshared_console()
9578 dhdpcie_readshared(dhd_bus_t *bus) in dhdpcie_readshared() argument
9583 pciedev_shared_t *sh = bus->pcie_sh; in dhdpcie_readshared()
9587 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_readshared()
9588 dhd_bus_pcie_pwr_req(bus); in dhdpcie_readshared()
9591 shaddr = bus->dongle_ram_base + bus->ramsize - 4; in dhdpcie_readshared()
9595 while (((addr == 0) || (addr == bus->nvram_csm)) && !dhd_timeout_expired(&tmo)) { in dhdpcie_readshared()
9597 addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr)); in dhdpcie_readshared()
9604 bus->no_cfg_restore = 1; in dhdpcie_readshared()
9607 bus->is_linkdown = 1; in dhdpcie_readshared()
9611 if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) || in dhdpcie_readshared()
9619 bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON; in dhdpcie_readshared()
9621 if (bus->dhd->memdump_enabled) { in dhdpcie_readshared()
9622 bus->dhd->memdump_type = DUMP_TYPE_DONGLE_INIT_FAILURE; in dhdpcie_readshared()
9623 dhdpcie_mem_dump(bus); in dhdpcie_readshared()
9629 bus->shared_addr = (ulong)addr; in dhdpcie_readshared()
9635 if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)sh, in dhdpcie_readshared()
9653 /* load bus console address */ in dhdpcie_readshared()
9654 bus->console_addr = sh->console_addr; in dhdpcie_readshared()
9657 bus->dma_rxoffset = bus->pcie_sh->dma_rxoffset; in dhdpcie_readshared()
9658 dhd_prot_rx_dataoffset(bus->dhd, bus->dma_rxoffset); in dhdpcie_readshared()
9660 DHD_INFO(("DMA RX offset from shared Area %d\n", bus->dma_rxoffset)); in dhdpcie_readshared()
9662 bus->api.fw_rev = sh->flags & PCIE_SHARED_VERSION_MASK; in dhdpcie_readshared()
9663 if (!(dhdpcie_check_firmware_compatible(bus->api.fw_rev, PCIE_SHARED_VERSION))) in dhdpcie_readshared()
9668 bus->api.fw_rev)); in dhdpcie_readshared()
9671 dhdpcie_update_bus_api_revisions(bus->api.fw_rev, PCIE_SHARED_VERSION); in dhdpcie_readshared()
9673 bus->rw_index_sz = (sh->flags & PCIE_SHARED_2BYTE_INDICES) ? in dhdpcie_readshared()
9676 __FUNCTION__, bus->rw_index_sz)); in dhdpcie_readshared()
9682 bus->enable_idle_flowring_mgmt = TRUE; in dhdpcie_readshared()
9686 if (IDMA_CAPABLE(bus)) { in dhdpcie_readshared()
9687 if (bus->sih->buscorerev == 23) { in dhdpcie_readshared()
9694 bus->dhd->hwa_enable = TRUE; in dhdpcie_readshared()
9697 bus->dhd->idma_enable = (sh->flags & PCIE_SHARED_IDMA) ? TRUE : FALSE; in dhdpcie_readshared()
9698 bus->dhd->ifrm_enable = (sh->flags & PCIE_SHARED_IFRM) ? TRUE : FALSE; in dhdpcie_readshared()
9701 bus->dhd->d2h_sync_mode = sh->flags & PCIE_SHARED_D2H_SYNC_MODE_MASK; in dhdpcie_readshared()
9703 bus->dhd->dar_enable = (sh->flags & PCIE_SHARED_DAR) ? TRUE : FALSE; in dhdpcie_readshared()
9707 if (!bus->dhd->dma_ring_upd_overwrite) { in dhdpcie_readshared()
9709 if (!IFRM_ENAB(bus->dhd)) { in dhdpcie_readshared()
9710 bus->dhd->dma_h2d_ring_upd_support = TRUE; in dhdpcie_readshared()
9712 bus->dhd->dma_d2h_ring_upd_support = TRUE; in dhdpcie_readshared()
9716 if (bus->dhd->dma_d2h_ring_upd_support) in dhdpcie_readshared()
9717 bus->dhd->d2h_sync_mode = 0; in dhdpcie_readshared()
9721 (bus->dhd->dma_h2d_ring_upd_support ? 1 : 0), in dhdpcie_readshared()
9722 (bus->dhd->dma_d2h_ring_upd_support ? 1 : 0))); in dhdpcie_readshared()
9728 bus->dhd->dma_h2d_ring_upd_support = FALSE; in dhdpcie_readshared()
9729 bus->dhd->dma_d2h_ring_upd_support = FALSE; in dhdpcie_readshared()
9736 bus->dhd->fast_delete_ring_support = TRUE; in dhdpcie_readshared()
9740 bus->dhd->fast_delete_ring_support = FALSE; in dhdpcie_readshared()
9743 /* get ring_info, ring_state and mb data ptrs and store the addresses in bus structure */ in dhdpcie_readshared()
9754 if ((rv = dhdpcie_bus_membytes(bus, FALSE, sh->rings_info_ptr, in dhdpcie_readshared()
9758 bus->h2d_mb_data_ptr_addr = ltoh32(sh->h2d_mb_data_ptr); in dhdpcie_readshared()
9759 bus->d2h_mb_data_ptr_addr = ltoh32(sh->d2h_mb_data_ptr); in dhdpcie_readshared()
9761 if (bus->api.fw_rev >= PCIE_SHARED_VERSION_6) { in dhdpcie_readshared()
9762 bus->max_tx_flowrings = ltoh16(ring_info.max_tx_flowrings); in dhdpcie_readshared()
9763 bus->max_submission_rings = ltoh16(ring_info.max_submission_queues); in dhdpcie_readshared()
9764 bus->max_completion_rings = ltoh16(ring_info.max_completion_rings); in dhdpcie_readshared()
9765 bus->max_cmn_rings = bus->max_submission_rings - bus->max_tx_flowrings; in dhdpcie_readshared()
9766 bus->api.handle_mb_data = dhdpcie_read_handle_mb_data; in dhdpcie_readshared()
9767 bus->use_mailbox = sh->flags & PCIE_SHARED_USE_MAILBOX; in dhdpcie_readshared()
9770 bus->max_tx_flowrings = ltoh16(ring_info.max_tx_flowrings); in dhdpcie_readshared()
9771 bus->max_submission_rings = bus->max_tx_flowrings; in dhdpcie_readshared()
9772 bus->max_completion_rings = BCMPCIE_D2H_COMMON_MSGRINGS; in dhdpcie_readshared()
9773 bus->max_cmn_rings = BCMPCIE_H2D_COMMON_MSGRINGS; in dhdpcie_readshared()
9774 bus->api.handle_mb_data = dhdpcie_handle_mb_data; in dhdpcie_readshared()
9775 bus->use_mailbox = TRUE; in dhdpcie_readshared()
9777 if (bus->max_completion_rings == 0) { in dhdpcie_readshared()
9779 bus->max_completion_rings)); in dhdpcie_readshared()
9782 if (bus->max_submission_rings == 0) { in dhdpcie_readshared()
9784 bus->max_submission_rings)); in dhdpcie_readshared()
9787 if (bus->max_tx_flowrings == 0) { in dhdpcie_readshared()
9788 DHD_ERROR(("dongle txflow rings are invalid %d\n", bus->max_tx_flowrings)); in dhdpcie_readshared()
9795 if (bus->dhd->dma_h2d_ring_upd_support || IDMA_ENAB(bus->dhd)) { in dhdpcie_readshared()
9796 dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, in dhdpcie_readshared()
9797 H2D_DMA_INDX_WR_BUF, bus->max_submission_rings); in dhdpcie_readshared()
9798 dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, in dhdpcie_readshared()
9799 D2H_DMA_INDX_RD_BUF, bus->max_completion_rings); in dhdpcie_readshared()
9805 bus->dhd->dma_h2d_ring_upd_support = FALSE; in dhdpcie_readshared()
9806 bus->dhd->idma_enable = FALSE; in dhdpcie_readshared()
9810 if (bus->dhd->dma_d2h_ring_upd_support) { in dhdpcie_readshared()
9811 dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, in dhdpcie_readshared()
9812 D2H_DMA_INDX_WR_BUF, bus->max_completion_rings); in dhdpcie_readshared()
9813 dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, in dhdpcie_readshared()
9814 H2D_DMA_INDX_RD_BUF, bus->max_submission_rings); in dhdpcie_readshared()
9820 bus->dhd->dma_d2h_ring_upd_support = FALSE; in dhdpcie_readshared()
9824 if (IFRM_ENAB(bus->dhd)) { in dhdpcie_readshared()
9825 dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, in dhdpcie_readshared()
9826 H2D_IFRM_INDX_WR_BUF, bus->max_tx_flowrings); in dhdpcie_readshared()
9831 bus->dhd->ifrm_enable = FALSE; in dhdpcie_readshared()
9836 dhd_fillup_ring_sharedptr_info(bus, &ring_info); in dhdpcie_readshared()
9847 __FUNCTION__, bus->h2d_mb_data_ptr_addr)); in dhdpcie_readshared()
9849 __FUNCTION__, bus->d2h_mb_data_ptr_addr)); in dhdpcie_readshared()
9853 __FUNCTION__, bus->dhd->d2h_sync_mode)); in dhdpcie_readshared()
9855 bus->dhd->d2h_hostrdy_supported = in dhdpcie_readshared()
9858 bus->dhd->ext_trap_data_supported = in dhdpcie_readshared()
9862 bus->dhd->pcie_txs_metadata_enable = 0; in dhdpcie_readshared()
9864 bus->dhd->hscb_enable = in dhdpcie_readshared()
9869 bus->dhd->dongle_edl_support = (sh->flags2 & PCIE_SHARED2_EDL_RING) ? TRUE : FALSE; in dhdpcie_readshared()
9870 DHD_ERROR(("Dongle EDL support: %u\n", bus->dhd->dongle_edl_support)); in dhdpcie_readshared()
9874 bus->dhd->debug_buf_dest_support = in dhdpcie_readshared()
9877 bus->dhd->debug_buf_dest_support ? "Y" : "N")); in dhdpcie_readshared()
9880 if (bus->dhd->hp2p_enable) { in dhdpcie_readshared()
9881 bus->dhd->hp2p_ts_capable = in dhdpcie_readshared()
9883 bus->dhd->hp2p_capable = in dhdpcie_readshared()
9885 bus->dhd->hp2p_capable &= bus->dhd->hp2p_ts_capable; in dhdpcie_readshared()
9888 bus->dhd->hp2p_capable ? "Y" : "N")); in dhdpcie_readshared()
9890 if (bus->dhd->hp2p_capable) { in dhdpcie_readshared()
9891 bus->dhd->pkt_thresh = HP2P_PKT_THRESH; in dhdpcie_readshared()
9892 bus->dhd->pkt_expiry = HP2P_PKT_EXPIRY; in dhdpcie_readshared()
9893 bus->dhd->time_thresh = HP2P_TIME_THRESH; in dhdpcie_readshared()
9895 hp2p_info_t *hp2p_info = &bus->dhd->hp2p_info[addr]; in dhdpcie_readshared()
9912 bus->dhd->db0ts_capable = in dhdpcie_readshared()
9916 if (MULTIBP_ENAB(bus->sih)) { in dhdpcie_readshared()
9917 dhd_bus_pcie_pwr_req_clear(bus); in dhdpcie_readshared()
9923 if (bus->sih->buscorerev >= 68) { in dhdpcie_readshared()
9924 dhd_bus_pcie_pwr_req_wl_domain(bus, FALSE); in dhdpcie_readshared()
9932 dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info) in dhd_fillup_ring_sharedptr_info() argument
9938 uint16 max_tx_flowrings = bus->max_tx_flowrings; in dhd_fillup_ring_sharedptr_info()
9955 bus->ring_sh[i].ring_mem_addr = tcm_memloc; in dhd_fillup_ring_sharedptr_info()
9959 i, bus->ring_sh[i].ring_mem_addr)); in dhd_fillup_ring_sharedptr_info()
9972 bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr; in dhd_fillup_ring_sharedptr_info()
9973 bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr; in dhd_fillup_ring_sharedptr_info()
9976 h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
9977 h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
9980 bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); in dhd_fillup_ring_sharedptr_info()
9985 bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr; in dhd_fillup_ring_sharedptr_info()
9986 bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr; in dhd_fillup_ring_sharedptr_info()
9989 d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
9990 d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
9993 bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); in dhd_fillup_ring_sharedptr_info()
9997 if (bus->api.fw_rev < PCIE_SHARED_VERSION_6) { in dhd_fillup_ring_sharedptr_info()
10005 bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr; in dhd_fillup_ring_sharedptr_info()
10006 bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr; in dhd_fillup_ring_sharedptr_info()
10009 h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
10010 h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
10013 bus->ring_sh[i].ring_state_w, in dhd_fillup_ring_sharedptr_info()
10014 bus->ring_sh[i].ring_state_r)); in dhd_fillup_ring_sharedptr_info()
10017 bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr; in dhd_fillup_ring_sharedptr_info()
10018 bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr; in dhd_fillup_ring_sharedptr_info()
10019 d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
10020 d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz; in dhd_fillup_ring_sharedptr_info()
10022 bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); in dhd_fillup_ring_sharedptr_info()
10027 * Initialize bus module: prepare for communication with the dongle. Called after downloading
10032 dhd_bus_t *bus = dhdp->bus; in dhd_bus_init() local
10037 ASSERT(bus->dhd); in dhd_bus_init()
10038 if (!bus->dhd) in dhd_bus_init()
10041 if (PCIE_RELOAD_WAR_ENAB(bus->sih->buscorerev)) { in dhd_bus_init()
10042 dhd_bus_pcie_pwr_req_clear_reload_war(bus); in dhd_bus_init()
10045 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_init()
10046 dhd_bus_pcie_pwr_req(bus); in dhd_bus_init()
10050 dhd_bus_aer_config(bus); in dhd_bus_init()
10053 bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0); in dhd_bus_init()
10054 ASSERT(bus->reg != NULL); in dhd_bus_init()
10056 /* before opening up bus for data transfer, check if shared are is intact */ in dhd_bus_init()
10060 if ((ret = dhdpcie_readshared_console(bus)) >= 0) { in dhd_bus_init()
10061 if ((ret = dhdpcie_bus_readconsole(bus)) < 0) { in dhd_bus_init()
10067 ret = dhdpcie_readshared(bus); in dhd_bus_init()
10074 bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0); in dhd_bus_init()
10075 ASSERT(bus->reg != NULL); in dhd_bus_init()
10077 dhd_init_bus_lock(bus); in dhd_bus_init()
10079 dhd_init_backplane_access_lock(bus); in dhd_bus_init()
10081 /* Set bus state according to enable result */ in dhd_bus_init()
10083 bus->bus_low_power_state = DHD_BUS_NO_LOW_POWER_STATE; in dhd_bus_init()
10087 if ((ret = dhdpcie_init_d11status(bus)) < 0) { in dhd_bus_init()
10092 dhd_dpc_enable(bus->dhd); in dhd_bus_init()
10094 dhdpcie_bus_intr_enable(bus); in dhd_bus_init()
10096 bus->intr_enabled = TRUE; in dhd_bus_init()
10098 /* bcmsdh_intr_unmask(bus->sdh); */ in dhd_bus_init()
10100 bus->idlecount = 0; in dhd_bus_init()
10101 bus->idletime = (int32)MAX_IDLE_COUNT; in dhd_bus_init()
10102 init_waitqueue_head(&bus->rpm_queue); in dhd_bus_init()
10103 mutex_init(&bus->pm_lock); in dhd_bus_init()
10105 bus->idletime = 0; in dhd_bus_init()
10109 if (bus->api.fw_rev < PCIE_SHARED_VERSION_6) { in dhd_bus_init()
10110 bus->use_d0_inform = TRUE; in dhd_bus_init()
10112 bus->use_d0_inform = FALSE; in dhd_bus_init()
10116 if (MULTIBP_ENAB(bus->sih)) { in dhd_bus_init()
10117 dhd_bus_pcie_pwr_req_clear(bus); in dhd_bus_init()
10123 dhdpcie_init_shared_addr(dhd_bus_t *bus) in dhdpcie_init_shared_addr() argument
10128 addr = bus->dongle_ram_base + bus->ramsize - 4; in dhdpcie_init_shared_addr()
10130 dhdpcie_runtime_bus_wake(bus->dhd, TRUE, __builtin_return_address(0)); in dhdpcie_init_shared_addr()
10132 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val)); in dhdpcie_init_shared_addr()
10316 dhdpcie_sromotp_customvar(dhd_bus_t *bus, uint32 *customvar1, uint32 *customvar2) in dhdpcie_sromotp_customvar() argument
10332 cur_coreid = si_coreid(bus->sih); in dhdpcie_sromotp_customvar()
10334 chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0); in dhdpcie_sromotp_customvar()
10336 chipc_corerev = si_corerev(bus->sih); in dhdpcie_sromotp_customvar()
10343 if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip) && in dhdpcie_sromotp_customvar()
10344 ((uint16)bus->sih->chip != BCM4355_CHIP_ID) && in dhdpcie_sromotp_customvar()
10345 ((uint16)bus->sih->chip != BCM4359_CHIP_ID) && in dhdpcie_sromotp_customvar()
10346 ((uint16)bus->sih->chip != BCM4349_CHIP_ID)) { in dhdpcie_sromotp_customvar()
10433 if (bus->regs == NULL) { in dhdpcie_sromotp_customvar()
10444 nvm_shadow = (volatile uint16 *)si_setcore(bus->sih, GCI_CORE_ID, 0); in dhdpcie_sromotp_customvar()
10513 si_setcore(bus->sih, cur_coreid, 0); in dhdpcie_sromotp_customvar()
10527 dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b) in dhdpcie_cc_nvmshadow() argument
10542 cur_coreid = si_coreid(bus->sih); in dhdpcie_cc_nvmshadow()
10544 chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0); in dhdpcie_cc_nvmshadow()
10547 chipc_corerev = si_corerev(bus->sih); in dhdpcie_cc_nvmshadow()
10556 if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip) && in dhdpcie_cc_nvmshadow()
10557 ((uint16)bus->sih->chip != BCM4355_CHIP_ID) && in dhdpcie_cc_nvmshadow()
10558 ((uint16)bus->sih->chip != BCM4364_CHIP_ID)) { in dhdpcie_cc_nvmshadow()
10654 if (bus->regs == NULL) { in dhdpcie_cc_nvmshadow()
10667 nvm_shadow = (volatile uint16 *)si_setcore(bus->sih, GCI_CORE_ID, 0); in dhdpcie_cc_nvmshadow()
10693 si_setcore(bus->sih, cur_coreid, 0); in dhdpcie_cc_nvmshadow()
10699 void dhd_bus_clean_flow_ring(dhd_bus_t *bus, void *node) in dhd_bus_clean_flow_ring() argument
10712 dhd_tcpack_info_tbl_clean(bus->dhd); in dhd_bus_clean_flow_ring()
10717 bus->dhd->hp2p_ring_active = FALSE; in dhd_bus_clean_flow_ring()
10722 /* clean up BUS level info */ in dhd_bus_clean_flow_ring()
10726 while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { in dhd_bus_clean_flow_ring()
10727 PKTFREE(bus->dhd->osh, pkt, TRUE); in dhd_bus_clean_flow_ring()
10732 dhd_flow_queue_reinit(bus->dhd, queue, FLOW_RING_QUEUE_THRESHOLD); in dhd_bus_clean_flow_ring()
10739 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_clean_flow_ring()
10741 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_clean_flow_ring()
10744 dhd_prot_flowrings_pool_release(bus->dhd, in dhd_bus_clean_flow_ring()
10748 dhd_flowid_free(bus->dhd, flow_ring_node->flow_info.ifindex, in dhd_bus_clean_flow_ring()
10757 dhd_bus_flow_ring_create_request(dhd_bus_t *bus, void *arg) in dhd_bus_flow_ring_create_request() argument
10764 if (dhd_prot_flow_ring_create(bus->dhd, flow_ring_node) != BCME_OK) in dhd_bus_flow_ring_create_request()
10772 dhd_bus_flow_ring_create_response(dhd_bus_t *bus, uint16 flowid, int32 status) in dhd_bus_flow_ring_create_response() argument
10780 if (flowid >= bus->dhd->num_flow_rings) { in dhd_bus_flow_ring_create_response()
10782 flowid, bus->dhd->num_flow_rings)); in dhd_bus_flow_ring_create_response()
10786 flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); in dhd_bus_flow_ring_create_response()
10804 dhd_bus_clean_flow_ring(bus, flow_ring_node); in dhd_bus_flow_ring_create_response()
10828 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_flow_ring_create_response()
10829 dll_prepend(&bus->flowring_active_list, &flow_ring_node->list); in dhd_bus_flow_ring_create_response()
10830 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_flow_ring_create_response()
10832 dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */ in dhd_bus_flow_ring_create_response()
10838 dhd_bus_flow_ring_delete_request(dhd_bus_t *bus, void *arg) in dhd_bus_flow_ring_delete_request() argument
10853 dhd_tcpack_info_tbl_clean(bus->dhd); in dhd_bus_flow_ring_delete_request()
10866 while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { in dhd_bus_flow_ring_delete_request()
10867 PKTFREE(bus->dhd->osh, pkt, TRUE); in dhd_bus_flow_ring_delete_request()
10874 dhd_prot_flow_ring_delete(bus->dhd, flow_ring_node); in dhd_bus_flow_ring_delete_request()
10880 dhd_bus_flow_ring_delete_response(dhd_bus_t *bus, uint16 flowid, uint32 status) in dhd_bus_flow_ring_delete_response() argument
10887 if (flowid >= bus->dhd->num_flow_rings) { in dhd_bus_flow_ring_delete_response()
10889 flowid, bus->dhd->num_flow_rings)); in dhd_bus_flow_ring_delete_response()
10893 flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); in dhd_bus_flow_ring_delete_response()
10913 dhd_bus_clean_flow_ring(bus, flow_ring_node); in dhd_bus_flow_ring_delete_response()
10919 int dhd_bus_flow_ring_flush_request(dhd_bus_t *bus, void *arg) in dhd_bus_flow_ring_flush_request() argument
10941 dhd_tcpack_info_tbl_clean(bus->dhd); in dhd_bus_flow_ring_flush_request()
10945 while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { in dhd_bus_flow_ring_flush_request()
10946 PKTFREE(bus->dhd->osh, pkt, TRUE); in dhd_bus_flow_ring_flush_request()
10953 dhd_prot_flow_ring_flush(bus->dhd, flow_ring_node); in dhd_bus_flow_ring_flush_request()
10959 dhd_bus_flow_ring_flush_response(dhd_bus_t *bus, uint16 flowid, uint32 status) in dhd_bus_flow_ring_flush_response() argument
10970 if (flowid >= bus->dhd->num_flow_rings) { in dhd_bus_flow_ring_flush_response()
10972 flowid, bus->dhd->num_flow_rings)); in dhd_bus_flow_ring_flush_response()
10976 flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); in dhd_bus_flow_ring_flush_response()
10995 dhd_bus_max_h2d_queues(struct dhd_bus *bus) in dhd_bus_max_h2d_queues() argument
10997 return bus->max_submission_rings; in dhd_bus_max_h2d_queues()
11010 dhdp->bus->is_linkdown = val; in dhd_bus_set_linkdown()
11016 return dhdp->bus->is_linkdown; in dhd_bus_get_linkdown()
11022 return dhdp->bus->cto_triggered; in dhd_bus_get_cto()
11028 dhd_bus_flow_ring_resume_request(dhd_bus_t *bus, void *arg) in dhd_bus_flow_ring_resume_request() argument
11037 dhd_prot_flow_ring_resume(bus->dhd, flow_ring_node); in dhd_bus_flow_ring_resume_request()
11044 dhd_bus_flow_ring_resume_response(dhd_bus_t *bus, uint16 flowid, int32 status) in dhd_bus_flow_ring_resume_response() argument
11051 flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); in dhd_bus_flow_ring_resume_response()
11065 dhd_bus_schedule_queue(bus, flowid, FALSE); in dhd_bus_flow_ring_resume_response()
11071 dhd_bus_check_idle_scan(dhd_bus_t *bus) in dhd_bus_check_idle_scan() argument
11077 diff = time_stamp - bus->active_list_last_process_ts; in dhd_bus_check_idle_scan()
11080 dhd_bus_idle_scan(bus); in dhd_bus_check_idle_scan()
11081 bus->active_list_last_process_ts = OSL_SYSUPTIME(); in dhd_bus_check_idle_scan()
11089 dhd_bus_idle_scan(dhd_bus_t *bus) in dhd_bus_idle_scan() argument
11099 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_idle_scan()
11101 for (item = dll_tail_p(&bus->flowring_active_list); in dhd_bus_idle_scan()
11102 !dll_end(&bus->flowring_active_list, item); item = prev) { in dhd_bus_idle_scan()
11107 if (flow_ring_node->flowid == (bus->max_submission_rings - 1)) in dhd_bus_idle_scan()
11115 __dhd_flow_ring_delete_from_active_list(bus, flow_ring_node); in dhd_bus_idle_scan()
11124 __dhd_flow_ring_delete_from_active_list(bus, flow_ring_node); in dhd_bus_idle_scan()
11130 dhd_prot_flow_ring_batch_suspend_request(bus->dhd, ringid, count); in dhd_bus_idle_scan()
11142 dhd_prot_flow_ring_batch_suspend_request(bus->dhd, ringid, count); in dhd_bus_idle_scan()
11145 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_bus_idle_scan()
11150 void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node) in dhd_flow_ring_move_to_active_list_head() argument
11155 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_move_to_active_list_head()
11157 list = dll_head_p(&bus->flowring_active_list); in dhd_flow_ring_move_to_active_list_head()
11160 dll_prepend(&bus->flowring_active_list, &flow_ring_node->list); in dhd_flow_ring_move_to_active_list_head()
11166 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_move_to_active_list_head()
11171 void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node) in dhd_flow_ring_add_to_active_list() argument
11175 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_add_to_active_list()
11177 dll_prepend(&bus->flowring_active_list, &flow_ring_node->list); in dhd_flow_ring_add_to_active_list()
11181 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_add_to_active_list()
11185 void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node) in __dhd_flow_ring_delete_from_active_list() argument
11190 void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node) in dhd_flow_ring_delete_from_active_list() argument
11194 DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_delete_from_active_list()
11196 __dhd_flow_ring_delete_from_active_list(bus, flow_ring_node); in dhd_flow_ring_delete_from_active_list()
11198 DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); in dhd_flow_ring_delete_from_active_list()
11205 dhdpcie_bus_clock_start(struct dhd_bus *bus) in dhdpcie_bus_clock_start() argument
11207 return dhdpcie_start_host_pcieclock(bus); in dhdpcie_bus_clock_start()
11211 dhdpcie_bus_clock_stop(struct dhd_bus *bus) in dhdpcie_bus_clock_stop() argument
11213 return dhdpcie_stop_host_pcieclock(bus); in dhdpcie_bus_clock_stop()
11217 dhdpcie_bus_disable_device(struct dhd_bus *bus) in dhdpcie_bus_disable_device() argument
11219 return dhdpcie_disable_device(bus); in dhdpcie_bus_disable_device()
11223 dhdpcie_bus_enable_device(struct dhd_bus *bus) in dhdpcie_bus_enable_device() argument
11225 return dhdpcie_enable_device(bus); in dhdpcie_bus_enable_device()
11229 dhdpcie_bus_alloc_resource(struct dhd_bus *bus) in dhdpcie_bus_alloc_resource() argument
11231 return dhdpcie_alloc_resource(bus); in dhdpcie_bus_alloc_resource()
11235 dhdpcie_bus_free_resource(struct dhd_bus *bus) in dhdpcie_bus_free_resource() argument
11237 dhdpcie_free_resource(bus); in dhdpcie_bus_free_resource()
11241 dhd_bus_request_irq(struct dhd_bus *bus) in dhd_bus_request_irq() argument
11243 return dhdpcie_bus_request_irq(bus); in dhd_bus_request_irq()
11247 dhdpcie_bus_dongle_attach(struct dhd_bus *bus) in dhdpcie_bus_dongle_attach() argument
11249 return dhdpcie_dongle_attach(bus); in dhdpcie_bus_dongle_attach()
11253 dhd_bus_release_dongle(struct dhd_bus *bus) in dhd_bus_release_dongle() argument
11260 if (bus) { in dhd_bus_release_dongle()
11261 osh = bus->osh; in dhd_bus_release_dongle()
11264 if (bus->dhd) { in dhd_bus_release_dongle()
11269 dongle_isolation = bus->dhd->dongle_isolation; in dhd_bus_release_dongle()
11270 dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE); in dhd_bus_release_dongle()
11278 dhdpcie_cto_cfg_init(struct dhd_bus *bus, bool enable) in dhdpcie_cto_cfg_init() argument
11282 dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4, in dhdpcie_cto_cfg_init()
11284 val = dhdpcie_bus_cfg_read_dword(bus, PCI_SPROM_CONTROL, 4); in dhdpcie_cto_cfg_init()
11285 dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, val | SPROM_BACKPLANE_EN); in dhdpcie_cto_cfg_init()
11287 dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4, 0); in dhdpcie_cto_cfg_init()
11288 val = dhdpcie_bus_cfg_read_dword(bus, PCI_SPROM_CONTROL, 4); in dhdpcie_cto_cfg_init()
11289 dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, val & ~SPROM_BACKPLANE_EN); in dhdpcie_cto_cfg_init()
11295 dhdpcie_cto_init(struct dhd_bus *bus, bool enable) in dhdpcie_cto_init() argument
11297 if (bus->sih->buscorerev < 19) { in dhdpcie_cto_init()
11299 __FUNCTION__, bus->sih->buscorerev)); in dhdpcie_cto_init()
11303 if (bus->sih->buscorerev == 19) { in dhdpcie_cto_init()
11305 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_init()
11308 pcie_lnkst = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_init()
11317 bus->cto_enable = enable; in dhdpcie_cto_init()
11319 dhdpcie_cto_cfg_init(bus, enable); in dhdpcie_cto_init()
11322 if (bus->cto_threshold == 0) { in dhdpcie_cto_init()
11323 bus->cto_threshold = PCIE_CTO_TO_THRESH_DEFAULT; in dhdpcie_cto_init()
11325 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_init()
11327 ((bus->cto_threshold << PCIE_CTO_TO_THRESHOLD_SHIFT) & in dhdpcie_cto_init()
11333 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_init()
11338 __FUNCTION__, bus->cto_enable)); in dhdpcie_cto_init()
11344 dhdpcie_cto_error_recovery(struct dhd_bus *bus) in dhdpcie_cto_error_recovery() argument
11350 pci_intmask = dhdpcie_bus_cfg_read_dword(bus, PCI_INT_MASK, 4); in dhdpcie_cto_error_recovery()
11351 dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4, pci_intmask & ~PCI_CTO_INT_MASK); in dhdpcie_cto_error_recovery()
11353 DHD_OS_WAKE_LOCK(bus->dhd); in dhdpcie_cto_error_recovery()
11355 DHD_ERROR(("--- CTO Triggered --- %d\n", bus->pwr_req_ref)); in dhdpcie_cto_error_recovery()
11360 dhd_bus_dump_dar_registers(bus); in dhdpcie_cto_error_recovery()
11363 val = dhdpcie_bus_cfg_read_dword(bus, PCI_SPROM_CONTROL, 4); in dhdpcie_cto_error_recovery()
11364 dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, val | SPROM_CFG_TO_SB_RST); in dhdpcie_cto_error_recovery()
11368 err_status = si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_error_recovery()
11369 DAR_ERRLOG(bus->sih->buscorerev), in dhdpcie_cto_error_recovery()
11372 si_corereg(bus->sih, bus->sih->buscoreidx, in dhdpcie_cto_error_recovery()
11373 DAR_ERRLOG(bus->sih->buscorerev), in dhdpcie_cto_error_recovery()
11383 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhdpcie_cto_error_recovery()
11389 dhdpcie_bus_cfg_write_dword(bus, PCI_INT_STATUS, 4, PCI_CTO_INT_MASK); in dhdpcie_cto_error_recovery()
11395 val = dhdpcie_bus_cfg_read_dword(bus, PCI_SPROM_CONTROL, 4); in dhdpcie_cto_error_recovery()
11399 dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, val & ~SPROM_CFG_TO_SB_RST); in dhdpcie_cto_error_recovery()
11401 val = dhdpcie_bus_cfg_read_dword(bus, PCI_SPROM_CONTROL, 4); in dhdpcie_cto_error_recovery()
11405 DHD_OS_WAKE_UNLOCK(bus->dhd); in dhdpcie_cto_error_recovery()
11411 dhdpcie_ssreset_dis_enum_rst(struct dhd_bus *bus) in dhdpcie_ssreset_dis_enum_rst() argument
11415 val = dhdpcie_bus_cfg_read_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL, 4); in dhdpcie_ssreset_dis_enum_rst()
11416 dhdpcie_bus_cfg_write_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL, 4, in dhdpcie_ssreset_dis_enum_rst()
11422 dhdpcie_init_d11status(struct dhd_bus *bus) in dhdpcie_init_d11status() argument
11428 if (bus->pcie_sh->flags2 & PCIE_SHARED2_D2H_D11_TX_STATUS) { in dhdpcie_init_d11status()
11429 flags2 = bus->pcie_sh->flags2; in dhdpcie_init_d11status()
11430 addr = bus->shared_addr + OFFSETOF(pciedev_shared_t, flags2); in dhdpcie_init_d11status()
11432 ret = dhdpcie_bus_membytes(bus, TRUE, addr, in dhdpcie_init_d11status()
11439 bus->pcie_sh->flags2 = flags2; in dhdpcie_init_d11status()
11440 bus->dhd->d11_tx_status = TRUE; in dhdpcie_init_d11status()
11447 dhdpcie_init_d11status(struct dhd_bus *bus) in dhdpcie_init_d11status() argument
11457 return dhdpcie_oob_intr_register(dhdp->bus); in dhd_bus_oob_intr_register()
11463 dhdpcie_oob_intr_unregister(dhdp->bus); in dhd_bus_oob_intr_unregister()
11469 dhdpcie_oob_intr_set(dhdp->bus, enable); in dhd_bus_oob_intr_set()
11474 dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus) in dhdpcie_bus_get_pcie_hostready_supported() argument
11476 return bus->dhd->d2h_hostrdy_supported; in dhdpcie_bus_get_pcie_hostready_supported()
11482 dhd_bus_t *bus = pub->bus; in dhd_pcie_dump_core_regs() local
11484 uint32 core_addr = SI_ENUM_BASE(bus->sih) + coreoffset; in dhd_pcie_dump_core_regs()
11488 core_addr = SI_ENUM_BASE(bus->sih) + coreoffset + first_addr; in dhd_pcie_dump_core_regs()
11489 if (serialized_backplane_access(bus, core_addr, 4, &value, TRUE) != BCME_OK) { in dhd_pcie_dump_core_regs()
11498 dhdpcie_bus_get_pcie_hwa_supported(dhd_bus_t *bus) in dhdpcie_bus_get_pcie_hwa_supported() argument
11500 if (!bus->dhd) in dhdpcie_bus_get_pcie_hwa_supported()
11502 else if (bus->hwa_enab_bmap) { in dhdpcie_bus_get_pcie_hwa_supported()
11503 return bus->dhd->hwa_enable; in dhdpcie_bus_get_pcie_hwa_supported()
11510 dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus) in dhdpcie_bus_get_pcie_idma_supported() argument
11512 if (!bus->dhd) in dhdpcie_bus_get_pcie_idma_supported()
11514 else if (bus->idma_enabled) { in dhdpcie_bus_get_pcie_idma_supported()
11515 return bus->dhd->idma_enable; in dhdpcie_bus_get_pcie_idma_supported()
11522 dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus) in dhdpcie_bus_get_pcie_ifrm_supported() argument
11524 if (!bus->dhd) in dhdpcie_bus_get_pcie_ifrm_supported()
11526 else if (bus->ifrm_enabled) { in dhdpcie_bus_get_pcie_ifrm_supported()
11527 return bus->dhd->ifrm_enable; in dhdpcie_bus_get_pcie_ifrm_supported()
11534 dhdpcie_bus_get_pcie_dar_supported(dhd_bus_t *bus) in dhdpcie_bus_get_pcie_dar_supported() argument
11536 if (!bus->dhd) { in dhdpcie_bus_get_pcie_dar_supported()
11538 } else if (bus->dar_enabled) { in dhdpcie_bus_get_pcie_dar_supported()
11539 return bus->dhd->dar_enable; in dhdpcie_bus_get_pcie_dar_supported()
11546 dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option) in dhdpcie_bus_enab_pcie_dw() argument
11549 bus->dw_option = dw_option; in dhdpcie_bus_enab_pcie_dw()
11553 dhd_bus_dump_trap_info(dhd_bus_t *bus, struct bcmstrbuf *strbuf) in dhd_bus_dump_trap_info() argument
11555 trap_t *tr = &bus->dhd->last_trap_info; in dhd_bus_dump_trap_info()
11564 ltoh32(bus->pcie_sh->trap_addr), in dhd_bus_dump_trap_info()
11575 struct dhd_bus *bus = dhdp->bus; in dhd_bus_readwrite_bp_addr() local
11577 if (serialized_backplane_access(bus, addr, size, data, read) != BCME_OK) { in dhd_bus_readwrite_bp_addr()
11588 return dhd->bus->idletime; in dhd_get_idletime()
11595 if (serialized_backplane_access(dhd->bus, addr, sizeof(uint), val, read) != BCME_OK) { in dhd_sbreg_op()
11632 if (serialized_backplane_access(dhd->bus, addr, in dhdpcie_get_sssr_fifo_dump()
11650 si_t *sih = dhd->bus->sih; in dhdpcie_get_sssr_dig_dump()
11668 int err = dhdpcie_bus_membytes(dhd->bus, FALSE, addr_reg, (uint8 *)buf, in dhdpcie_get_sssr_dig_dump()
11686 if (serialized_backplane_access(dhd->bus, addr, sizeof(uint), in dhdpcie_get_sssr_dig_dump()
11753 uint32 endaddr = dhd->bus->dongle_ram_base + dhd->bus->ramsize - 4; in dhdpcie_get_etd_preserve_logs()
11773 if ((baseaddr < dhd->bus->dongle_ram_base) || in dhdpcie_get_etd_preserve_logs()
11781 err = dhdpcie_bus_membytes(dhd->bus, FALSE, in dhdpcie_get_etd_preserve_logs()
11798 if ((baseaddr < dhd->bus->dongle_ram_base) || in dhdpcie_get_etd_preserve_logs()
11805 err = dhdpcie_bus_membytes(dhd->bus, FALSE, in dhdpcie_get_etd_preserve_logs()
12183 if (dhd->bus->is_linkdown) { in dhdpcie_sssr_dump()
12226 if (dhd->bus->is_linkdown) { in dhdpcie_fis_trigger()
12232 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhdpcie_fis_trigger()
12233 DAR_FIS_CTRL(dhd->bus->sih->buscorerev), ~0, DAR_FIS_START_MASK); in dhdpcie_fis_trigger()
12255 if (dhd->bus->is_linkdown) { in dhdpcie_fis_dump()
12261 PMU_REG(dhd->bus->sih, min_res_mask, ~0, in dhdpcie_fis_dump()
12262 PMU_REG(dhd->bus->sih, max_res_mask, 0, 0)); in dhdpcie_fis_dump()
12273 PMU_REG(dhd->bus->sih, fis_ctrl_status, PMU_CLEAR_FIS_DONE_MASK, PMU_CLEAR_FIS_DONE_MASK); in dhdpcie_fis_dump()
12299 return &dhd->bus->wake_counts; in dhd_bus_get_wakecount()
12304 return bcmpcie_set_get_wake(dhd->bus, 0); in dhd_bus_get_bus_wake()
12312 dhdpcie_wrt_rnd(struct dhd_bus *bus) in dhdpcie_wrt_rnd() argument
12318 uint32 addr = bus->dongle_ram_base + (bus->ramsize - BCM_NVRAM_OFFSET_TCM) - in dhdpcie_wrt_rnd()
12319 ((bus->nvram_csm & 0xffff)* BCM_NVRAM_IMG_COMPRS_FACTOR + sizeof(rnd_data)); in dhdpcie_wrt_rnd()
12325 dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&rnd_data, sizeof(rnd_data)); in dhdpcie_wrt_rnd()
12330 bus->dhd->rnd_buf = NULL; in dhdpcie_wrt_rnd()
12332 ret = dhd_get_rnd_info(bus->dhd); in dhdpcie_wrt_rnd()
12333 if (bus->dhd->rnd_buf) { in dhdpcie_wrt_rnd()
12336 dhdpcie_bus_membytes(bus, TRUE, addr, bus->dhd->rnd_buf, bus->dhd->rnd_len); in dhdpcie_wrt_rnd()
12339 dhd_dump_rnd_info(bus->dhd, bus->dhd->rnd_buf, bus->dhd->rnd_len); in dhdpcie_wrt_rnd()
12341 /* bus->dhd->rnd_buf is allocated in dhd_get_rnd_info, free here */ in dhdpcie_wrt_rnd()
12342 MFREE(bus->dhd->osh, bus->dhd->rnd_buf, bus->dhd->rnd_len); in dhdpcie_wrt_rnd()
12343 bus->dhd->rnd_buf = NULL; in dhdpcie_wrt_rnd()
12353 dhdpcie_bus_membytes(bus, TRUE, addr, rand_buf, count); in dhdpcie_wrt_rnd()
12357 dhd_dump_rnd_info(bus->dhd, rand_buf, count); in dhdpcie_wrt_rnd()
12366 struct dhd_bus *bus = dhd->bus; in dhd_pcie_intr_count_dump() local
12371 bus->resume_intr_enable_count, bus->dpc_intr_enable_count)); in dhd_pcie_intr_count_dump()
12373 bus->isr_intr_disable_count, bus->suspend_intr_disable_count)); in dhd_pcie_intr_count_dump()
12376 bus->oob_intr_count, bus->oob_intr_enable_count, in dhd_pcie_intr_count_dump()
12377 bus->oob_intr_disable_count)); in dhd_pcie_intr_count_dump()
12379 dhdpcie_get_oob_irq_num(bus), in dhd_pcie_intr_count_dump()
12380 GET_SEC_USEC(bus->last_oob_irq_time))); in dhd_pcie_intr_count_dump()
12383 GET_SEC_USEC(bus->last_oob_irq_enable_time), in dhd_pcie_intr_count_dump()
12384 GET_SEC_USEC(bus->last_oob_irq_disable_time))); in dhd_pcie_intr_count_dump()
12386 dhdpcie_get_oob_irq_status(bus), in dhd_pcie_intr_count_dump()
12390 bus->dpc_return_busdown_count, bus->non_ours_irq_count)); in dhd_pcie_intr_count_dump()
12397 GET_SEC_USEC(bus->isr_entry_time), in dhd_pcie_intr_count_dump()
12398 GET_SEC_USEC(bus->isr_exit_time))); in dhd_pcie_intr_count_dump()
12401 GET_SEC_USEC(bus->dpc_sched_time), in dhd_pcie_intr_count_dump()
12402 GET_SEC_USEC(bus->last_non_ours_irq_time))); in dhd_pcie_intr_count_dump()
12405 GET_SEC_USEC(bus->dpc_entry_time), in dhd_pcie_intr_count_dump()
12406 GET_SEC_USEC(bus->last_process_ctrlbuf_time))); in dhd_pcie_intr_count_dump()
12409 GET_SEC_USEC(bus->last_process_flowring_time), in dhd_pcie_intr_count_dump()
12410 GET_SEC_USEC(bus->last_process_txcpl_time))); in dhd_pcie_intr_count_dump()
12414 GET_SEC_USEC(bus->last_process_rxcpl_time), in dhd_pcie_intr_count_dump()
12415 GET_SEC_USEC(bus->last_process_infocpl_time), in dhd_pcie_intr_count_dump()
12416 GET_SEC_USEC(bus->last_process_edl_time))); in dhd_pcie_intr_count_dump()
12419 GET_SEC_USEC(bus->dpc_exit_time), in dhd_pcie_intr_count_dump()
12420 GET_SEC_USEC(bus->resched_dpc_time))); in dhd_pcie_intr_count_dump()
12422 GET_SEC_USEC(bus->last_d3_inform_time))); in dhd_pcie_intr_count_dump()
12426 GET_SEC_USEC(bus->last_suspend_start_time), in dhd_pcie_intr_count_dump()
12427 GET_SEC_USEC(bus->last_suspend_end_time))); in dhd_pcie_intr_count_dump()
12430 GET_SEC_USEC(bus->last_resume_start_time), in dhd_pcie_intr_count_dump()
12431 GET_SEC_USEC(bus->last_resume_end_time))); in dhd_pcie_intr_count_dump()
12457 si_t *sih = dhd->bus->sih; in dhd_pcie_dump_wrapper_regs()
12562 si_setcoreidx(dhd->bus->sih, save_idx); in dhd_pcie_dump_wrapper_regs()
12570 if (dhd->bus->is_linkdown) { in dhd_pcie_dma_info_dump()
12580 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x200, 0, 0), in dhd_pcie_dma_info_dump()
12581 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x204, 0, 0))); in dhd_pcie_dma_info_dump()
12583 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x208, 0, 0), in dhd_pcie_dma_info_dump()
12584 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x20C, 0, 0))); in dhd_pcie_dma_info_dump()
12586 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x210, 0, 0), in dhd_pcie_dma_info_dump()
12587 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x214, 0, 0))); in dhd_pcie_dma_info_dump()
12590 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x220, 0, 0), in dhd_pcie_dma_info_dump()
12591 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x224, 0, 0))); in dhd_pcie_dma_info_dump()
12593 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x228, 0, 0), in dhd_pcie_dma_info_dump()
12594 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x22C, 0, 0))); in dhd_pcie_dma_info_dump()
12596 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x230, 0, 0), in dhd_pcie_dma_info_dump()
12597 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x234, 0, 0))); in dhd_pcie_dma_info_dump()
12601 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x240, 0, 0), in dhd_pcie_dma_info_dump()
12602 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x244, 0, 0))); in dhd_pcie_dma_info_dump()
12604 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x248, 0, 0), in dhd_pcie_dma_info_dump()
12605 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x24C, 0, 0))); in dhd_pcie_dma_info_dump()
12607 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x250, 0, 0), in dhd_pcie_dma_info_dump()
12608 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x254, 0, 0))); in dhd_pcie_dma_info_dump()
12611 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x260, 0, 0), in dhd_pcie_dma_info_dump()
12612 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x264, 0, 0))); in dhd_pcie_dma_info_dump()
12614 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x268, 0, 0), in dhd_pcie_dma_info_dump()
12615 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x26C, 0, 0))); in dhd_pcie_dma_info_dump()
12617 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x270, 0, 0), in dhd_pcie_dma_info_dump()
12618 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x274, 0, 0))); in dhd_pcie_dma_info_dump()
12632 intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_dump_int_regs()
12633 dhd->bus->pcie_mailbox_int, 0, 0); in dhd_pcie_dump_int_regs()
12639 intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_dump_int_regs()
12640 dhd->bus->pcie_mailbox_mask, 0, 0); in dhd_pcie_dump_int_regs()
12646 d2h_db0 = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_dump_int_regs()
12656 dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0); in dhd_pcie_dump_int_regs()
12658 dhd->bus->def_intmask)); in dhd_pcie_dump_int_regs()
12668 dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_dump_rc_conf_space_cap()
12672 dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_dump_rc_conf_space_cap()
12674 dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_dump_rc_conf_space_cap()
12676 dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_dump_rc_conf_space_cap()
12678 dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_dump_rc_conf_space_cap()
12688 DHD_ERROR(("bus->bus_low_power_state = %d\n", dhd->bus->bus_low_power_state)); in dhd_pcie_debug_info_dump()
12689 host_irq_disabled = dhdpcie_irq_disabled(dhd->bus); in dhd_pcie_debug_info_dump()
12695 dhdpcie_dump_resource(dhd->bus); in dhd_pcie_debug_info_dump()
12700 dhd_debug_get_rc_linkcap(dhd->bus))); in dhd_pcie_debug_info_dump()
12702 if (dhd->bus->is_linkdown && !dhd->bus->cto_triggered) { in dhd_pcie_debug_info_dump()
12712 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_STATUS_CMD, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12714 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_BASEADDR0, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12716 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_BASEADDR1, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12718 dhd_pcie_config_read(dhd->bus->osh, PCIE_CFG_PMCSR, sizeof(uint32)))); in dhd_pcie_debug_info_dump()
12721 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_LINK_STATUS_CTRL, in dhd_pcie_debug_info_dump()
12723 dhd_pcie_config_read(dhd->bus->osh, PCIECFGGEN_DEV_STATUS_CTRL2, in dhd_pcie_debug_info_dump()
12725 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_PML1_SUB_CTRL1, in dhd_pcie_debug_info_dump()
12729 dhdpcie_ep_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR, in dhd_pcie_debug_info_dump()
12733 dhd_pcie_config_read(dhd->bus->osh, PCI_TLP_HDR_LOG1, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12735 dhd_pcie_config_read(dhd->bus->osh, PCI_TLP_HDR_LOG2, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12737 dhd_pcie_config_read(dhd->bus->osh, PCI_TLP_HDR_LOG3, sizeof(uint32)), in dhd_pcie_debug_info_dump()
12739 dhd_pcie_config_read(dhd->bus->osh, PCI_TLP_HDR_LOG4, sizeof(uint32)))); in dhd_pcie_debug_info_dump()
12740 if (dhd->bus->sih->buscorerev >= 24) { in dhd_pcie_debug_info_dump()
12743 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_DEV_STATUS_CTRL, in dhd_pcie_debug_info_dump()
12745 dhd_pcie_config_read(dhd->bus->osh, PCIE_CFG_SUBSYSTEM_CONTROL, in dhd_pcie_debug_info_dump()
12747 dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_PML1_SUB_CTRL2, in dhd_pcie_debug_info_dump()
12749 dhd_bus_dump_dar_registers(dhd->bus); in dhd_pcie_debug_info_dump()
12753 if (dhd->bus->is_linkdown) { in dhd_pcie_debug_info_dump()
12762 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ0), in dhd_pcie_debug_info_dump()
12764 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ1), in dhd_pcie_debug_info_dump()
12766 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ2), in dhd_pcie_debug_info_dump()
12768 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ3))); in dhd_pcie_debug_info_dump()
12771 if (dhd->bus->sih->buscorerev >= 24) { in dhd_pcie_debug_info_dump()
12776 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_LTSSM_HIST_0), in dhd_pcie_debug_info_dump()
12778 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_LTSSM_HIST_1), in dhd_pcie_debug_info_dump()
12780 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_LTSSM_HIST_2), in dhd_pcie_debug_info_dump()
12782 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_LTSSM_HIST_3))); in dhd_pcie_debug_info_dump()
12786 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_TREFUP), in dhd_pcie_debug_info_dump()
12788 dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_TREFUP_EXT))); in dhd_pcie_debug_info_dump()
12794 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12797 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12799 PCIFunctionIntstatus(dhd->bus->sih->buscorerev), in dhd_pcie_debug_info_dump()
12800 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12801 PCIFunctionIntstatus(dhd->bus->sih->buscorerev), 0, 0), in dhd_pcie_debug_info_dump()
12802 PCIFunctionIntmask(dhd->bus->sih->buscorerev), in dhd_pcie_debug_info_dump()
12803 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12804 PCIFunctionIntmask(dhd->bus->sih->buscorerev), 0, 0), in dhd_pcie_debug_info_dump()
12805 PCIPowerIntstatus(dhd->bus->sih->buscorerev), in dhd_pcie_debug_info_dump()
12806 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12807 PCIPowerIntstatus(dhd->bus->sih->buscorerev), 0, 0), in dhd_pcie_debug_info_dump()
12808 PCIPowerIntmask(dhd->bus->sih->buscorerev), in dhd_pcie_debug_info_dump()
12809 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12810 PCIPowerIntmask(dhd->bus->sih->buscorerev), 0, 0))); in dhd_pcie_debug_info_dump()
12814 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12817 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12820 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12823 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12827 si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, in dhd_pcie_debug_info_dump()
12840 dhd_bus_force_bt_quiesce_enabled(struct dhd_bus *bus) in dhd_bus_force_bt_quiesce_enabled() argument
12842 return bus->force_bt_quiesce; in dhd_bus_force_bt_quiesce_enabled()
12847 dhd_bus_get_hp2p_ring_max_size(struct dhd_bus *bus, bool tx) in dhd_bus_get_hp2p_ring_max_size() argument
12850 return bus->hp2p_txcpl_max_items; in dhd_bus_get_hp2p_ring_max_size()
12852 return bus->hp2p_rxcpl_max_items; in dhd_bus_get_hp2p_ring_max_size()
12856 dhd_bus_set_hp2p_ring_max_size(struct dhd_bus *bus, bool tx, uint16 val) in dhd_bus_set_hp2p_ring_max_size() argument
12859 bus->hp2p_txcpl_max_items = val; in dhd_bus_set_hp2p_ring_max_size()
12861 bus->hp2p_rxcpl_max_items = val; in dhd_bus_set_hp2p_ring_max_size()
12867 dhd_bus_tcm_test(struct dhd_bus *bus) in dhd_bus_tcm_test() argument
12880 if (!bus) { in dhd_bus_tcm_test()
12881 DHD_ERROR(("%s: bus is NULL !\n", __FUNCTION__)); in dhd_bus_tcm_test()
12885 read_buf = MALLOCZ(bus->dhd->osh, MEMBLOCK); in dhd_bus_tcm_test()
12892 write_buf = MALLOCZ(bus->dhd->osh, MEMBLOCK); in dhd_bus_tcm_test()
12895 MFREE(bus->dhd->osh, read_buf, MEMBLOCK); in dhd_bus_tcm_test()
12900 DHD_ERROR(("%s: start %x, size: %x\n", __FUNCTION__, bus->dongle_ram_base, bus->ramsize)); in dhd_bus_tcm_test()
12904 start = bus->dongle_ram_base; in dhd_bus_tcm_test()
12906 size = bus->ramsize; in dhd_bus_tcm_test()
12914 if ((ret = dhdpcie_bus_membytes(bus, TRUE, start, write_buf, read_size))) { in dhd_bus_tcm_test()
12916 MFREE(bus->dhd->osh, read_buf, MEMBLOCK); in dhd_bus_tcm_test()
12917 MFREE(bus->dhd->osh, write_buf, MEMBLOCK); in dhd_bus_tcm_test()
12922 if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, read_buf, read_size))) { in dhd_bus_tcm_test()
12924 MFREE(bus->dhd->osh, read_buf, MEMBLOCK); in dhd_bus_tcm_test()
12925 MFREE(bus->dhd->osh, write_buf, MEMBLOCK); in dhd_bus_tcm_test()
12935 MFREE(bus->dhd->osh, read_buf, MEMBLOCK); in dhd_bus_tcm_test()
12936 MFREE(bus->dhd->osh, write_buf, MEMBLOCK); in dhd_bus_tcm_test()
12947 MFREE(bus->dhd->osh, read_buf, MEMBLOCK); in dhd_bus_tcm_test()
12948 MFREE(bus->dhd->osh, write_buf, MEMBLOCK); in dhd_bus_tcm_test()