Lines Matching defs:dhd_prot
443 typedef struct dhd_prot { struct
444 osl_t *osh; /* OSL handle */
445 uint16 rxbufpost_sz;
446 uint16 rxbufpost;
447 uint16 max_rxbufpost;
448 uint16 max_eventbufpost;
449 uint16 max_ioctlrespbufpost;
450 uint16 max_tsbufpost;
451 uint16 max_infobufpost;
452 uint16 infobufpost;
453 uint16 cur_event_bufs_posted;
454 uint16 cur_ioctlresp_bufs_posted;
455 uint16 cur_ts_bufs_posted;
458 osl_atomic_t active_tx_count; /* increments/decrements on every packet tx/tx_status */
459 uint16 h2d_max_txpost;
460 uint16 txp_threshold; /* optimization to write "n" tx items at a time to ring */
463 msgbuf_ring_t h2dring_ctrl_subn; /* H2D ctrl message submission ring */
464 msgbuf_ring_t h2dring_rxp_subn; /* H2D RxBuf post ring */
465 msgbuf_ring_t d2hring_ctrl_cpln; /* D2H ctrl completion ring */
466 msgbuf_ring_t d2hring_tx_cpln; /* D2H Tx complete message ring */
467 msgbuf_ring_t d2hring_rx_cpln; /* D2H Rx complete message ring */
468 msgbuf_ring_t *h2dring_info_subn; /* H2D info submission ring */
469 msgbuf_ring_t *d2hring_info_cpln; /* D2H info completion ring */
470 msgbuf_ring_t *d2hring_edl; /* D2H Enhanced Debug Lane (EDL) ring */
472 msgbuf_ring_t *h2d_flowrings_pool; /* Pool of preallocated flowings */
473 dhd_dma_buf_t flowrings_dma_buf; /* Contiguous DMA buffer for flowrings */
474 uint16 h2d_rings_total; /* total H2D (common rings + flowrings) */
476 uint32 rx_dataoffset;
478 dhd_mb_ring_t mb_ring_fn; /* called when dongle needs to be notified of new msg */
479 dhd_mb_ring_2_t mb_2_ring_fn; /* called when dongle needs to be notified of new msg */
482 uint8 ioctl_state;
483 int16 ioctl_status; /* status returned from dongle */
484 uint16 ioctl_resplen;
485 dhd_ioctl_recieved_status_t ioctl_received;
486 uint curr_ioctl_cmd;
487 dhd_dma_buf_t retbuf; /* For holding ioctl response */
488 dhd_dma_buf_t ioctbuf; /* For holding ioctl request */
490 dhd_dma_buf_t d2h_dma_scratch_buf; /* For holding d2h scratch */
493 uint32 rw_index_sz; /* Size of a RD or WR index in dongle */
494 dhd_dma_buf_t h2d_dma_indx_wr_buf; /* Array of H2D WR indices */
495 dhd_dma_buf_t h2d_dma_indx_rd_buf; /* Array of H2D RD indices */
496 dhd_dma_buf_t d2h_dma_indx_wr_buf; /* Array of D2H WR indices */
497 dhd_dma_buf_t d2h_dma_indx_rd_buf; /* Array of D2H RD indices */
498 dhd_dma_buf_t h2d_ifrm_indx_wr_buf; /* Array of H2D WR indices for ifrm */
500 dhd_dma_buf_t host_bus_throughput_buf; /* bus throughput measure buffer */
502 dhd_dma_buf_t *flowring_buf; /* pool of flow ring buf */
503 uint32 flowring_num;
505 d2h_sync_cb_t d2h_sync_cb; /* Sync on D2H DMA done: SEQNUM or XORCSUM */
507 d2h_edl_sync_cb_t d2h_edl_sync_cb; /* Sync on EDL D2H DMA done: SEQNUM or XORCSUM */
509 ulong d2h_sync_wait_max; /* max number of wait loops to receive one msg */
510 ulong d2h_sync_wait_tot; /* total wait loops */
512 dhd_dmaxfer_t dmaxfer; /* for test/DMA loopback */
514 uint16 ioctl_seq_no;
515 uint16 data_seq_no;
516 uint16 ioctl_trans_id;
517 void *pktid_ctrl_map; /* a pktid maps to a packet and its metadata */
518 void *pktid_rx_map; /* pktid map for rx path */
519 void *pktid_tx_map; /* pktid map for tx path */
520 bool metadata_dbg;
521 void *pktid_map_handle_ioctl;
523 void *pktid_dma_map; /* pktid map for DMA MAP */
524 void *pktid_dma_unmap; /* pktid map for DMA UNMAP */
526 uint32 pktid_depleted_cnt; /* pktid depleted count */
528 uint8 pktid_txq_stop_cnt;
530 uint8 pktid_txq_start_cnt;
531 uint64 ioctl_fillup_time; /* timestamp for ioctl fillup */
532 uint64 ioctl_ack_time; /* timestamp for ioctl ack */
533 uint64 ioctl_cmplt_time; /* timestamp for ioctl completion */
536 uint16 rx_metadata_offset;
537 uint16 tx_metadata_offset;
541 bcmpcie_soft_doorbell_t soft_doorbell[BCMPCIE_D2H_COMMON_MSGRINGS];
548 uint32 tx_compl_prod_sync ____cacheline_aligned;
549 bcm_workq_t tx_compl_prod, tx_compl_cons;
574 } dhd_prot_t; argument