876 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in ai_corereg()  argument
887 	ASSERT(regoff < SI_CORE_SIZE);  in ai_corereg()
902 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg()
911 			               PCI_16KB0_CCREGS_OFFSET + regoff);  in ai_corereg()
919 				               PCI_16KB0_PCIREGS_OFFSET + regoff);  in ai_corereg()
922 				               ((regoff >= SBCONFIGOFF) ?  in ai_corereg()
924 				               regoff);  in ai_corereg()
936 		               regoff);  in ai_corereg()
970 ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in ai_corereg_writeonly()  argument
981 	ASSERT(regoff < SI_CORE_SIZE);  in ai_corereg_writeonly()
996 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg_writeonly()
1005 			               PCI_16KB0_CCREGS_OFFSET + regoff);  in ai_corereg_writeonly()
1013 				               PCI_16KB0_PCIREGS_OFFSET + regoff);  in ai_corereg_writeonly()
1016 				               ((regoff >= SBCONFIGOFF) ?  in ai_corereg_writeonly()
1018 				               regoff);  in ai_corereg_writeonly()
1030 		               regoff);  in ai_corereg_writeonly()
1061 ai_corereg_addr(si_t *sih, uint coreidx, uint regoff)  in ai_corereg_addr()  argument
1069 	ASSERT(regoff < SI_CORE_SIZE);  in ai_corereg_addr()
1083 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg_addr()
1092 			               PCI_16KB0_CCREGS_OFFSET + regoff);  in ai_corereg_addr()
1100 				               PCI_16KB0_PCIREGS_OFFSET + regoff);  in ai_corereg_addr()
1103 				               ((regoff >= SBCONFIGOFF) ?  in ai_corereg_addr()
1105 				               regoff);  in ai_corereg_addr()
1111 		r = (volatile uint32*) ((volatile uchar*)sii->curmap + regoff);  in ai_corereg_addr()