51 static bool ai_get_apb_bridge(si_t *sih, uint32 coreidx, uint32 *apb_id, uint32 *apb_coreuinit);
471 _ai_setcoreidx(si_t *sih, uint coreidx, uint use_wrapn)  in _ai_setcoreidx()  argument
478 	if (coreidx >= MIN(sii->numcores, SI_MAXCORES))  in _ai_setcoreidx()
481 	addr = cores_info->coresba[coreidx];  in _ai_setcoreidx()
482 	wrap = cores_info->wrapba[coreidx];  in _ai_setcoreidx()
483 	wrap2 = cores_info->wrapba2[coreidx];  in _ai_setcoreidx()
484 	wrap3 = cores_info->wrapba3[coreidx];  in _ai_setcoreidx()
488 	if ((cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID) &&  in _ai_setcoreidx()
503 		if (!cores_info->regs[coreidx]) {  in _ai_setcoreidx()
504 			cores_info->regs[coreidx] = REG_MAP(addr,  in _ai_setcoreidx()
505 				AI_SETCOREIDX_MAPSIZE(cores_info->coreid[coreidx]));  in _ai_setcoreidx()
506 			ASSERT(GOODREGS(cores_info->regs[coreidx]));  in _ai_setcoreidx()
508 		sii->curmap = regs = cores_info->regs[coreidx];  in _ai_setcoreidx()
509 		if (!cores_info->wrappers[coreidx] && (wrap != 0)) {  in _ai_setcoreidx()
510 			cores_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);  in _ai_setcoreidx()
511 			ASSERT(GOODREGS(cores_info->wrappers[coreidx]));  in _ai_setcoreidx()
513 		if (!cores_info->wrappers2[coreidx] && (wrap2 != 0)) {  in _ai_setcoreidx()
514 			cores_info->wrappers2[coreidx] = REG_MAP(wrap2, SI_CORE_SIZE);  in _ai_setcoreidx()
515 			ASSERT(GOODREGS(cores_info->wrappers2[coreidx]));  in _ai_setcoreidx()
517 		if (!cores_info->wrappers3[coreidx] && (wrap3 != 0)) {  in _ai_setcoreidx()
518 			cores_info->wrappers3[coreidx] = REG_MAP(wrap3, SI_CORE_SIZE);  in _ai_setcoreidx()
519 			ASSERT(GOODREGS(cores_info->wrappers3[coreidx]));  in _ai_setcoreidx()
523 			sii->curwrap = cores_info->wrappers3[coreidx];  in _ai_setcoreidx()
525 			sii->curwrap = cores_info->wrappers2[coreidx];  in _ai_setcoreidx()
527 			sii->curwrap = cores_info->wrappers[coreidx];  in _ai_setcoreidx()
536 		if (cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID)  in _ai_setcoreidx()
572 	sii->curidx = coreidx;  in _ai_setcoreidx()
578 ai_setcoreidx(si_t *sih, uint coreidx)  in ai_setcoreidx()  argument
580 	return _ai_setcoreidx(sih, coreidx, 0);  in ai_setcoreidx()
584 ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx)  in ai_setcoreidx_2ndwrap()  argument
586 	return _ai_setcoreidx(sih, coreidx, 1);  in ai_setcoreidx_2ndwrap()
590 ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx)  in ai_setcoreidx_3rdwrap()  argument
592 	return _ai_setcoreidx(sih, coreidx, 2);  in ai_setcoreidx_3rdwrap()
876 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in ai_corereg()  argument
886 	ASSERT(GOODIDX(coreidx));  in ai_corereg()
890 	if (coreidx >= SI_MAXCORES)  in ai_corereg()
897 		if (!cores_info->regs[coreidx]) {  in ai_corereg()
898 			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],  in ai_corereg()
900 			ASSERT(GOODREGS(cores_info->regs[coreidx]));  in ai_corereg()
902 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg()
906 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in ai_corereg()
912 		} else if (sii->pub.buscoreidx == coreidx) {  in ai_corereg()
935 		r = (volatile uint32*) ((volatile uchar*) ai_setcoreidx(&sii->pub, coreidx) +  in ai_corereg()
951 		if (origidx != coreidx)  in ai_corereg()
970 ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in ai_corereg_writeonly()  argument
980 	ASSERT(GOODIDX(coreidx));  in ai_corereg_writeonly()
984 	if (coreidx >= SI_MAXCORES)  in ai_corereg_writeonly()
991 		if (!cores_info->regs[coreidx]) {  in ai_corereg_writeonly()
992 			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],  in ai_corereg_writeonly()
994 			ASSERT(GOODREGS(cores_info->regs[coreidx]));  in ai_corereg_writeonly()
996 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg_writeonly()
1000 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in ai_corereg_writeonly()
1006 		} else if (sii->pub.buscoreidx == coreidx) {  in ai_corereg_writeonly()
1029 		r = (volatile uint32*) ((volatile uchar*) ai_setcoreidx(&sii->pub, coreidx) +  in ai_corereg_writeonly()
1042 		if (origidx != coreidx)  in ai_corereg_writeonly()
1061 ai_corereg_addr(si_t *sih, uint coreidx, uint regoff)  in ai_corereg_addr()  argument
1068 	ASSERT(GOODIDX(coreidx));  in ai_corereg_addr()
1071 	if (coreidx >= SI_MAXCORES)  in ai_corereg_addr()
1078 		if (!cores_info->regs[coreidx]) {  in ai_corereg_addr()
1079 			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],  in ai_corereg_addr()
1081 			ASSERT(GOODREGS(cores_info->regs[coreidx]));  in ai_corereg_addr()
1083 		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);  in ai_corereg_addr()
1087 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in ai_corereg_addr()
1093 		} else if (sii->pub.buscoreidx == coreidx) {  in ai_corereg_addr()
1110 		ASSERT(sii->curidx == coreidx);  in ai_corereg_addr()
1625 ai_get_apb_bridge(si_t * sih, uint32 coreidx, uint32 *apb_id, uint32 * apb_coreuinit)  in ai_get_apb_bridge()  argument
1634 	if (coreidx >= MIN(sii->numcores, SI_MAXCORES))  in ai_get_apb_bridge()
1640 	if (coreidx_cached == coreidx) {  in ai_get_apb_bridge()
1646 	core_base = cores_info->coresba[coreidx];  in ai_get_apb_bridge()
1647 	core_end = core_base + cores_info->coresba_size[coreidx];  in ai_get_apb_bridge()
1662 				coreidx_cached = coreidx;  in ai_get_apb_bridge()
2035 ai_num_slaveports(si_t *sih, uint coreidx)  in ai_num_slaveports()  argument
2041 	cib = cores_info->cib[coreidx];  in ai_num_slaveports()