Lines Matching refs:cfg_reg
1353 uint32 cfg_reg = 0; in ai_dumpregs() local
1361 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_dumpregs()
1364 cfg_reg = PCI_BAR0_WIN2; in ai_dumpregs()
1368 prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4); in ai_dumpregs()
1384 cfg_reg, 4, axi_wrapper[i].wrapper_addr); in ai_dumpregs()
1435 if (prev_value && cfg_reg) { in ai_dumpregs()
1436 OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value); in ai_dumpregs()
1456 uint32 cfg_reg = 0; in ai_update_backplane_timeouts() local
1475 cfg_reg = PCI_BAR0_WIN2; in ai_update_backplane_timeouts()
1478 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_update_backplane_timeouts()
1485 prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4); in ai_update_backplane_timeouts()
1512 cfg_reg, 4, axi_wrapper[i].wrapper_addr); in ai_update_backplane_timeouts()
1535 OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value); in ai_update_backplane_timeouts()
1941 uint32 cfg_reg = 0; in ai_clear_backplane_to() local
1959 cfg_reg = PCI_BAR0_WIN2; in ai_clear_backplane_to()
1962 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_clear_backplane_to()
1969 prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4); in ai_clear_backplane_to()
1980 axi_error->errlog_lo = cfg_reg; in ai_clear_backplane_to()
2005 cfg_reg, 4, axi_wrapper[i].wrapper_addr); in ai_clear_backplane_to()
2025 OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value); in ai_clear_backplane_to()