Lines Matching refs:SI_VMSG
101 SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent)); in get_erom_ent()
103 SI_VMSG((" after %d invalid and %d non-matching entries\n", inv, nom)); in get_erom_ent()
139 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n", in get_asd()
189 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", in ai_scan()
203 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores)); in ai_scan()
223 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " in ai_scan()
283 SI_VMSG((" Master port %d, mp: %d id: %d\n", i, in ai_scan()
378 SI_VMSG(("MASTER WRAPPER: %d, mfg:%x, cid:%x," in ai_scan()
441 SI_VMSG(("SLAVE WRAPPER: %d, mfg:%x, cid:%x," in ai_scan()
1465 SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n", in ai_update_backplane_timeouts()
1496 SI_VMSG(("SKIP ENABLE BPT: MFG:%x, CID:%x, ADDR:%x\n", in ai_update_backplane_timeouts()
1525 SI_VMSG(("ENABLED BPT: MFG:%x, CID:%x, ADDR:%x, ERR_CTRL:%x\n", in ai_update_backplane_timeouts()
1744 SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n", in ai_clear_backplane_to_per_core()
1949 SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n", in ai_clear_backplane_to()