Lines Matching refs:sii
149 static int32 BCMATTACHFN(si_alloc_wrapper)(si_info_t *sii);
150 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs,
152 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
153 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
157 static void si_nvram_process(si_info_t *sii, char *pvars);
162 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
163 static bool si_ispcie(const si_info_t *sii);
164 static uint sysmem_banksize(const si_info_t *sii, sysmemregs_t *r, uint8 idx);
165 static uint socram_banksize(const si_info_t *sii, sbsocramregs_t *r, uint8 idx, uint8 mtype);
276 si_info_t *sii; in BCMATTACHFN() local
280 if ((sii = MALLOCZ_NOPERSIST(osh, sizeof(si_info_t))) == NULL) { in BCMATTACHFN()
286 if (BCMDVFS_ENAB() && si_dvfs_info_init((si_t *)sii, osh) == NULL) { in BCMATTACHFN()
292 if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) { in BCMATTACHFN()
293 MFREE(osh, sii, sizeof(si_info_t)); in BCMATTACHFN()
296 sii->vars = vars ? *vars : NULL; in BCMATTACHFN()
297 sii->varsz = varsz ? *varsz : 0; in BCMATTACHFN()
300 sh_sflash_attach(osh, (si_t *)sii); in BCMATTACHFN()
302 return (si_t *)sii; in BCMATTACHFN()
362 BCMATTACHFN(si_buscore_prep)(si_info_t *sii, uint bustype, uint devid, void *sdh) in BCMATTACHFN()
369 if (BUSTYPE(bustype) == PCI_BUS && !si_ispcie(sii)) in BCMATTACHFN()
370 si_clkctl_xtal(&sii->pub, XTAL|PLL, ON); in BCMATTACHFN()
446 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr() local
451 if (!(sii->pub.cccaps & CC_CAP_PMU)) { in si_get_pmu_reg_addr()
454 if (AOB_ENAB(&sii->pub)) { in si_get_pmu_reg_addr()
458 origidx = sii->curidx; in si_get_pmu_reg_addr()
459 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in si_get_pmu_reg_addr()
460 pmu = si_setcoreidx(&sii->pub, pmucoreidx); in si_get_pmu_reg_addr()
475 BCMATTACHFN(si_buscore_setup)(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin, in BCMATTACHFN()
478 const si_cores_info_t *cores_info = sii->cores_info; in BCMATTACHFN()
485 si_slave_wrapper_add(&sii->pub); in BCMATTACHFN()
487 sii->curidx = 0; in BCMATTACHFN()
489 cc = si_setcoreidx(&sii->pub, SI_CC_IDX); in BCMATTACHFN()
493 sii->pub.ccrev = (int)si_corerev(&sii->pub); in BCMATTACHFN()
496 if (CCREV(sii->pub.ccrev) >= 11) in BCMATTACHFN()
497 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus); in BCMATTACHFN()
500 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); in BCMATTACHFN()
503 if (CCREV(sii->pub.ccrev) >= 35) /* PR77565 */ in BCMATTACHFN()
504 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); in BCMATTACHFN()
507 if (sii->pub.cccaps & CC_CAP_PMU) { in BCMATTACHFN()
508 if (AOB_ENAB(&sii->pub)) { in BCMATTACHFN()
512 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in BCMATTACHFN()
513 if (!GOODIDX(pmucoreidx, sii->numcores)) { in BCMATTACHFN()
518 pmu = si_setcoreidx(&sii->pub, pmucoreidx); in BCMATTACHFN()
519 sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities); in BCMATTACHFN()
520 si_setcoreidx(&sii->pub, SI_CC_IDX); in BCMATTACHFN()
522 sii->pub.gcirev = si_corereg(&sii->pub, GCI_CORE_IDX(&sii->pub), in BCMATTACHFN()
523 GCI_OFFSETOF(&sii->pub, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK; in BCMATTACHFN()
525 if (GCIREV(sii->pub.gcirev) >= 9) { in BCMATTACHFN()
526 sii->pub.lhlrev = si_corereg(&sii->pub, GCI_CORE_IDX(&sii->pub), in BCMATTACHFN()
530 sii->pub.lhlrev = NOREV; in BCMATTACHFN()
534 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); in BCMATTACHFN()
536 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; in BCMATTACHFN()
540 CCREV(sii->pub.ccrev), sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev, in BCMATTACHFN()
541 sii->pub.pmucaps)); in BCMATTACHFN()
545 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) { in BCMATTACHFN()
546 sii->pub.buscoretype = NODEV_CORE_ID; in BCMATTACHFN()
548 sii->pub.buscorerev = NOREV; in BCMATTACHFN()
549 sii->pub.buscoreidx = BADIDX; in BCMATTACHFN()
556 for (i = 0; i < sii->numcores; i++) { in BCMATTACHFN()
559 si_setcoreidx(&sii->pub, i); in BCMATTACHFN()
560 cid = si_coreid(&sii->pub); in BCMATTACHFN()
561 crev = si_corerev(&sii->pub); in BCMATTACHFN()
564 if (CHIPTYPE(sii->pub.socitype) != SOCI_NCI) { in BCMATTACHFN()
602 sii->pub.buscorerev = (int16)crev; in BCMATTACHFN()
603 sii->pub.buscoretype = (uint16)cid; in BCMATTACHFN()
604 sii->pub.buscoreidx = (uint16)i; in BCMATTACHFN()
609 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
610 if (regs == sii->curmap) { in BCMATTACHFN()
624 if (si_ispcie(sii)) in BCMATTACHFN()
634 sii->pub.buscoretype = PCIE2_CORE_ID; in BCMATTACHFN()
636 sii->pub.buscoretype = PCIE_CORE_ID; in BCMATTACHFN()
637 sii->pub.buscorerev = (int16)pcierev; in BCMATTACHFN()
638 sii->pub.buscoreidx = (uint16)pcieidx; in BCMATTACHFN()
645 sii->pub.buscoretype = PCI_CORE_ID; in BCMATTACHFN()
646 sii->pub.buscorerev = (int16)pcirev; in BCMATTACHFN()
647 sii->pub.buscoreidx = (uint16)pciidx; in BCMATTACHFN()
650 sii->pub.buscoretype = PCIE2_CORE_ID; in BCMATTACHFN()
652 sii->pub.buscoretype = PCIE_CORE_ID; in BCMATTACHFN()
653 sii->pub.buscorerev = (int16)pcierev; in BCMATTACHFN()
654 sii->pub.buscoreidx = (uint16)pcieidx; in BCMATTACHFN()
658 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype, in BCMATTACHFN()
659 sii->pub.buscorerev)); in BCMATTACHFN()
663 if (!FWSIGN_ENAB() && BUSTYPE(sii->pub.bustype) == PCI_BUS) { in BCMATTACHFN()
664 if (SI_FAST(sii)) { in BCMATTACHFN()
665 if (!sii->pch && in BCMATTACHFN()
666 ((sii->pch = (void *)(uintptr)pcicore_init(&sii->pub, sii->osh, in BCMATTACHFN()
667 (volatile void *)PCIEREGS(sii))) == NULL)) in BCMATTACHFN()
670 if (si_pci_fixcfg(&sii->pub)) { in BCMATTACHFN()
682 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || in BCMATTACHFN()
683 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) in BCMATTACHFN()
684 si_core_disable(&sii->pub, 0); in BCMATTACHFN()
689 si_setcoreidx(&sii->pub, *origidx); in BCMATTACHFN()
725 BCMATTACHFN(si_fixup_vid_overrides)(si_info_t *sii, char *pvars, uint32 conf_vid) in BCMATTACHFN()
729 if ((sii->pub.boardvendor != VENDOR_APPLE)) { in BCMATTACHFN()
733 switch (sii->pub.boardtype) in BCMATTACHFN()
743 sii->pub.boardtype = (conf_vid >> 16) & 0xffff; in BCMATTACHFN()
755 BCMATTACHFN(si_nvram_process)(si_info_t *sii, char *pvars) in BCMATTACHFN()
764 switch (BUSTYPE(sii->pub.bustype)) { in BCMATTACHFN()
767 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); in BCMATTACHFN()
770 if ((sii->pub.boardvendor = (uint16)si_getdevpathintvar(&sii->pub, in BCMATTACHFN()
774 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
777 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
780 sii->pub.boardvendor, w & 0xffff)); in BCMATTACHFN()
783 if ((sii->pub.boardtype = (uint16)si_getdevpathintvar(&sii->pub, rstr_boardtype)) in BCMATTACHFN()
785 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
786 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
789 sii->pub.boardtype, (w >> 16) & 0xffff)); in BCMATTACHFN()
794 si_fixup_vid_overrides(sii, pvars, w); in BCMATTACHFN()
800 sii->pub.boardvendor = getintvar(pvars, rstr_manfid); in BCMATTACHFN()
801 sii->pub.boardtype = getintvar(pvars, rstr_prodid); in BCMATTACHFN()
805 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
806 sii->pub.boardtype = QT4710_BOARD; in BCMATTACHFN()
812 if (BCMPCIEDEV_ENAB() && si_is_sprom_available(&sii->pub) && pvars && in BCMATTACHFN()
814 sii->pub.boardvendor = getintvar(pvars, rstr_subvid); in BCMATTACHFN()
817 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
818 if (pvars == NULL || ((sii->pub.boardtype = getintvar(pvars, rstr_prodid)) == 0)) in BCMATTACHFN()
819 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
820 sii->pub.boardtype = 0xffff; in BCMATTACHFN()
822 if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) { in BCMATTACHFN()
824 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); in BCMATTACHFN()
825 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
826 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
834 if (sii->pub.boardtype == 0) { in BCMATTACHFN()
836 ASSERT(sii->pub.boardtype); in BCMATTACHFN()
839 sii->pub.lpflags = getintvar(pvars, rstr_lpflags); in BCMATTACHFN()
840 sii->pub.boardrev = getintvar(pvars, rstr_boardrev); in BCMATTACHFN()
841 sii->pub.boardflags = getintvar(pvars, rstr_boardflags); in BCMATTACHFN()
844 sii->pub.boardflags2 |= ((!CHIP_HOSTIF_USB(&(sii->pub))) ? ((si_arm_sflags(&(sii->pub)) in BCMATTACHFN()
848 sii->pub.boardflags4 = getintvar(pvars, rstr_boardflags4); in BCMATTACHFN()
1483 si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
1488 sii->device_wake_opt = (uint8)getintvar(NULL, rstr_device_wake_opt); in BCMINITFN()
1489 return sii->device_wake_opt; in BCMINITFN()
1497 const si_info_t *sii = SI_INFO(sih); in si_enable_device_wake() local
1499 device_wake_opt = sii->device_wake_opt; in si_enable_device_wake()
1562 si_info_t *sii; in si_gci_gpioint_handler_unregister() local
1565 sii = SI_INFO(sih); in si_gci_gpioint_handler_unregister()
1569 sii = SI_INFO(sih); in si_gci_gpioint_handler_unregister()
1575 ASSERT(sii->gci_gpio_head != NULL); in si_gci_gpioint_handler_unregister()
1577 if ((void*)sii->gci_gpio_head == gci_i) { in si_gci_gpioint_handler_unregister()
1578 sii->gci_gpio_head = sii->gci_gpio_head->next; in si_gci_gpioint_handler_unregister()
1579 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t)); in si_gci_gpioint_handler_unregister()
1582 p = sii->gci_gpio_head; in si_gci_gpioint_handler_unregister()
1587 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t)); in si_gci_gpioint_handler_unregister()
1600 si_info_t *sii; in si_gci_gpioint_handler_register() local
1603 sii = SI_INFO(sih); in si_gci_gpioint_handler_register()
1607 sii = SI_INFO(sih); in si_gci_gpioint_handler_register()
1620 gci_i = MALLOC(sii->osh, (sizeof(gci_gpio_item_t))); in si_gci_gpioint_handler_register()
1628 if (sii->gci_gpio_head) in si_gci_gpioint_handler_register()
1629 gci_i->next = sii->gci_gpio_head; in si_gci_gpioint_handler_register()
1633 sii->gci_gpio_head = gci_i; in si_gci_gpioint_handler_register()
1646 si_info_t *sii; in si_gci_gpioint_handler_process() local
1650 sii = SI_INFO(sih); in si_gci_gpioint_handler_process()
1671 gci_i = sii->gci_gpio_head; in si_gci_gpioint_handler_process()
1803 si_info_t *sii; in si_wci2_rxfifo_handler_register() local
1806 sii = SI_INFO(sih); in si_wci2_rxfifo_handler_register()
1815 if ((wci2_info = (wci2_rxfifo_info_t *)MALLOCZ(sii->osh, in si_wci2_rxfifo_handler_register()
1821 if ((wci2_info->rx_buf = (char *)MALLOCZ(sii->osh, WCI2_UART_RX_BUF_SIZE)) == NULL) { in si_wci2_rxfifo_handler_register()
1822 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_register()
1828 if ((wci2_info->cbs = (wci2_cbs_t *)MALLOCZ(sii->osh, sizeof(wci2_cbs_t))) == NULL) { in si_wci2_rxfifo_handler_register()
1829 MFREE(sii->osh, wci2_info->rx_buf, WCI2_UART_RX_BUF_SIZE); in si_wci2_rxfifo_handler_register()
1830 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_register()
1836 sii->wci2_info = wci2_info; in si_wci2_rxfifo_handler_register()
1849 si_info_t *sii; in si_wci2_rxfifo_handler_unregister() local
1852 sii = SI_INFO(sih); in si_wci2_rxfifo_handler_unregister()
1853 ASSERT(sii); in si_wci2_rxfifo_handler_unregister()
1860 wci2_info = sii->wci2_info; in si_wci2_rxfifo_handler_unregister()
1867 MFREE(sii->osh, wci2_info->rx_buf, WCI2_UART_RX_BUF_SIZE); in si_wci2_rxfifo_handler_unregister()
1871 MFREE(sii->osh, wci2_info->cbs, sizeof(wci2_cbs_t)); in si_wci2_rxfifo_handler_unregister()
1874 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_unregister()
1882 const si_info_t *sii = SI_INFO(sih); in si_wci2_rxfifo_intr_handler_process() local
1888 wci2_info = sii->wci2_info; in si_wci2_rxfifo_intr_handler_process()
2551 const si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
2553 return (sii->chipnew) ? sii->chipnew : sih->chip; in BCMINITFN()
2560 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
2562 ASSERT(sii->chipnew == 0); in BCMATTACHFN()
2565 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2566 sii->pub.chip = BCM4369_CHIP_ID; /* chip class */ in BCMATTACHFN()
2569 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2570 sii->pub.chip = BCM4375_CHIP_ID; /* chip class */ in BCMATTACHFN()
2573 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2574 sii->pub.chip = BCM4362_CHIP_ID; /* chip class */ in BCMATTACHFN()
2578 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2579 sii->pub.chip = BCM4354_CHIP_ID; /* chip class */ in BCMATTACHFN()
2620 BCMATTACHFN(si_alloc_wrapper)(si_info_t *sii) in BCMATTACHFN()
2622 if (sii->osh) { in BCMATTACHFN()
2623 sii->axi_wrapper = (axi_wrapper_t *)MALLOCZ(sii->osh, in BCMATTACHFN()
2626 if (sii->axi_wrapper == NULL) { in BCMATTACHFN()
2630 sii->axi_wrapper = NULL; in BCMATTACHFN()
2637 BCMATTACHFN(si_free_wrapper)(si_info_t *sii) in BCMATTACHFN()
2639 if (sii->axi_wrapper) { in BCMATTACHFN()
2641 MFREE(sii->osh, sii->axi_wrapper, (sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS)); in BCMATTACHFN()
2646 BCMATTACHFN(si_alloc_coresinfo)(si_info_t *sii, osl_t *osh, chipcregs_t *cc) in BCMATTACHFN()
2648 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2649 sii->nci_info = nci_init(&sii->pub, (void*)(uintptr)cc, sii->pub.bustype); in BCMATTACHFN()
2651 return sii->nci_info; in BCMATTACHFN()
2656 sii->cores_info = (si_cores_info_t *)&ksii_cores_info; in BCMATTACHFN()
2658 if (sii->cores_info == NULL) { in BCMATTACHFN()
2660 if ((sii->cores_info = (si_cores_info_t *)MALLOCZ(osh, in BCMATTACHFN()
2667 ASSERT(sii->cores_info == &ksii_cores_info); in BCMATTACHFN()
2671 return sii->cores_info; in BCMATTACHFN()
2677 BCMATTACHFN(si_free_coresinfo)(si_info_t *sii, osl_t *osh) in BCMATTACHFN()
2680 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2681 if (sii->nci_info) { in BCMATTACHFN()
2682 nci_uninit(sii->nci_info); in BCMATTACHFN()
2683 sii->nci_info = NULL; in BCMATTACHFN()
2686 if (sii->cores_info && (sii->cores_info != &ksii_cores_info)) { in BCMATTACHFN()
2687 MFREE(osh, sii->cores_info, sizeof(si_cores_info_t)); in BCMATTACHFN()
2700 BCMATTACHFN(si_doattach)(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs, in BCMATTACHFN()
2703 struct si_pub *sih = &sii->pub; in BCMATTACHFN()
2718 sii->device_removed = FALSE; in BCMATTACHFN()
2720 sii->curmap = regs; in BCMATTACHFN()
2721 sii->sdh = sdh; in BCMATTACHFN()
2722 sii->osh = osh; in BCMATTACHFN()
2723 sii->second_bar0win = ~0x0; in BCMATTACHFN()
2740 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) { in BCMATTACHFN()
2748 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); in BCMATTACHFN()
2752 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih)); in BCMATTACHFN()
2760 cc = (chipcregs_t *)sii->curmap; in BCMATTACHFN()
2777 if (!si_buscore_prep(sii, bustype, devid, sdh)) { in BCMATTACHFN()
2816 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2818 if (si_alloc_coresinfo(sii, osh, cc) == NULL) { in BCMATTACHFN()
2822 ASSERT(sii->nci_info); in BCMATTACHFN()
2825 if ((si_alloc_wrapper(sii)) != BCME_OK) { in BCMATTACHFN()
2831 if ((sii->numcores = nci_scan(sih)) == 0u) { in BCMATTACHFN()
2836 nci_dump_erom(sii->nci_info); in BCMATTACHFN()
2841 if (si_alloc_coresinfo(sii, osh, cc) == NULL) { in BCMATTACHFN()
2846 if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) { in BCMATTACHFN()
2848 sb_scan(&sii->pub, regs, devid); in BCMATTACHFN()
2849 } else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) || in BCMATTACHFN()
2850 (CHIPTYPE(sii->pub.socitype) == SOCI_NAI) || in BCMATTACHFN()
2851 (CHIPTYPE(sii->pub.socitype) == SOCI_DVTBUS)) { in BCMATTACHFN()
2853 if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) in BCMATTACHFN()
2855 else if (CHIPTYPE(sii->pub.socitype) == SOCI_NAI) in BCMATTACHFN()
2860 if ((si_alloc_wrapper(sii)) != BCME_OK) { in BCMATTACHFN()
2864 ai_scan(&sii->pub, (void *)(uintptr)cc, devid); in BCMATTACHFN()
2866 if (sii->axi_num_wrappers == 0) { in BCMATTACHFN()
2872 else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) { in BCMATTACHFN()
2875 ub_scan(&sii->pub, (void *)(uintptr)cc, devid); in BCMATTACHFN()
2883 if (sii->numcores == 0) { in BCMATTACHFN()
2889 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { in BCMATTACHFN()
2920 pcie_disable_TL_clk_gating(sii->pch); in BCMATTACHFN()
2921 pcie_set_L1_entry_time(sii->pch, 0x40); in BCMATTACHFN()
2932 if (CHIP_HOSTIF_PCIE(&(sii->pub))) { in BCMATTACHFN()
2933 uint32 sflags = si_arm_sflags(&(sii->pub)); in BCMATTACHFN()
2953 if (nvram_init(&(sii->pub)) != BCME_OK) { in BCMATTACHFN()
2976 if (srom_var_init(&sii->pub, BUSTYPE(bustype), (void *)regs, in BCMATTACHFN()
2977 sii->osh, &sromvars, varsz)) { in BCMATTACHFN()
2984 if (srom_var_init(&sii->pub, BUSTYPE(bustype), (void *)regs, in BCMATTACHFN()
2985 sii->osh, vars, varsz)) { in BCMATTACHFN()
2996 si_nvram_process(sii, pvars); in BCMATTACHFN()
2999 sii->xtalfreq = getintvar(NULL, rstr_xtalfreq); in BCMATTACHFN()
3013 sii->lhl_ps_mode = (uint8)getintvar(NULL, rstr_lhl_ps_mode); in BCMATTACHFN()
3016 sii->hib_ext_wakeup_enab = FALSE; in BCMATTACHFN()
3019 sii->hib_ext_wakeup_enab = TRUE; in BCMATTACHFN()
3021 sii->hib_ext_wakeup_enab = TRUE; in BCMATTACHFN()
3023 sii->hib_ext_wakeup_enab = FALSE; in BCMATTACHFN()
3027 sii->rfldo3p3_war = (bool)getintvar(NULL, rstr_rfldo3p3_cap_war); in BCMATTACHFN()
3039 sii->min_mask_valid = TRUE; in BCMATTACHFN()
3040 sii->nvram_min_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3042 sii->min_mask_valid = FALSE; in BCMATTACHFN()
3046 sii->max_mask_valid = TRUE; in BCMATTACHFN()
3047 sii->nvram_max_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3049 sii->max_mask_valid = FALSE; in BCMATTACHFN()
3058 sii->armpllclkfreq = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3059 ASSERT(sii->armpllclkfreq > 0); in BCMATTACHFN()
3061 sii->armpllclkfreq = 0; in BCMATTACHFN()
3085 if (CCREV(sii->pub.ccrev) >= 20) { in BCMATTACHFN()
3148 si_pmu_init(sih, sii->osh); in BCMATTACHFN()
3149 si_pmu_chip_init(sih, sii->osh); in BCMATTACHFN()
3175 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); in BCMATTACHFN()
3177 sii->xtalfreq = xtalfreq; in BCMATTACHFN()
3178 si_pmu_pll_init(sih, sii->osh, xtalfreq); in BCMATTACHFN()
3182 sii->spurmode = getintvar(pvars, rstr_spurconfig) & 0xf; in BCMATTACHFN()
3213 si_pmu_res_init(sih, sii->osh); in BCMATTACHFN()
3214 si_pmu_swreg_init(sih, sii->osh); in BCMATTACHFN()
3230 if (PCIE(sii)) { in BCMATTACHFN()
3231 ASSERT(sii->pch != NULL); in BCMATTACHFN()
3232 pcicore_attach(sii->pch, pvars, SI_DOATTACH); in BCMATTACHFN()
3258 si_muxenab((si_t *)sii, w); in BCMATTACHFN()
3264 si_swdenable((si_t *)sii, w); in BCMATTACHFN()
3267 sii->device_wake_opt = CC_GCI_GPIO_INVALID; in BCMATTACHFN()
3278 si_muxenab(sii, 3); in BCMATTACHFN()
3290 return (sii); in BCMATTACHFN()
3295 if (sii->pch) in BCMATTACHFN()
3296 pcicore_deinit(sii->pch); in BCMATTACHFN()
3297 sii->pch = NULL; in BCMATTACHFN()
3303 si_free_coresinfo(sii, osh); in BCMATTACHFN()
3304 si_free_wrapper(sii); in BCMATTACHFN()
3313 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
3314 si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info; in BCMATTACHFN()
3324 sh_sflash_detach(sii->osh, sih); in BCMATTACHFN()
3328 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
3329 if (sii->nci_info) { in BCMATTACHFN()
3330 nci_uninit(sii->nci_info); in BCMATTACHFN()
3331 sii->nci_info = NULL; in BCMATTACHFN()
3352 if (sii->pch) in BCMATTACHFN()
3353 pcicore_deinit(sii->pch); in BCMATTACHFN()
3354 sii->pch = NULL; in BCMATTACHFN()
3358 si_free_coresinfo(sii, sii->osh); in BCMATTACHFN()
3362 MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t)); in BCMATTACHFN()
3363 sii->pub.err_info = NULL; in BCMATTACHFN()
3367 si_free_wrapper(sii); in BCMATTACHFN()
3371 si_dvfs_info_deinit(sih, sii->osh); in BCMATTACHFN()
3375 if (sii != &ksii) { in BCMATTACHFN()
3376 MFREE(sii->osh, sii, sizeof(si_info_t)); in BCMATTACHFN()
3383 const si_info_t *sii; in BCMPOSTTRAPFN() local
3385 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3386 return sii->osh; in BCMPOSTTRAPFN()
3392 si_info_t *sii; in si_setosh() local
3394 sii = SI_INFO(sih); in si_setosh()
3395 if (sii->osh != NULL) { in si_setosh()
3397 ASSERT(!sii->osh); in si_setosh()
3399 sii->osh = osh; in si_setosh()
3407 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
3408 sii->intr_arg = intr_arg; in BCMATTACHFN()
3409 sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn; in BCMATTACHFN()
3410 sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn; in BCMATTACHFN()
3411 sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn; in BCMATTACHFN()
3415 sii->dev_coreid = si_coreid(sih); in BCMATTACHFN()
3421 si_info_t *sii; in BCMPOSTTRAPFN() local
3423 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3424 sii->intrsoff_fn = NULL; in BCMPOSTTRAPFN()
3425 sii->intrsrestore_fn = NULL; in BCMPOSTTRAPFN()
3426 sii->intrsenabled_fn = NULL; in BCMPOSTTRAPFN()
3432 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3439 return R_REG(sii->osh, ((uint32 *)(uintptr) in BCMPOSTTRAPFN()
3440 (sii->oob_router + OOB_STATUSA))); in BCMPOSTTRAPFN()
3503 const si_info_t *sii = SI_INFO(sih); in si_oobr_baseaddr() local
3510 return (second ? sii->oob_router1 : sii->oob_router); in si_oobr_baseaddr()
3522 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3523 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3524 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3525 return nci_coreid(sih, sii->curidx); in BCMPOSTTRAPFN()
3528 return cores_info->coreid[sii->curidx]; in BCMPOSTTRAPFN()
3535 const si_info_t *sii; in BCMPOSTTRAPFN() local
3537 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3538 return sii->curidx; in BCMPOSTTRAPFN()
3544 const si_info_t *sii = SI_INFO(sih); in si_get_num_cores() local
3545 return sii->numcores; in si_get_num_cores()
3558 const si_info_t *sii = SI_INFO(sih); in si_coreunit() local
3559 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_coreunit()
3565 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in si_coreunit()
3571 idx = sii->curidx; in si_coreunit()
3573 ASSERT(GOODREGS(sii->curmap)); in si_coreunit()
3645 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3646 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3656 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3689 const si_info_t *sii = SI_INFO(sih); in si_findcoreid() local
3690 const si_cores_info_t *cores_info = sii->cores_info; in si_findcoreid()
3692 if (coreidx >= sii->numcores) { in si_findcoreid()
3705 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3706 const si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3713 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3736 const si_info_t *sii = SI_INFO(sih); in si_corelist() local
3737 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_corelist()
3742 (void)memcpy_s(coreid, (sii->numcores * sizeof(uint)), cores_info->coreid, in si_corelist()
3743 (sii->numcores * sizeof(uint))); in si_corelist()
3744 return (sii->numcores); in si_corelist()
3751 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3753 ASSERT(GOODREGS(sii->curwrap)); in BCMPOSTTRAPFN()
3755 return (sii->curwrap); in BCMPOSTTRAPFN()
3762 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3764 ASSERT(GOODREGS(sii->curmap)); in BCMPOSTTRAPFN()
3766 return (sii->curmap); in BCMPOSTTRAPFN()
3777 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3781 if (!GOODIDX(idx, sii->numcores)) { in BCMPOSTTRAPFN()
3825 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3827 if (SI_FAST(sii)) { in BCMPOSTTRAPFN()
3834 return (volatile void *)CCREGS_FAST(sii); in BCMPOSTTRAPFN()
3836 return (volatile void *)PCIEREGS(sii); in BCMPOSTTRAPFN()
3838 INTR_OFF(sii, intr_val); in BCMPOSTTRAPFN()
3839 *origidx = sii->curidx; in BCMPOSTTRAPFN()
3850 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
3852 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype)))) in BCMPOSTTRAPFN()
3856 INTR_RESTORE(sii, intr_val); in BCMPOSTTRAPFN()
4113 si_info_t *sii = SI_INFO(sih); in si_invalidate_second_bar0win() local
4114 sii->second_bar0win = ~0x0; in si_invalidate_second_bar0win()
4122 si_info_t *sii = SI_INFO(sih); in si_backplane_access() local
4139 if (sii->second_bar0win != region) { in si_backplane_access()
4140 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region); in si_backplane_access()
4141 sii->second_bar0win = region; in si_backplane_access()
4149 r = (volatile uint32 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr); in si_backplane_access()
4152 (volatile char*)sii->curmap, region, addr, r, read)); in si_backplane_access()
4157 *val = R_REG(sii->osh, (volatile uint8*)r); in si_backplane_access()
4159 W_REG(sii->osh, (volatile uint8*)r, *val); in si_backplane_access()
4163 *val = R_REG(sii->osh, (volatile uint16*)r); in si_backplane_access()
4165 W_REG(sii->osh, (volatile uint16*)r, *val); in si_backplane_access()
4169 *val = R_REG(sii->osh, (volatile uint32*)r); in si_backplane_access()
4171 W_REG(sii->osh, (volatile uint32*)r, *val); in si_backplane_access()
4195 si_info_t *sii = SI_INFO(sih); in si_backplane_access_64()
4214 if (sii->second_bar0win != region) { in si_backplane_access_64()
4215 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region); in si_backplane_access_64()
4216 sii->second_bar0win = region; in si_backplane_access_64()
4224 r = (volatile uint64 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr); in si_backplane_access_64()
4229 *val = R_REG(sii->osh, (volatile uint64*)r); in si_backplane_access_64()
4231 W_REG(sii->osh, (volatile uint64*)r, *val); in si_backplane_access_64()
4409 const si_info_t *sii = SI_INFO(sih); in si_get_slaveport_addr() local
4410 uint origidx = sii->curidx; in si_get_slaveport_addr()
4433 const si_info_t *sii = SI_INFO(sih); in si_get_d11_slaveport_addr() local
4434 uint origidx = sii->curidx; in si_get_d11_slaveport_addr()
4625 const si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
4632 INTR_OFF(sii, &intr_val); in BCMINITFN()
4634 rate = si_pmu_si_clock(sih, sii->osh); in BCMINITFN()
4638 idx = sii->curidx; in BCMINITFN()
4642 n = R_REG(sii->osh, &cc->clockcontrol_n); in BCMINITFN()
4645 m = R_REG(sii->osh, &cc->clockcontrol_m3); in BCMINITFN()
4647 m = R_REG(sii->osh, &cc->clockcontrol_m2); in BCMINITFN()
4649 m = R_REG(sii->osh, &cc->clockcontrol_sb); in BCMINITFN()
4660 INTR_RESTORE(sii, &intr_val); in BCMINITFN()
4783 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
4786 (void) sii; in BCMATTACHFN()
4795 else if ((device = (uint16)getintvar(sii->vars, rstr_devid)) != 0) in BCMATTACHFN()
4798 else if ((device = (uint16)getintvar(sii->vars, rstr_wl0id)) != 0) in BCMATTACHFN()
4960 si_info_t *sii = SI_INFO(sih); in si_dumpregs() local
4964 origidx = sii->curidx; in si_dumpregs()
4966 INTR_OFF(sii, &intr_val); in si_dumpregs()
4981 INTR_RESTORE(sii, &intr_val); in si_dumpregs()
5007 si_info_t *sii = SI_INFO(sih); in si_viewall() local
5011 curidx = sii->curidx; in si_viewall()
5013 INTR_OFF(sii, &intr_val); in si_viewall()
5021 SI_ERROR(("si_viewall: num_cores %d\n", sii->numcores)); in si_viewall()
5022 for (i = 0; i < sii->numcores; i++) { in si_viewall()
5028 INTR_RESTORE(sii, &intr_val); in si_viewall()
5034 si_slowclk_src(si_info_t *sii) in si_slowclk_src() argument
5038 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); in si_slowclk_src()
5040 if (CCREV(sii->pub.ccrev) < 6) { in si_slowclk_src()
5041 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) && in si_slowclk_src()
5042 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) & in si_slowclk_src()
5047 } else if (CCREV(sii->pub.ccrev) < 10) { in si_slowclk_src()
5048 cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx); in si_slowclk_src()
5050 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK); in si_slowclk_src()
5057 si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc) in si_slowclk_freq() argument
5062 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); in si_slowclk_freq()
5065 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); in si_slowclk_freq()
5067 slowclk = si_slowclk_src(sii); in si_slowclk_freq()
5068 if (CCREV(sii->pub.ccrev) < 6) { in si_slowclk_freq()
5073 } else if (CCREV(sii->pub.ccrev) < 10) { in si_slowclk_freq()
5075 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1); in si_slowclk_freq()
5086 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; in si_slowclk_freq()
5094 BCMINITFN(si_clkctl_setdelay)(si_info_t *sii, void *chipcregs) in BCMINITFN()
5106 slowclk = si_slowclk_src(sii); in BCMINITFN()
5111 slowmaxfreq = si_slowclk_freq(sii, (CCREV(sii->pub.ccrev) >= 10) ? FALSE : TRUE, cc); in BCMINITFN()
5116 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay); in BCMINITFN()
5117 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay); in BCMINITFN()
5124 si_info_t *sii; in BCMINITFN() local
5132 sii = SI_INFO(sih); in BCMINITFN()
5133 fast = SI_FAST(sii); in BCMINITFN()
5135 origidx = sii->curidx; in BCMINITFN()
5138 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL) in BCMINITFN()
5144 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK, in BCMINITFN()
5147 si_clkctl_setdelay(sii, (void *)(uintptr)cc); in BCMINITFN()
5161 si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
5170 INTR_OFF(sii, &intr_val); in BCMINITFN()
5171 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh); in BCMINITFN()
5172 INTR_RESTORE(sii, &intr_val); in BCMINITFN()
5179 fast = SI_FAST(sii); in BCMINITFN()
5182 origidx = sii->curidx; in BCMINITFN()
5183 INTR_OFF(sii, &intr_val); in BCMINITFN()
5186 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL) { in BCMINITFN()
5192 slowminfreq = si_slowclk_freq(sii, FALSE, cc); in BCMINITFN()
5194 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) + in BCMINITFN()
5200 INTR_RESTORE(sii, &intr_val); in BCMINITFN()
5209 si_info_t *sii; in si_clkctl_xtal() local
5212 sii = SI_INFO(sih); in si_clkctl_xtal()
5223 if (PCIE(sii) || PCIE_GEN2(sii)) in si_clkctl_xtal()
5226 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32)); in si_clkctl_xtal()
5227 out = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)); in si_clkctl_xtal()
5228 outen = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32)); in si_clkctl_xtal()
5249 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, in si_clkctl_xtal()
5251 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, in si_clkctl_xtal()
5259 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, in si_clkctl_xtal()
5268 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32), out); in si_clkctl_xtal()
5269 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32), in si_clkctl_xtal()
5292 si_info_t *sii; in si_clkctl_cc() local
5294 sii = SI_INFO(sih); in si_clkctl_cc()
5300 return _si_clkctl_cc(sii, mode); in si_clkctl_cc()
5305 _si_clkctl_cc(si_info_t *sii, uint mode) in _si_clkctl_cc() argument
5311 bool fast = SI_FAST(sii); in _si_clkctl_cc()
5314 if (CCREV(sii->pub.ccrev) < 6) in _si_clkctl_cc()
5318 ASSERT(CCREV(sii->pub.ccrev) != 10); in _si_clkctl_cc()
5321 INTR_OFF(sii, &intr_val); in _si_clkctl_cc()
5322 origidx = sii->curidx; in _si_clkctl_cc()
5323 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); in _si_clkctl_cc()
5324 } else if ((cc = (chipcregs_t *) CCREGS_FAST(sii)) == NULL) in _si_clkctl_cc()
5328 if (!CCCTL_ENAB(&sii->pub) && (CCREV(sii->pub.ccrev) < 20)) in _si_clkctl_cc()
5333 if (CCREV(sii->pub.ccrev) < 10) { in _si_clkctl_cc()
5335 si_clkctl_xtal(&sii->pub, XTAL, ON); in _si_clkctl_cc()
5336 SET_REG(sii->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP); in _si_clkctl_cc()
5337 } else if (CCREV(sii->pub.ccrev) < 20) { in _si_clkctl_cc()
5338 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR); in _si_clkctl_cc()
5340 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT); in _si_clkctl_cc()
5344 if (PMUCTL_ENAB(&sii->pub)) { in _si_clkctl_cc()
5346 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0), in _si_clkctl_cc()
5348 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); in _si_clkctl_cc()
5355 if (CCREV(sii->pub.ccrev) < 10) { in _si_clkctl_cc()
5356 scc = R_REG(sii->osh, &cc->slow_clk_ctl); in _si_clkctl_cc()
5360 W_REG(sii->osh, &cc->slow_clk_ctl, scc); in _si_clkctl_cc()
5364 si_clkctl_xtal(&sii->pub, XTAL, OFF); in _si_clkctl_cc()
5365 } else if (CCREV(sii->pub.ccrev) < 20) { in _si_clkctl_cc()
5367 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR); in _si_clkctl_cc()
5369 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); in _si_clkctl_cc()
5373 if (PMUCTL_ENAB(&sii->pub)) { in _si_clkctl_cc()
5375 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0), in _si_clkctl_cc()
5377 ASSERT(!(R_REG(sii->osh, &cc->clk_ctl_st) & htavail)); in _si_clkctl_cc()
5390 si_setcoreidx(&sii->pub, origidx); in _si_clkctl_cc()
5391 INTR_RESTORE(sii, &intr_val); in _si_clkctl_cc()
5617 si_info_t *sii; in BCMPOSTTRAPFN() local
5620 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
5626 reg_val = si_corereg(&sii->pub, SI_CC_IDX, offset, mask, val); in BCMPOSTTRAPFN()
5695 const si_info_t *sii = SI_INFO(sih); in si_pmu_keep_on() local
5702 W_REG(sii->osh, &cc->res_table_sel, int_val); in si_pmu_keep_on()
5703 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on()
5707 max_res_mask = R_REG(sii->osh, &cc->max_res_mask); in si_pmu_keep_on()
5709 W_REG(sii->osh, &cc->max_res_mask, max_res_mask); in si_pmu_keep_on()
5711 W_REG(sii->osh, &cc->min_res_mask, min_res_mask); in si_pmu_keep_on()
5718 const si_info_t *sii = SI_INFO(sih); in si_pmu_keep_on_get() local
5724 min_res_mask = R_REG(sii->osh, &cc->min_res_mask); in si_pmu_keep_on_get()
5727 W_REG(sii->osh, &cc->res_table_sel, i); in si_pmu_keep_on_get()
5728 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on_get()
5802 const si_info_t *sii = SI_INFO(sih); in si_pciereg() local
5804 if (!PCIE(sii)) { in si_pciereg()
5809 return pcicore_pciereg(sii->pch, offset, mask, val, type); in si_pciereg()
5815 const si_info_t *sii = SI_INFO(sih); in si_pcieserdesreg() local
5817 if (!PCIE(sii)) { in si_pcieserdesreg()
5822 return pcicore_pcieserdesreg(sii->pch, mdioslave, offset, mask, val); in si_pcieserdesreg()
5828 BCMATTACHFN(si_ispcie)(const si_info_t *sii) in BCMATTACHFN()
5832 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) in BCMATTACHFN()
5835 cap_ptr = pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, NULL); in BCMATTACHFN()
5875 const si_info_t *sii = SI_INFO(sih); in si_sdio_init() local
5883 idx = sii->curidx; in si_sdio_init()
5893 sih->buscorerev, idx, sii->curidx, OSL_OBFUSCATE_BUF(sdpregs))); in si_sdio_init()
5896 W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT); in si_sdio_init()
5897 W_REG(sii->osh, &sdpregs->sbintmask, (I_SB_SERR | I_SB_RESPERR | (1 << idx))); in si_sdio_init()
5904 bcmsdh_intr_enable(sii->sdh); in si_sdio_init()
5919 const si_info_t *sii = SI_INFO(sih); in si_pcie_war_ovr_update() local
5921 if (!PCIE_GEN1(sii)) in si_pcie_war_ovr_update()
5924 pcie_war_ovr_aspm_update(sii->pch, aspm); in si_pcie_war_ovr_update()
5930 const si_info_t *sii = SI_INFO(sih); in si_pcie_power_save_enable() local
5932 if (!PCIE_GEN1(sii)) in si_pcie_power_save_enable()
5935 pcie_power_save_enable(sii->pch, enable); in si_pcie_power_save_enable()
5941 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_maxpayload_size() local
5943 if (!PCIE(sii)) in si_pcie_set_maxpayload_size()
5946 pcie_set_maxpayload_size(sii->pch, size); in si_pcie_set_maxpayload_size()
5952 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_maxpayload_size() local
5954 if (!PCIE(sii)) in si_pcie_get_maxpayload_size()
5957 return pcie_get_maxpayload_size(sii->pch); in si_pcie_get_maxpayload_size()
5963 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_request_size() local
5965 if (!PCIE(sii)) in si_pcie_set_request_size()
5968 pcie_set_request_size(sii->pch, size); in si_pcie_set_request_size()
5974 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
5976 if (!PCIE_GEN1(sii)) in BCMATTACHFN()
5979 return pcie_get_request_size(sii->pch); in BCMATTACHFN()
5985 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_ssid() local
5987 if (!PCIE_GEN1(sii)) in si_pcie_get_ssid()
5990 return pcie_get_ssid(sii->pch); in si_pcie_get_ssid()
5996 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_bar0() local
5998 if (!PCIE(sii)) in si_pcie_get_bar0()
6001 return pcie_get_bar0(sii->pch); in si_pcie_get_bar0()
6007 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_cache() local
6009 if (!PCIE(sii)) in si_pcie_configspace_cache()
6012 return pcie_configspace_cache(sii->pch); in si_pcie_configspace_cache()
6018 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_restore() local
6020 if (!PCIE(sii)) in si_pcie_configspace_restore()
6023 return pcie_configspace_restore(sii->pch); in si_pcie_configspace_restore()
6029 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_get() local
6031 if (!PCIE(sii) || size > PCI_CONFIG_SPACE_SIZE) in si_pcie_configspace_get()
6034 return pcie_configspace_get(sii->pch, buf, size); in si_pcie_configspace_get()
6040 const si_info_t *sii = SI_INFO(sih); in si_pcie_hw_L1SS_war() local
6045 if (PCIE_GEN2(sii)) in si_pcie_hw_L1SS_war()
6046 pcie_hw_L1SS_war(sii->pch); in si_pcie_hw_L1SS_war()
6052 const si_info_t *sii; in BCMINITFN() local
6058 sii = SI_INFO(sih); in BCMINITFN()
6060 if (PCIE(sii)) { in BCMINITFN()
6061 pcicore_up(sii->pch, SI_PCIUP); in BCMINITFN()
6079 const si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
6080 BCM_REFERENCE(sii); in BCMINITFN()
6086 pcicore_down(sii->pch, SI_PCIDOWN); in BCMINITFN()
6096 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
6101 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) in BCMATTACHFN()
6104 ASSERT(PCI(sii) || PCIE(sii)); in BCMATTACHFN()
6105 ASSERT(sii->pub.buscoreidx != BADIDX); in BCMATTACHFN()
6107 if (PCI(sii)) { in BCMATTACHFN()
6109 idx = sii->curidx; in BCMATTACHFN()
6115 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx); in BCMATTACHFN()
6122 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { in BCMATTACHFN()
6124 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32)); in BCMATTACHFN()
6130 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w); in BCMATTACHFN()
6141 if (PCI(sii)) { in BCMATTACHFN()
6142 OR_REG(sii->osh, &pciregs->sbtopci2, (SBTOPCI_PREF | SBTOPCI_BURST)); in BCMATTACHFN()
6143 if (sii->pub.buscorerev >= 11) { in BCMATTACHFN()
6144 OR_REG(sii->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI); in BCMATTACHFN()
6148 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6149 W_REG(sii->osh, &pciregs->clkrun, (w | PCI_CLKRUN_DSBL)); in BCMATTACHFN()
6150 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6182 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
6212 if (!GOODIDX(armcidx, sii->numcores)) { in BCMATTACHFN()
6274 const si_info_t *sii = SI_INFO(sih); in si_pcieclkreq() local
6276 if (!PCIE(sii)) in si_pcieclkreq()
6279 return pcie_clkreq(sii->pch, mask, val); in si_pcieclkreq()
6285 const si_info_t *sii = SI_INFO(sih); in si_pcielcreg() local
6287 if (!PCIE(sii)) in si_pcielcreg()
6290 return pcie_lcreg(sii->pch, mask, val); in si_pcielcreg()
6296 const si_info_t *sii = SI_INFO(sih); in si_pcieltrenable() local
6298 if (!(PCIE(sii))) in si_pcieltrenable()
6301 return pcie_ltrenable(sii->pch, mask, val); in si_pcieltrenable()
6307 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN() local
6309 if (!(PCIE(sii))) in BCMATTACHFN()
6312 return pcie_obffenable(sii->pch, mask, val); in BCMATTACHFN()
6318 const si_info_t *sii = SI_INFO(sih); in si_pcieltr_reg() local
6320 if (!(PCIE(sii))) in si_pcieltr_reg()
6323 return pcie_ltr_reg(sii->pch, reg, mask, val); in si_pcieltr_reg()
6329 const si_info_t *sii = SI_INFO(sih); in si_pcieltrspacing_reg() local
6331 if (!(PCIE(sii))) in si_pcieltrspacing_reg()
6334 return pcieltrspacing_reg(sii->pch, mask, val); in si_pcieltrspacing_reg()
6340 const si_info_t *sii = SI_INFO(sih); in si_pcieltrhysteresiscnt_reg() local
6342 if (!(PCIE(sii))) in si_pcieltrhysteresiscnt_reg()
6345 return pcieltrhysteresiscnt_reg(sii->pch, mask, val); in si_pcieltrhysteresiscnt_reg()
6351 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_error_injection() local
6353 if (!PCIE(sii)) in si_pcie_set_error_injection()
6356 pcie_set_error_injection(sii->pch, mode); in si_pcie_set_error_injection()
6362 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_L1substate() local
6364 if (PCIE_GEN2(sii)) in si_pcie_set_L1substate()
6365 pcie_set_L1substate(sii->pch, substate); in si_pcie_set_L1substate()
6371 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_L1substate() local
6373 if (PCIE_GEN2(sii)) in si_pcie_get_L1substate()
6374 return pcie_get_L1substate(sii->pch); in si_pcie_get_L1substate()
6412 si_info_t *sii = SI_INFO(sih); in si_pci_fixcfg() local
6414 ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS); in si_pci_fixcfg()
6417 origidx = si_coreidx(&sii->pub); in si_pci_fixcfg()
6420 if (BUSCORETYPE(sii->pub.buscoretype) == PCIE2_CORE_ID) { in si_pci_fixcfg()
6421 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE2_CORE_ID, 0); in si_pci_fixcfg()
6424 } else if (BUSCORETYPE(sii->pub.buscoretype) == PCIE_CORE_ID) { in si_pci_fixcfg()
6425 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE_CORE_ID, 0); in si_pci_fixcfg()
6428 } else if (BUSCORETYPE(sii->pub.buscoretype) == PCI_CORE_ID) { in si_pci_fixcfg()
6429 pciregs = (sbpciregs_t *)si_setcore(&sii->pub, PCI_CORE_ID, 0); in si_pci_fixcfg()
6433 pciidx = si_coreidx(&sii->pub); in si_pci_fixcfg()
6437 val16 = R_REG(sii->osh, reg16); in si_pci_fixcfg()
6441 W_REG(sii->osh, reg16, val16); in si_pci_fixcfg()
6445 si_setcoreidx(&sii->pub, origidx); in si_pci_fixcfg()
6447 pcicore_hwup(sii->pch); in si_pci_fixcfg()
6456 const si_info_t *sii = SI_INFO(sih); in si_dump_pcieinfo() local
6458 if (!PCIE_GEN1(sii) && !PCIE_GEN2(sii)) in si_dump_pcieinfo()
6461 return pcicore_dump_pcieinfo(sii->pch, b); in si_dump_pcieinfo()
6525 const si_info_t *sii = SI_INFO(sih); in si_dump_pcieregs() local
6527 if (!PCIE_GEN1(sii) && !PCIE_GEN2(sii)) in si_dump_pcieregs()
6530 return pcicore_dump_pcieregs(sii->pch, b); in si_dump_pcieregs()
6539 const si_info_t *sii = SI_INFO(sih); in si_dump() local
6540 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_dump()
6544 OSL_OBFUSCATE_BUF(sii), sih->chip, sih->chiprev, in si_dump()
6547 OSL_OBFUSCATE_BUF(sii->osh), OSL_OBFUSCATE_BUF(sii->curmap)); in si_dump()
6552 CCREV(sih->ccrev), sih->buscoretype, sih->buscorerev, sii->curidx); in si_dump()
6555 if ((BUSTYPE(sih->bustype) == PCI_BUS) && (sii->pch)) in si_dump()
6556 pcicore_dump(sii->pch, b); in si_dump()
6560 for (i = 0; i < sii->numcores; i++) in si_dump()
6568 const si_info_t *sii = SI_INFO(sih); in si_ccreg_dump() local
6578 origidx = sii->curidx; in si_ccreg_dump()
6580 INTR_OFF(sii, &intr_val); in si_ccreg_dump()
6609 INTR_RESTORE(sii, &intr_val); in si_ccreg_dump()
6616 const si_info_t *sii = SI_INFO(sih); in si_clkctl_dump() local
6624 INTR_OFF(sii, &intr_val); in si_clkctl_dump()
6625 origidx = sii->curidx; in si_clkctl_dump()
6640 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)), in si_clkctl_dump()
6641 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32))); in si_clkctl_dump()
6650 INTR_RESTORE(sii, &intr_val); in si_clkctl_dump()
6656 const si_info_t *sii = SI_INFO(sih); in si_gpiodump() local
6661 INTR_OFF(sii, &intr_val); in si_gpiodump()
6670 bcm_bprintf(b, "gpioin 0x%x ", R_REG(sii->osh, &cc->gpioin)); in si_gpiodump()
6671 bcm_bprintf(b, "gpioout 0x%x ", R_REG(sii->osh, &cc->gpioout)); in si_gpiodump()
6672 bcm_bprintf(b, "gpioouten 0x%x ", R_REG(sii->osh, &cc->gpioouten)); in si_gpiodump()
6673 bcm_bprintf(b, "gpiocontrol 0x%x ", R_REG(sii->osh, &cc->gpiocontrol)); in si_gpiodump()
6674 bcm_bprintf(b, "gpiointpolarity 0x%x ", R_REG(sii->osh, &cc->gpiointpolarity)); in si_gpiodump()
6675 bcm_bprintf(b, "gpiointmask 0x%x ", R_REG(sii->osh, &cc->gpiointmask)); in si_gpiodump()
6682 INTR_RESTORE(sii, &intr_val); in si_gpiodump()
7022 sysmem_banksize(const si_info_t *sii, sysmemregs_t *regs, uint8 idx) in sysmem_banksize() argument
7027 W_REG(sii->osh, ®s->bankidx, bankidx); in sysmem_banksize()
7028 bankinfo = R_REG(sii->osh, ®s->bankinfo); in sysmem_banksize()
7037 const si_info_t *sii = SI_INFO(sih); in si_sysmem_size() local
7049 INTR_OFF(sii, &intr_val); in si_sysmem_size()
7059 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_sysmem_size()
7070 memsize += sysmem_banksize(sii, regs, i + nrb); in si_sysmem_size()
7075 INTR_RESTORE(sii, &intr_val); in si_sysmem_size()
7082 socram_banksize(const si_info_t *sii, sbsocramregs_t *regs, uint8 idx, uint8 mem_type) in socram_banksize() argument
7089 W_REG(sii->osh, ®s->bankidx, bankidx); in socram_banksize()
7090 bankinfo = R_REG(sii->osh, ®s->bankinfo); in socram_banksize()
7097 const si_info_t *sii = SI_INFO(sih); in si_socram_set_bankpda() local
7105 INTR_OFF(sii, &intr_val); in si_socram_set_bankpda()
7117 W_REG(sii->osh, ®s->bankidx, bankidx); in si_socram_set_bankpda()
7118 W_REG(sii->osh, ®s->bankpda, bankpda); in si_socram_set_bankpda()
7127 INTR_RESTORE(sii, &intr_val); in si_socram_set_bankpda()
7134 const si_info_t *sii = SI_INFO(sih); in si_socram_size() local
7145 INTR_OFF(sii, &intr_val); in si_socram_size()
7156 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_socram_size()
7183 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM); in si_socram_size()
7192 INTR_RESTORE(sii, &intr_val); in si_socram_size()
7204 const si_info_t *sii = SI_INFO(sih); in si_is_bus_mpu_present() local
7228 ret = R_REG(sii->osh, &cr4regs->corecapabilities) & CAP_MPU_MASK; in si_is_bus_mpu_present()
7231 ret = R_REG(sii->osh, &sysmemregs->mpucapabilities) & in si_is_bus_mpu_present()
7250 const si_info_t *sii = SI_INFO(sih); in si_tcm_size() local
7268 INTR_OFF(sii, &intr_val); in si_tcm_size()
7282 corecap = R_REG(sii->osh, arm_cap_reg); in si_tcm_size()
7291 W_REG(sii->osh, arm_bidx, idx); in si_tcm_size()
7293 bxinfo = R_REG(sii->osh, arm_binfo); in si_tcm_size()
7308 INTR_RESTORE(sii, &intr_val); in si_tcm_size()
7334 const si_info_t *sii = SI_INFO(sih); in si_socram_srmem_size() local
7345 INTR_OFF(sii, &intr_val); in si_socram_srmem_size()
7356 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_socram_srmem_size()
7363 W_REG(sii->osh, ®s->bankidx, i); in si_socram_srmem_size()
7364 if (R_REG(sii->osh, ®s->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK) in si_socram_srmem_size()
7365 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM); in si_socram_srmem_size()
7375 INTR_RESTORE(sii, &intr_val); in si_socram_srmem_size()
7396 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
7437 W_REG(sii->osh, &cc->SECI_status, SECI_STAT_BI); in BCMPOSTTRAPFN()
7440 SPINWAIT(!(R_REG(sii->osh, &cc->SECI_status) & SECI_STAT_BI), 1000); in BCMPOSTTRAPFN()
7464 (void)si_pmu_wait_for_steady_state(sih, sii->osh, pmu); in BCMPOSTTRAPFN()
7486 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
7487 *fast = SI_FAST(sii); in BCMPOSTTRAPFN()
7490 *origidx = sii->curidx; in BCMPOSTTRAPFN()
7494 cc = (chipcregs_t *)CCREGS_FAST(sii); in BCMPOSTTRAPFN()
7500 BCMPOSTTRAPFN(si_seci_access_preamble)(si_t *sih, const si_info_t *sii, uint32 *origidx, bool *fast) in BCMPOSTTRAPFN()
7505 if (((R_REG(sii->osh, &cc->clk_ctl_st) & CCS_SECICLKREQ) != CCS_SECICLKREQ)) { in BCMPOSTTRAPFN()
7520 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
7528 INTR_OFF(sii, &intr_val); in BCMPOSTTRAPFN()
7529 if (!(cc = si_seci_access_preamble(sih, sii, &origidx, &fast))) in BCMPOSTTRAPFN()
7582 W_REG(sii->osh, &cc->seci_uart_data, (uint32)(val & 0xff)); in BCMPOSTTRAPFN()
7594 INTR_RESTORE(sii, &intr_val); in BCMPOSTTRAPFN()
7621 const si_info_t *sii; in BCMINITFN() local
7646 sii = SI_INFO(sih); in BCMINITFN()
7647 fast = SI_FAST(sii); in BCMINITFN()
7649 origidx = sii->curidx; in BCMINITFN()
7652 } else if ((ptr = CCREGS_FAST(sii)) == NULL) in BCMINITFN()
7662 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7664 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7666 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7675 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7679 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7681 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7739 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7742 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7745 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7747 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7819 const si_info_t *sii; in BCMINITFN() local
7828 sii = SI_INFO(sih); in BCMINITFN()
7829 fast = SI_FAST(sii); in BCMINITFN()
7831 origidx = sii->curidx; in BCMINITFN()
7834 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL) in BCMINITFN()
7840 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskhi, 0x0); in BCMINITFN()
7841 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskmi, 0x0); in BCMINITFN()
7842 W_REG(sii->osh, &cc->eci.lt35.eci_intmasklo, 0x0); in BCMINITFN()
7844 W_REG(sii->osh, &cc->eci.ge35.eci_intmaskhi, 0x0); in BCMINITFN()
7845 W_REG(sii->osh, &cc->eci.ge35.eci_intmasklo, 0x0); in BCMINITFN()
7850 W_REG(sii->osh, &cc->eci.lt35.eci_control, ECI_MACCTRL_BITS); in BCMINITFN()
7852 W_REG(sii->osh, &cc->eci.ge35.eci_controllo, ECI_MACCTRLLO_BITS); in BCMINITFN()
7853 W_REG(sii->osh, &cc->eci.ge35.eci_controlhi, ECI_MACCTRLHI_BITS); in BCMINITFN()
7860 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskhi, 0x0); in BCMINITFN()
7861 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskmi, 0x0); in BCMINITFN()
7862 W_REG(sii->osh, &cc->eci.lt35.eci_eventmasklo, 0x0); in BCMINITFN()
7864 W_REG(sii->osh, &cc->eci.ge35.eci_eventmaskhi, 0x0); in BCMINITFN()
7865 W_REG(sii->osh, &cc->eci.ge35.eci_eventmasklo, 0x0); in BCMINITFN()
7947 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
7957 if (!(cc = si_seci_access_preamble(sih, sii, &origidx, &fast))) in BCMPOSTTRAPFN()
7972 const si_info_t *sii = SI_INFO(sih); in si_seci_upd() local
7981 fast = SI_FAST(sii); in si_seci_upd()
7982 INTR_OFF(sii, &intr_val); in si_seci_upd()
7984 origidx = sii->curidx; in si_seci_upd()
7987 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL) in si_seci_upd()
7994 regval = R_REG(sii->osh, &cc->chipcontrol); in si_seci_upd()
8003 W_REG(sii->osh, &cc->chipcontrol, regval); in si_seci_upd()
8007 regval = R_REG(sii->osh, &cc->SECI_config); in si_seci_upd()
8009 W_REG(sii->osh, &cc->SECI_config, regval); in si_seci_upd()
8010 SPINWAIT((R_REG(sii->osh, &cc->SECI_config) & SECI_UPD_SECI), 1000); in si_seci_upd()
8012 W_REG(sii->osh, &cc->seci_uart_data, SECI_SLIP_ESC_CHAR); in si_seci_upd()
8013 W_REG(sii->osh, &cc->seci_uart_data, SECI_REFRESH_REQ); in si_seci_upd()
8022 INTR_RESTORE(sii, &intr_val); in si_seci_upd()
8029 const si_info_t *sii = SI_INFO(sih); in BCMINITFN() local
8047 hndgci_init(sih, sii->osh, HND_GCI_PLAIN_UART_MODE, in BCMINITFN()
8067 const si_info_t *sii = SI_INFO(sih); in si_btcgpiowar() local
8079 INTR_OFF(sii, &intr_val); in si_btcgpiowar()
8086 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04); in si_btcgpiowar()
8091 INTR_RESTORE(sii, &intr_val); in si_btcgpiowar()
8097 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_restore() local
8105 W_REG(sii->osh, &cc->chipcontrol, val); in si_chipcontrl_restore()
8112 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_read() local
8121 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_read()
8130 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_srom4360() local
8139 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_srom4360()
8148 W_REG(sii->osh, &cc->chipcontrol, val); in si_chipcontrl_srom4360()
8163 const si_info_t *sii = SI_INFO(sih); in si_srom_clk_set() local
8174 val = R_REG(sii->osh, &cc->clkdiv2); in si_srom_clk_set()
8177 W_REG(sii->osh, &cc->clkdiv2, ((val & ~CLKD2_SROM) | divisor)); in si_srom_clk_set()
8199 const si_info_t *sii = SI_INFO(sih); in si_btc_enable_chipcontrol() local
8209 W_REG(sii->osh, &cc->chipcontrol, in si_btc_enable_chipcontrol()
8210 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK); in si_btc_enable_chipcontrol()
8218 si_info_t *sii = SI_INFO(sih); in si_set_device_removed() local
8220 sii->device_removed = status; in si_set_device_removed()
8228 const si_info_t *sii = SI_INFO(sih); in si_deviceremoved() local
8230 if (sii->device_removed) { in si_deviceremoved()
8258 const si_info_t *sii; in si_is_sprom_available() local
8266 sii = SI_INFO(sih); in si_is_sprom_available()
8267 origidx = sii->curidx; in si_is_sprom_available()
8270 sromctrl = R_REG(sii->osh, &cc->sromcontrol); in si_is_sprom_available()
8508 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
8512 INTR_OFF(sii, &intr_val); in BCMPOSTTRAPFN()
8520 INTR_RESTORE(sii, &intr_val); in BCMPOSTTRAPFN()
8530 const si_info_t *sii = SI_INFO(sih); in si_pmu_sr_upd() local
8534 si_pmu_res_minmax_update(sih, sii->osh); in si_pmu_sr_upd()
8546 const si_info_t *sii = SI_INFO(sih); in si_update_masks() local
8561 si_pmu_res_minmax_update(sih, sii->osh); in si_update_masks()
8667 const si_info_t *sii = SI_INFO(sih); in si_pcie_ltr_war() local
8669 if (PCIE_GEN2(sii)) in si_pcie_ltr_war()
8670 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0)); in si_pcie_ltr_war()
8678 const si_info_t *sii = SI_INFO(sih); in si_pcie_hw_LTR_war() local
8680 if (PCIE_GEN2(sii)) in si_pcie_hw_LTR_war()
8681 pcie_hw_LTR_war(sii->pch); in si_pcie_hw_LTR_war()
8689 const si_info_t *sii = SI_INFO(sih); in si_pciedev_reg_pm_clk_period() local
8691 if (PCIE_GEN2(sii)) in si_pciedev_reg_pm_clk_period()
8692 pciedev_reg_pm_clk_period(sii->pch); in si_pciedev_reg_pm_clk_period()
8700 const si_info_t *sii = SI_INFO(sih); in si_pciedev_crwlpciegen2() local
8702 if (PCIE_GEN2(sii)) in si_pciedev_crwlpciegen2()
8703 pciedev_crwlpciegen2(sii->pch); in si_pciedev_crwlpciegen2()
8711 const si_info_t *sii = SI_INFO(sih); in si_pcie_prep_D3() local
8713 if (PCIE_GEN2(sii)) in si_pcie_prep_D3()
8714 pciedev_prep_D3(sii->pch, enter_D3); in si_pcie_prep_D3()
8752 const si_info_t *sii = SI_INFO(sih); in si_43012_lp_enable() local
8759 INTR_OFF(sii, &intr_val); in si_43012_lp_enable()
8796 OR_REG(sii->osh, &gciregs->gpio_ctrl_iocfg_p_adr[count], in si_43012_lp_enable()
8808 INTR_RESTORE(sii, &intr_val); in si_43012_lp_enable()
9034 const si_info_t *sii = SI_INFO(sih); in si_pll_sr_reinit() local
9047 si_pmu_pll_init(sih, osh, sii->xtalfreq); in si_pll_sr_reinit()
9073 si_pmu_res_init(sih, sii->osh); in si_pll_sr_reinit()
9129 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9130 INTR_OFF(sii, intr_val); in BCMPOSTTRAPFN()
9136 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9137 INTR_RESTORE(sii, intr_val); in BCMPOSTTRAPFN()
9143 const si_info_t *sii = SI_INFO(sih); in si_get_nvram_rfldo3p3_war() local
9144 return sii->rfldo3p3_war; in si_get_nvram_rfldo3p3_war()
9150 const si_info_t *sii = SI_INFO(sih); in si_nvram_res_masks() local
9152 if (sii->min_mask_valid == TRUE) { in si_nvram_res_masks()
9153 SI_MSG(("Applying rmin=%d to min_mask\n", sii->nvram_min_mask)); in si_nvram_res_masks()
9154 *min_mask = sii->nvram_min_mask; in si_nvram_res_masks()
9157 if (sii->max_mask_valid == TRUE) { in si_nvram_res_masks()
9158 SI_MSG(("Applying rmax=%d to max_mask\n", sii->nvram_max_mask)); in si_nvram_res_masks()
9159 *max_mask = sii->nvram_max_mask; in si_nvram_res_masks()
9166 const si_info_t *sii = SI_INFO(sih); in si_getspurmode() local
9167 return sii->spurmode; in si_getspurmode()
9173 const si_info_t *sii = SI_INFO(sih); in si_xtalfreq() local
9174 return sii->xtalfreq; in si_xtalfreq()
9180 const si_info_t *sii = SI_INFO(sih); in si_get_openloop_dco_code() local
9181 return sii->openloop_dco_code; in si_get_openloop_dco_code()
9187 si_info_t *sii = SI_INFO(sih); in si_set_openloop_dco_code() local
9188 sii->openloop_dco_code = _openloop_dco_code; in si_set_openloop_dco_code()
9194 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9196 BCM_REFERENCE(sii); in BCMPOSTTRAPFN()
9209 armpllclkfreq = (sii->armpllclkfreq) ? sii->armpllclkfreq : armpllclk_max; in BCMPOSTTRAPFN()
9220 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9222 BCM_REFERENCE(sii); in BCMPOSTTRAPFN()
9225 ccidiv = (sii->ccidiv) ? sii->ccidiv : CCIDIV_3_TO_1; in BCMPOSTTRAPFN()
9302 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9306 r = (volatile uint32 *)((volatile char *)sii->curmap + in BCMPOSTTRAPFN()
9309 W_REG(sii->osh, r, val); in BCMPOSTTRAPFN()
9316 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9320 r = (volatile uint32 *)((volatile char *)sii->curmap + in BCMPOSTTRAPFN()
9323 return R_REG(sii->osh, r); in BCMPOSTTRAPFN()
9329 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9347 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9359 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9360 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9375 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9388 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9401 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9407 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9414 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9415 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9444 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9448 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & in BCMPOSTTRAPFN()
9460 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN() local
9477 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & mask) != val), in BCMPOSTTRAPFN()
9479 r = R_REG(sii->osh, fast_srpwr_addr) & mask; in BCMPOSTTRAPFN()
9589 const si_info_t *sii = SI_INFO(sih); in si_raw_reg() local
9595 if (sii == NULL) { in si_raw_reg()
9609 if (PCIE_GEN2(sii)) { in si_raw_reg()
9613 addr = (volatile uint32*)(((volatile uint8*)sii->curmap) + in si_raw_reg()
9621 addr = (volatile uint32*)(((volatile uint8*)sii->curmap) + in si_raw_reg()
9626 prev_value = OSL_PCI_READ_CONFIG(sii->osh, cfg_reg, 4); in si_raw_reg()
9629 OSL_PCI_WRITE_CONFIG(sii->osh, cfg_reg, in si_raw_reg()
9637 W_REG(sii->osh, addr, val); in si_raw_reg()
9639 val = R_REG(sii->osh, addr); in si_raw_reg()
9644 OSL_PCI_WRITE_CONFIG(sii->osh, in si_raw_reg()
9666 const si_info_t *sii = SI_INFO(sih); in si_lhl_ps_mode() local
9667 return sii->lhl_ps_mode; in si_lhl_ps_mode()
9673 const si_info_t *sii = SI_INFO(sih); in si_hib_ext_wakeup_isenab() local
9674 return sii->hib_ext_wakeup_enab; in si_hib_ext_wakeup_isenab()
10043 si_info_t *sii = SI_INFO(sih); in si_set_slice_id() local
10045 sii->slice = slice; in si_set_slice_id()
10051 const si_info_t *sii = SI_INFO(sih); in si_get_slice_id() local
10053 return sii->slice; in si_get_slice_id()