Lines Matching refs:sih
147 static void si_43012_lp_enable(si_t *sih);
160 static char *si_devpathvar(const si_t *sih, char *var, int len, const char *name);
161 static char *si_pcie_devpathvar(const si_t *sih, char *var, int len, const char *name);
169 static void si_gci_enable_gpioint(si_t *sih, bool enable);
171 static chipcregs_t * seci_set_core(si_t *sih, uint32 *origidx, bool *fast);
177 static void si_oob_war_BT_F1(si_t *sih);
187 static void si_wci2_rxfifo_intr_handler_process(si_t *sih, uint32 intstatus);
444 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
446 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
465 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
467 pmuaddr = SI_ENUM_BASE(sih) + offset; in si_get_pmu_reg_addr()
892 BCMATTACHFN(si_swdenable)(si_t *sih, uint32 swdflag) in BCMATTACHFN()
895 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
902 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT), in BCMATTACHFN()
907 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, in BCMATTACHFN()
912 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, jtagctrl), in BCMATTACHFN()
926 BCMATTACHFN(si_muxenab)(si_t *sih, uint32 w) in BCMATTACHFN()
930 pmu_chipcontrol = si_pmu_chipcontrol(sih, 1, 0, 0); in BCMATTACHFN()
931 chipcontrol = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), in BCMATTACHFN()
934 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
963 si_gci_set_functionsel(sih, hostwake, CC_FNSEL_MISC1); in BCMATTACHFN()
981 if (CHIPREV(sih->chiprev) >= 3) { in BCMATTACHFN()
982 si_gci_set_functionsel(sih, uart_rx, CC_FNSEL_GPIO1); in BCMATTACHFN()
983 si_gci_set_functionsel(sih, uart_tx, CC_FNSEL_GPIO1); in BCMATTACHFN()
985 si_gci_set_functionsel(sih, uart_rx, CC_FNSEL_GPIO0); in BCMATTACHFN()
986 si_gci_set_functionsel(sih, uart_tx, CC_FNSEL_GPIO0); in BCMATTACHFN()
1008 si_gci_set_functionsel(sih, hostwake, CC_FNSEL_GPIO0); in BCMATTACHFN()
1017 si_gci_set_functionsel(sih, CC_PIN_GPIO_00, CC_FNSEL_MISC1); in BCMATTACHFN()
1036 si_pmu_chipcontrol(sih, 1, ~0, pmu_chipcontrol); in BCMATTACHFN()
1037 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), in BCMATTACHFN()
1043 BCMPOSTTRAPFN(si_gci_direct)(si_t *sih, uint offset, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
1046 return si_corereg(sih, GCI_CORE_IDX(sih), offset, mask, val); in BCMPOSTTRAPFN()
1050 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val) in si_gci_indirect() argument
1053 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, regidx); in si_gci_indirect()
1054 return si_corereg(sih, GCI_CORE_IDX(sih), offset, mask, val); in si_gci_indirect()
1058 si_gci_input(si_t *sih, uint reg) in si_gci_input() argument
1061 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_input[reg]), 0, 0); in si_gci_input()
1065 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val) in si_gci_output() argument
1068 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_output[reg]), mask, val); in si_gci_output()
1072 si_gci_int_enable(si_t *sih, bool enable) in si_gci_int_enable() argument
1078 return (si_corereg(sih, SI_CC_IDX, offs, CI_ECI, (enable ? CI_ECI : 0))); in si_gci_int_enable()
1082 si_gci_reset(si_t *sih) in si_gci_reset() argument
1090 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_gci_reset()
1098 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1101 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_gci_reset()
1110 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1113 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_gci_reset()
1123 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1127 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_gci_reset()
1135 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_event[i]), ALLONES_32, 0x00); in si_gci_reset()
1140 si_gci_gpio_chipcontrol_ex(si_t *sih, uint8 gci_gpio, uint8 opt) in si_gci_gpio_chipcontrol_ex() argument
1142 si_gci_gpio_chipcontrol(sih, gci_gpio, opt); in si_gci_gpio_chipcontrol_ex()
1146 BCMPOSTTRAPFN(si_gci_gpio_chipcontrol)(si_t *sih, uint8 gci_gpio, uint8 opt) in BCMPOSTTRAPFN()
1155 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1156 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_gpioctl), in BCMPOSTTRAPFN()
1161 BCMPOSTTRAPFN(si_gci_gpio_reg)(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value, in BCMPOSTTRAPFN()
1171 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1175 si_corereg(sih, GCI_CORE_IDX(sih), in BCMPOSTTRAPFN()
1178 val_32 = si_corereg(sih, GCI_CORE_IDX(sih), reg_offset, 0, 0); in BCMPOSTTRAPFN()
1195 BCMPOSTTRAPFN(si_gci_enable_gpio)(si_t *sih, uint8 gpio, uint32 mask, uint32 value) in BCMPOSTTRAPFN()
1203 si_gci_set_functionsel(sih, gpio, CC_FNSEL_SAMEASPIN); in BCMPOSTTRAPFN()
1204 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1206 si_gpiocontrol(sih, mask, 0, GPIO_HI_PRIORITY); in BCMPOSTTRAPFN()
1207 si_gpioouten(sih, mask, mask, GPIO_HI_PRIORITY); in BCMPOSTTRAPFN()
1208 si_gpioout(sih, mask, value, GPIO_HI_PRIORITY); in BCMPOSTTRAPFN()
1220 si_gpio_enable(si_t *sih, uint32 mask) in si_gpio_enable() argument
1229 if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiocontrol), 0, 0) & mask) { in si_gpio_enable()
1235 switch (CHIPID(sih->chip)) in si_gpio_enable()
1250 si_gci_set_functionsel(sih, bit, (uint8)fnsel); in si_gpio_enable()
1256 si_gpioouten(sih, mask, 0, GPIO_HI_PRIORITY); in si_gpio_enable()
1263 BCMATTACHFN(si_gci_host_wake_gpio_init)(si_t *sih) in BCMATTACHFN()
1275 si_gci_host_wake_gpio_enable(sih, host_wake_gpio, FALSE); in BCMATTACHFN()
1281 BCMPOSTTRAPFN(si_gci_host_wake_gpio_enable)(si_t *sih, uint8 gpio, bool state) in BCMPOSTTRAPFN()
1283 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
1293 si_gci_enable_gpio(sih, gpio, 1 << gpio, in BCMPOSTTRAPFN()
1297 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMPOSTTRAPFN()
1303 si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state) in si_gci_time_sync_gpio_enable() argument
1305 switch (CHIPID(sih->chip)) { in si_gci_time_sync_gpio_enable()
1312 si_gci_enable_gpio(sih, gpio, 1 << gpio, in si_gci_time_sync_gpio_enable()
1316 SI_ERROR(("Time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_gci_time_sync_gpio_enable()
1324 BCMATTACHFN(si_gci_time_sync_gpio_init)(si_t *sih) in BCMATTACHFN()
1336 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
1344 si_gci_enable_gpio(sih, time_sync_gpio, in BCMATTACHFN()
1348 SI_ERROR(("time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1356 BCMPOSTTRAPFN(si_gci_gpio_wakemask)(si_t *sih, uint8 gpio, uint8 mask, uint8 value) in BCMPOSTTRAPFN()
1358 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_wakemask), in BCMPOSTTRAPFN()
1360 return (si_gci_gpio_reg(sih, gpio, mask, value, GCI_OFFSETOF(sih, gci_gpiowakemask))); in BCMPOSTTRAPFN()
1364 BCMPOSTTRAPFN(si_gci_gpio_intmask)(si_t *sih, uint8 gpio, uint8 mask, uint8 value) in BCMPOSTTRAPFN()
1366 return (si_gci_gpio_reg(sih, gpio, mask, value, GCI_OFFSETOF(sih, gci_gpiointmask))); in BCMPOSTTRAPFN()
1370 BCMPOSTTRAPFN(si_gci_gpio_status)(si_t *sih, uint8 gpio, uint8 mask, uint8 value) in BCMPOSTTRAPFN()
1372 return (si_gci_gpio_reg(sih, gpio, mask, value, GCI_OFFSETOF(sih, gci_gpiostatus))); in BCMPOSTTRAPFN()
1376 si_gci_enable_gpioint(si_t *sih, bool enable) in si_gci_enable_gpioint() argument
1379 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_intmask), in si_gci_enable_gpioint()
1382 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_intmask), in si_gci_enable_gpioint()
1388 BCMINITFN(si_enable_gpio_wake)(si_t *sih, uint8 *wake_mask, uint8 *cur_status, uint8 gci_gpio, in BCMINITFN()
1391 si_gci_gpio_chipcontrol(sih, gci_gpio, in BCMINITFN()
1394 si_gci_gpio_intmask(sih, gci_gpio, *wake_mask, *wake_mask); in BCMINITFN()
1395 si_gci_gpio_wakemask(sih, gci_gpio, *wake_mask, *wake_mask); in BCMINITFN()
1398 *cur_status = si_gci_gpio_status(sih, gci_gpio, in BCMINITFN()
1402 si_gci_enable_gpioint(sih, TRUE); in BCMINITFN()
1405 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, pmu_cc2_mask, pmu_cc2_value); in BCMINITFN()
1409 BCMPOSTTRAPFN(si_gci_config_wake_pin)(si_t *sih, uint8 gpio_n, uint8 wake_events, bool gci_gpio) in BCMPOSTTRAPFN()
1418 si_gci_gpio_chipcontrol(sih, gpio_n, in BCMPOSTTRAPFN()
1422 si_gci_gpio_intmask(sih, gpio_n, wake_events, wake_events); in BCMPOSTTRAPFN()
1423 si_gci_gpio_wakemask(sih, gpio_n, wake_events, wake_events); in BCMPOSTTRAPFN()
1426 si_gci_gpio_status(sih, gpio_n, in BCMPOSTTRAPFN()
1430 pmu_chipcontrol2 = si_pmu_chipcontrol(sih, PMU_CHIPCTL2, 0, 0); in BCMPOSTTRAPFN()
1431 pmu_chipcontrol2 |= si_pmu_wake_bit_offset(sih); in BCMPOSTTRAPFN()
1432 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, ~0, pmu_chipcontrol2); in BCMPOSTTRAPFN()
1435 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_intmask), in BCMPOSTTRAPFN()
1437 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_wakemask), in BCMPOSTTRAPFN()
1442 si_gci_free_wake_pin(si_t *sih, uint8 gpio_n) in si_gci_free_wake_pin() argument
1447 si_gci_gpio_chipcontrol(sih, gpio_n, chipcontrol); in si_gci_free_wake_pin()
1450 wake_events = si_gci_gpio_intmask(sih, gpio_n, 0, 0); in si_gci_free_wake_pin()
1451 si_gci_gpio_intmask(sih, gpio_n, wake_events, 0); in si_gci_free_wake_pin()
1452 wake_events = si_gci_gpio_wakemask(sih, gpio_n, 0, 0); in si_gci_free_wake_pin()
1453 si_gci_gpio_wakemask(sih, gpio_n, wake_events, 0); in si_gci_free_wake_pin()
1456 si_gci_gpio_status(sih, gpio_n, in si_gci_free_wake_pin()
1468 BCMATTACHFN(si_enable_perst_wake)(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status) in BCMATTACHFN()
1471 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
1473 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1481 BCMINITFN(si_get_device_wake_opt)(si_t *sih) in BCMINITFN()
1483 si_info_t *sii = SI_INFO(sih); in BCMINITFN()
1493 si_enable_device_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status) in si_enable_device_wake() argument
1497 const si_info_t *sii = SI_INFO(sih); in si_enable_device_wake()
1512 switch (CHIPID(sih->chip)) { in si_enable_device_wake()
1533 si_gci_set_functionsel(sih, gci_gpio, CC_FNSEL_GCI0); in si_enable_device_wake()
1534 si_enable_gpio_wake(sih, wake_mask, cur_status, gci_gpio, in si_enable_device_wake()
1538 si_gci_gpio_chipcontrol(sih, 0, in si_enable_device_wake()
1542 si_gci_indirect(sih, 0, in si_enable_device_wake()
1543 GCI_OFFSETOF(sih, gci_wakemask), in si_enable_device_wake()
1549 CHIPID(sih->chip), device_wake_opt)); in si_enable_device_wake()
1553 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_enable_device_wake()
1560 si_gci_gpioint_handler_unregister(si_t *sih, void *gci_i) in si_gci_gpioint_handler_unregister() argument
1565 sii = SI_INFO(sih); in si_gci_gpioint_handler_unregister()
1569 sii = SI_INFO(sih); in si_gci_gpioint_handler_unregister()
1571 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_gci_gpioint_handler_unregister()
1597 si_gci_gpioint_handler_register(si_t *sih, uint8 gci_gpio, uint8 gpio_status, in si_gci_gpioint_handler_register() argument
1603 sii = SI_INFO(sih); in si_gci_gpioint_handler_register()
1607 sii = SI_INFO(sih); in si_gci_gpioint_handler_register()
1609 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_gci_gpioint_handler_register()
1644 si_gci_gpioint_handler_process(si_t *sih) in si_gci_gpioint_handler_process() argument
1650 sii = SI_INFO(sih); in si_gci_gpioint_handler_process()
1655 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, 0); in si_gci_gpioint_handler_process()
1656 gpio_status[0] = si_corereg(sih, GCI_CORE_IDX(sih), in si_gci_gpioint_handler_process()
1657 GCI_OFFSETOF(sih, gci_gpiostatus), 0, 0); in si_gci_gpioint_handler_process()
1661 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_gpiostatus), ~0, gpio_status[0]); in si_gci_gpioint_handler_process()
1663 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, 1); in si_gci_gpioint_handler_process()
1664 gpio_status[1] = si_corereg(sih, GCI_CORE_IDX(sih), in si_gci_gpioint_handler_process()
1665 GCI_OFFSETOF(sih, gci_gpiostatus), 0, 0); in si_gci_gpioint_handler_process()
1669 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_gpiostatus), ~0, gpio_status[1]); in si_gci_gpioint_handler_process()
1691 si_gci_handler_process(si_t *sih) in si_gci_handler_process() argument
1697 gci_intstatus = si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_intstat), 0, 0); in si_gci_handler_process()
1701 si_gci_gpioint_handler_process(sih); in si_gci_handler_process()
1705 hndgci_handler_process(gci_intstatus, sih); in si_gci_handler_process()
1710 hnd_gci_mb_handler_process(gci_intstatus, sih); in si_gci_handler_process()
1716 si_wci2_rxfifo_intr_handler_process(sih, gci_intstatus); in si_gci_handler_process()
1722 hnd_gcishm_handler_process(sih, gci_intstatus); in si_gci_handler_process()
1728 si_gci_seci_init(si_t *sih) in si_gci_seci_init() argument
1730 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), ALLONES_32, in si_gci_seci_init()
1735 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_chipctrl), ALLONES_32, 0x0080000); //0x200 in si_gci_seci_init()
1737 si_gci_indirect(sih, 1, GCI_OFFSETOF(sih, gci_gpioctl), ALLONES_32, 0x00010280); //0x044 in si_gci_seci_init()
1740 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), //0x1e0 in si_gci_seci_init()
1742 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), ALLONES_32, 0xFF); //0x1f8 in si_gci_seci_init()
1743 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secifcr), ALLONES_32, 0x00); //0x1e4 in si_gci_seci_init()
1744 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x08); //0x1ec in si_gci_seci_init()
1745 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0xA8); //0x1e8 in si_gci_seci_init()
1746 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartescval), //0x1d0 in si_gci_seci_init()
1750 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_miscctl), ALLONES_32, 0xFFFF); //0xc54 in si_gci_seci_init()
1753 si_gci_indirect(sih, 0, in si_gci_seci_init()
1754 GCI_OFFSETOF(sih, gci_seciin_ctrl), ALLONES_32, 0x161); //0x218 in si_gci_seci_init()
1755 si_gci_indirect(sih, 0, in si_gci_seci_init()
1756 GCI_OFFSETOF(sih, gci_seciout_ctrl), ALLONES_32, 0x10051); //0x21c in si_gci_seci_init()
1758 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciout_txen_txbr), ALLONES_32, 0x01); //0x224 in si_gci_seci_init()
1762 si_gci_indirect(sih, 0, in si_gci_seci_init()
1763 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x13121110); //0x1bc in si_gci_seci_init()
1764 si_gci_indirect(sih, 1, in si_gci_seci_init()
1765 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x17161514); in si_gci_seci_init()
1766 si_gci_indirect(sih, 2, in si_gci_seci_init()
1767 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x1b1a1918); in si_gci_seci_init()
1771 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_seciusef0tx_reg), //0x1b4 in si_gci_seci_init()
1774 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_secitx_datatag), in si_gci_seci_init()
1776 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_secirx_datatag), in si_gci_seci_init()
1780 si_gci_indirect(sih, 0, in si_gci_seci_init()
1781 GCI_OFFSETOF(sih, gci_secif0tx_offset), 0xFFFFFFFF, 0x76543210); //0x1b8 in si_gci_seci_init()
1782 si_gci_indirect(sih, 1, in si_gci_seci_init()
1783 GCI_OFFSETOF(sih, gci_secif0tx_offset), 0xFFFFFFFF, 0x0000ba98); in si_gci_seci_init()
1784 if (CHIPID(sih->chip) == BCM43602_CHIP_ID) { in si_gci_seci_init()
1786 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_seciauxtx), in si_gci_seci_init()
1790 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl), in si_gci_seci_init()
1795 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_control_0), ALLONES_32, 0x00000000); in si_gci_seci_init()
1796 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_control_1), ALLONES_32, 0x00000000); in si_gci_seci_init()
1801 si_wci2_rxfifo_handler_register(si_t *sih, wci2_handler_t rx_cb, void *ctx) in si_wci2_rxfifo_handler_register() argument
1806 sii = SI_INFO(sih); in si_wci2_rxfifo_handler_register()
1810 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_wci2_rxfifo_handler_register()
1846 si_wci2_rxfifo_handler_unregister(si_t *sih) in si_wci2_rxfifo_handler_unregister() argument
1852 sii = SI_INFO(sih); in si_wci2_rxfifo_handler_unregister()
1855 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_wci2_rxfifo_handler_unregister()
1880 si_wci2_rxfifo_intr_handler_process(si_t *sih, uint32 intstatus) in si_wci2_rxfifo_intr_handler_process() argument
1882 const si_info_t *sii = SI_INFO(sih); in si_wci2_rxfifo_intr_handler_process()
1896 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_intstat), in si_wci2_rxfifo_intr_handler_process()
1904 udata = si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartdata), 0, 0); in si_wci2_rxfifo_intr_handler_process()
1921 udata = si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartdata), 0, 0); in si_wci2_rxfifo_intr_handler_process()
1938 si_config_gcigpio(si_t *sih, uint32 gci_pos, uint8 gcigpio, in si_config_gcigpio() argument
1943 si_gci_indirect(sih, indirect_idx, GCI_OFFSETOF(sih, gci_gpiomask), in si_config_gcigpio()
1947 si_gci_indirect(sih, gcigpio/4, GCI_OFFSETOF(sih, gci_gpioctl), in si_config_gcigpio()
1952 si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum, in si_ercx_init() argument
1960 si_gci_reset(sih); in si_ercx_init()
1964 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_ercx_init()
1991 si_gci_clear_functionsel(sih, fsync_fnsel); in si_ercx_init()
1992 si_gci_clear_functionsel(sih, lterx_fnsel); in si_ercx_init()
1993 si_gci_clear_functionsel(sih, ltetx_fnsel); in si_ercx_init()
1994 si_gci_clear_functionsel(sih, wlprio_fnsel); in si_ercx_init()
1997 si_gci_set_functionsel(sih, fsync_padnum, fsync_fnsel); in si_ercx_init()
1998 si_gci_set_functionsel(sih, lterx_padnum, lterx_fnsel); in si_ercx_init()
1999 si_gci_set_functionsel(sih, ltetx_padnum, ltetx_fnsel); in si_ercx_init()
2000 si_gci_set_functionsel(sih, wlprio_padnum, wlprio_fnsel); in si_ercx_init()
2009 si_config_gcigpio(sih, GCI_LTE_FRAMESYNC_POS, fsync_gcigpio, 0xFF, in si_ercx_init()
2013 si_config_gcigpio(sih, GCI_LTE_RX_POS, lterx_gcigpio, 0xFF, in si_ercx_init()
2017 si_config_gcigpio(sih, GCI_LTE_TX_POS, ltetx_gcigpio, 0xFF, in si_ercx_init()
2023 si_config_gcigpio(sih, GCI_WLAN_PRIO_POS, wlprio_gcigpio, 0xFF, in si_ercx_init()
2030 si_gci_indirect(sih, GCI_REGIDX(GCI_LTE_FRAMESYNC_POS), in si_ercx_init()
2031 GCI_OFFSETOF(sih, gci_inbandeventintmask), in si_ercx_init()
2040 si_gci_indirect(sih, GCI_REGIDX(GCI_LTE_FRAMESYNC_POS), in si_ercx_init()
2041 GCI_OFFSETOF(sih, gci_intpolreg), in si_ercx_init()
2047 si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum, in si_wci2_init() argument
2065 si_gci_reset(sih); in si_wci2_init()
2068 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_wci2_init()
2085 si_gci_set_functionsel(sih, seciin, fnselin); in si_wci2_init()
2086 si_gci_set_functionsel(sih, seciout, fnselout); in si_wci2_init()
2092 si_gci_indirect(sih, in si_wci2_init()
2094 GCI_OFFSETOF(sih, gci_inbandeventintmask), in si_wci2_init()
2102 if (GCIREV(sih->gcirev) >= 1) { in si_wci2_init()
2104 si_gci_indirect(sih, GCI_REGIDX(GCI_LTE_FRAMESYNC_POS), in si_wci2_init()
2105 GCI_OFFSETOF(sih, gci_intpolreg), in si_wci2_init()
2109 if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2111 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2112 GCI_OFFSETOF(sih, gci_seciin_ctrl), ALLONES_32, in si_wci2_init()
2118 si_gci_indirect(sih, gcigpioin/4, GCI_OFFSETOF(sih, gci_gpioctl), in si_wci2_init()
2124 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2125 GCI_OFFSETOF(sih, gci_seciout_ctrl), ALLONES_32, in si_wci2_init()
2131 si_gci_indirect(sih, gcigpioout/4, GCI_OFFSETOF(sih, gci_gpioctl), in si_wci2_init()
2136 if (GCIREV(sih->gcirev) >= 16) { in si_wci2_init()
2137 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2138 GCI_OFFSETOF(sih, gci_seciin_auxfifo_en), in si_wci2_init()
2144 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciin_auxfifo_en), in si_wci2_init()
2151 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciout_txen_txbr), ALLONES_32, in si_wci2_init()
2154 if (GCIREV(sih->gcirev) >= 5) { in si_wci2_init()
2156 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_miscctl), in si_wci2_init()
2160 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_miscctl), in si_wci2_init()
2165 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secifcr), ALLONES_32, 0x00); in si_wci2_init()
2166 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2167 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secilcr), in si_wci2_init()
2169 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2170 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0x00); in si_wci2_init()
2172 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0x28); in si_wci2_init()
2174 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartescval), ALLONES_32, 0xDB); in si_wci2_init()
2179 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2180 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2183 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2186 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2187 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2189 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2190 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2193 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2196 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2206 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2207 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2208 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xFF); in si_wci2_init()
2210 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2213 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2214 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2215 GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x80); in si_wci2_init()
2217 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2220 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2224 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2225 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2226 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xFF); in si_wci2_init()
2228 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2231 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2232 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2233 GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x80); in si_wci2_init()
2234 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2235 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2238 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2241 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2248 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2249 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2252 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2255 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2256 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2258 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2259 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2262 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2265 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2275 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2276 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2277 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF6); in si_wci2_init()
2279 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2288 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2289 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2290 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF4); in si_wci2_init()
2292 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2296 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2297 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2298 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF1); in si_wci2_init()
2300 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2304 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2305 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2307 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2308 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2311 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2314 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2325 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2326 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2327 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF7); in si_wci2_init()
2329 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2333 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2334 si_gci_indirect(sih, GCI_LTECX_SECI_ID, in si_wci2_init()
2335 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF4); in si_wci2_init()
2337 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), in si_wci2_init()
2341 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2342 si_gci_indirect(sih, GCI_LTECX_SECI_ID, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2344 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2345 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2348 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), in si_wci2_init()
2351 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), in si_wci2_init()
2356 if (GCIREV(sih->gcirev) >= 1) { in si_wci2_init()
2358 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_rxfifo_common_ctrl), in si_wci2_init()
2362 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_rxfifo_common_ctrl), in si_wci2_init()
2365 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_intmask), in si_wci2_init()
2372 si_gci_indirect(sih, 0, in si_wci2_init()
2373 GCI_OFFSETOF(sih, gci_gpioctl), 0x20000000, 0x20000010); in si_wci2_init()
2374 si_gci_indirect(sih, 1, in si_wci2_init()
2375 GCI_OFFSETOF(sih, gci_gpioctl), 0x20202020, 0x20202020); in si_wci2_init()
2379 si_gci_indirect(sih, 0x70010, in si_wci2_init()
2380 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000001, 0x00000001); in si_wci2_init()
2381 si_gci_indirect(sih, 0x60010, in si_wci2_init()
2382 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000002, 0x00000002); in si_wci2_init()
2383 si_gci_indirect(sih, 0x50010, in si_wci2_init()
2384 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000004, 0x00000004); in si_wci2_init()
2385 si_gci_indirect(sih, 0x40010, in si_wci2_init()
2386 GCI_OFFSETOF(sih, gci_gpiomask), 0x02000000, 0x00000008); in si_wci2_init()
2387 si_gci_indirect(sih, 0x30010, in si_wci2_init()
2388 GCI_OFFSETOF(sih, gci_gpiomask), 0x04000000, 0x04000010); in si_wci2_init()
2390 si_gci_indirect(sih, 0x50000, in si_wci2_init()
2391 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000010, 0x00000010); in si_wci2_init()
2392 si_gci_indirect(sih, 0x40000, in si_wci2_init()
2393 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000020, 0x00000020); in si_wci2_init()
2395 si_gci_direct(sih, in si_wci2_init()
2396 GCI_OFFSETOF(sih, gci_control_0), 0x00000030, 0x00000000); in si_wci2_init()
2403 si_btcx_wci2_init(si_t *sih) in si_btcx_wci2_init() argument
2406 si_gci_reset(sih); in si_btcx_wci2_init()
2408 if (GCIREV(sih->gcirev) >= 1) { in si_btcx_wci2_init()
2409 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), in si_btcx_wci2_init()
2430 si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode) in si_gci_uart_init() argument
2433 hndgci_init(sih, osh, HND_GCI_PLAIN_UART_MODE, in si_gci_uart_init()
2439 BCM_REFERENCE(sih); in si_gci_uart_init()
2481 BCMPOSTTRAPFN(si_gci_set_functionsel)(si_t *sih, uint32 pin, uint8 fnsel) in BCMPOSTTRAPFN()
2488 si_gci_chipcontrol(sih, reg, GCIMASK_4B(pos), GCIPOSVAL_4B(fnsel, pos)); in BCMPOSTTRAPFN()
2493 si_gci_get_functionsel(si_t *sih, uint32 pin) in si_gci_get_functionsel() argument
2500 temp = si_gci_chipstatus(sih, reg); in si_gci_get_functionsel()
2506 si_gci_clear_functionsel(si_t *sih, uint8 fnsel) in si_gci_clear_functionsel() argument
2511 if (si_gci_get_functionsel(sih, i) == fnsel) in si_gci_clear_functionsel()
2512 si_gci_set_functionsel(sih, i, CC_FNSEL_IND); in si_gci_clear_functionsel()
2518 BCMPOSTTRAPFN(si_gci_chipcontrol)(si_t *sih, uint reg, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
2521 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2527 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, reg); in BCMPOSTTRAPFN()
2528 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_chipctrl), mask, val); in BCMPOSTTRAPFN()
2533 BCMPOSTTRAPFN(si_gci_chipstatus)(si_t *sih, uint reg) in BCMPOSTTRAPFN()
2536 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2542 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, reg); in BCMPOSTTRAPFN()
2544 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_chipsts), 0, 0); in BCMPOSTTRAPFN()
2549 BCMINITFN(si_chipid)(const si_t *sih) in BCMINITFN()
2551 const si_info_t *sii = SI_INFO(sih); in BCMINITFN()
2553 return (sii->chipnew) ? sii->chipnew : sih->chip; in BCMINITFN()
2558 BCMATTACHFN(si_chipid_fixup)(si_t *sih) in BCMATTACHFN()
2560 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
2563 switch (sih->chip) { in BCMATTACHFN()
2565 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2569 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2573 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2578 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2588 BCMPOSTTRAPFN(si_clear_backplane_to_fast)(void *sih, void *addr) in BCMPOSTTRAPFN()
2590 si_t *_sih = DISCARD_QUAL(sih, si_t); in BCMPOSTTRAPFN()
2600 si_get_axi_errlog_info(const si_t *sih) in si_get_axi_errlog_info() argument
2602 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_get_axi_errlog_info()
2603 return (const si_axi_error_info_t *)sih->err_info; in si_get_axi_errlog_info()
2610 si_reset_axi_errlog_info(const si_t *sih) in si_reset_axi_errlog_info() argument
2612 if (sih->err_info) { in si_reset_axi_errlog_info()
2613 sih->err_info->count = 0; in si_reset_axi_errlog_info()
2703 struct si_pub *sih = &sii->pub; in BCMATTACHFN() local
2717 sih->buscoreidx = BADIDX; in BCMATTACHFN()
2724 sih->enum_base = si_enum_base(devid); in BCMATTACHFN()
2727 sih->err_info = MALLOCZ(osh, sizeof(si_axi_error_info_t)); in BCMATTACHFN()
2728 if (sih->err_info == NULL) { in BCMATTACHFN()
2735 osl_set_bpt_cb(osh, (void *)si_clear_backplane_to_fast, (void *)sih); in BCMATTACHFN()
2750 if (!GOODCOREADDR(savewin, SI_ENUM_BASE(sih))) in BCMATTACHFN()
2751 savewin = SI_ENUM_BASE(sih); in BCMATTACHFN()
2752 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih)); in BCMATTACHFN()
2763 cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE(sih), SI_CORE_SIZE); in BCMATTACHFN()
2766 sih->bustype = (uint16)bustype; in BCMATTACHFN()
2797 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; in BCMATTACHFN()
2799 sih->chip = w & CID_ID_MASK; in BCMATTACHFN()
2800 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; in BCMATTACHFN()
2801 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; in BCMATTACHFN()
2804 dhd_conf_set_hw_oob_intr(sdh, sih); in BCMATTACHFN()
2807 si_chipid_fixup(sih); in BCMATTACHFN()
2809 sih->issim = IS_SIM(sih->chippkg); in BCMATTACHFN()
2811 if (MULTIBP_CAP(sih)) { in BCMATTACHFN()
2812 sih->_multibp_enable = TRUE; in BCMATTACHFN()
2831 if ((sii->numcores = nci_scan(sih)) == 0u) { in BCMATTACHFN()
2873 SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip)); in BCMATTACHFN()
2916 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
2917 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMATTACHFN()
2918 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2919 (CHIPREV(sih->chiprev) <= 2)) { in BCMATTACHFN()
2941 hnd_cpu_wait(sih); in BCMATTACHFN()
2947 si_sprom_init(sih); in BCMATTACHFN()
3012 if (HIB_EXT_WAKEUP_CAP(sih)) { in BCMATTACHFN()
3020 } else if (LHL_IS_PSMODE_1(sih)) { in BCMATTACHFN()
3054 if (BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip) || in BCMATTACHFN()
3055 BCM4389_CHIP(sih->chip) || in BCMATTACHFN()
3056 BCM4388_CHIP(sih->chip) || BCM4397_CHIP(sih->chip) || FALSE) { in BCMATTACHFN()
3075 hnd_tcam_bootloader_load(si_setcore(sih, ARMCR4_CORE_ID, 0), pvars); in BCMATTACHFN()
3077 hnd_tcam_bootloader_load(si_setcore(sih, SYSMEM_CORE_ID, 0), pvars); in BCMATTACHFN()
3079 hnd_tcam_bootloader_load(si_setcore(sih, SOCRAM_CORE_ID, 0), pvars); in BCMATTACHFN()
3081 si_setcoreidx(sih, origidx); in BCMATTACHFN()
3087 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMATTACHFN()
3102 si_setcoreidx(sih, origidx); in BCMATTACHFN()
3107 hnd_gci_init(sih); in BCMATTACHFN()
3130 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_23, in BCMATTACHFN()
3146 if (PMUCTL_ENAB(sih)) { in BCMATTACHFN()
3148 si_pmu_init(sih, sii->osh); in BCMATTACHFN()
3149 si_pmu_chip_init(sih, sii->osh); in BCMATTACHFN()
3161 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3175 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); in BCMATTACHFN()
3178 si_pmu_pll_init(sih, sii->osh, xtalfreq); in BCMATTACHFN()
3189 sr_save_restore_init(sih); in BCMATTACHFN()
3198 if (SRPWR_CAP(sih) && !SRPWR_ENAB()) { in BCMATTACHFN()
3205 if (si_scan_core_present(sih)) { in BCMATTACHFN()
3209 si_srpwr_request(sih, domain, domain); in BCMATTACHFN()
3213 si_pmu_res_init(sih, sii->osh); in BCMATTACHFN()
3214 si_pmu_swreg_init(sih, sii->osh); in BCMATTACHFN()
3216 hnd_gcishm_init(sih); in BCMATTACHFN()
3227 si_lowpwr_opt(sih); in BCMATTACHFN()
3236 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
3237 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
3238 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMATTACHFN()
3239 (CCREV(sih->ccrev) >= 62)) { in BCMATTACHFN()
3241 CHIPC_REG(sih, clk_ctl_st, CCS_SFLASH_CLKREQ, 0); in BCMATTACHFN()
3270 ASSERT(!si_taclear(sih, FALSE)); in BCMATTACHFN()
3273 si_pmustatstimer_init(sih); in BCMATTACHFN()
3281 if (((PCIECOREREV(sih->buscorerev) == 66) || (PCIECOREREV(sih->buscorerev) == 68)) && in BCMATTACHFN()
3282 CST4378_CHIPMODE_BTOP(sih->chipst)) { in BCMATTACHFN()
3287 si_oob_war_BT_F1(sih); in BCMATTACHFN()
3294 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
3311 BCMATTACHFN(si_detach)(si_t *sih) in BCMATTACHFN()
3313 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
3319 bcopy(&sih, &si_local, sizeof(si_t*)); in BCMATTACHFN()
3324 sh_sflash_detach(sii->osh, sih); in BCMATTACHFN()
3327 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMATTACHFN()
3351 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
3361 if (sih->err_info) { in BCMATTACHFN()
3362 MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t)); in BCMATTACHFN()
3371 si_dvfs_info_deinit(sih, sii->osh); in BCMATTACHFN()
3381 BCMPOSTTRAPFN(si_osh)(si_t *sih) in BCMPOSTTRAPFN()
3385 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3390 si_setosh(si_t *sih, osl_t *osh) in si_setosh() argument
3394 sii = SI_INFO(sih); in si_setosh()
3404 BCMATTACHFN(si_register_intr_callback)(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, in BCMATTACHFN()
3407 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
3415 sii->dev_coreid = si_coreid(sih); in BCMATTACHFN()
3419 BCMPOSTTRAPFN(si_deregister_intr_callback)(si_t *sih) in BCMPOSTTRAPFN()
3423 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3430 BCMPOSTTRAPFN(si_intflag)(si_t *sih) in BCMPOSTTRAPFN()
3432 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3434 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3435 return sb_intflag(sih); in BCMPOSTTRAPFN()
3436 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3437 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3438 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3441 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3442 return nci_intflag(sih); in BCMPOSTTRAPFN()
3450 si_flag(si_t *sih) in si_flag() argument
3452 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_flag()
3453 return sb_flag(sih); in si_flag()
3454 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag()
3455 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag()
3456 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag()
3457 return ai_flag(sih); in si_flag()
3458 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_flag()
3459 return ub_flag(sih); in si_flag()
3460 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_flag()
3461 return nci_flag(sih); in si_flag()
3469 si_flag_alt(const si_t *sih) in si_flag_alt() argument
3471 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag_alt()
3472 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag_alt()
3473 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag_alt()
3474 return ai_flag_alt(sih); in si_flag_alt()
3475 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_flag_alt()
3476 return nci_flag_alt(sih); in si_flag_alt()
3484 BCMATTACHFN(si_setint)(const si_t *sih, int siflag) in BCMATTACHFN()
3486 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3487 sb_setint(sih, siflag); in BCMATTACHFN()
3488 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3489 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3490 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3491 ai_setint(sih, siflag); in BCMATTACHFN()
3492 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3493 ub_setint(sih, siflag); in BCMATTACHFN()
3494 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3495 nci_setint(sih, siflag); in BCMATTACHFN()
3501 si_oobr_baseaddr(const si_t *sih, bool second) in si_oobr_baseaddr() argument
3503 const si_info_t *sii = SI_INFO(sih); in si_oobr_baseaddr()
3505 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_oobr_baseaddr()
3507 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_oobr_baseaddr()
3508 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_oobr_baseaddr()
3509 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_oobr_baseaddr()
3511 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_oobr_baseaddr()
3512 return nci_oobr_baseaddr(sih, second); in si_oobr_baseaddr()
3520 BCMPOSTTRAPFN(si_coreid)(const si_t *sih) in BCMPOSTTRAPFN()
3522 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3525 return nci_coreid(sih, sii->curidx); in BCMPOSTTRAPFN()
3533 BCMPOSTTRAPFN(si_coreidx)(const si_t *sih) in BCMPOSTTRAPFN()
3537 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3542 si_get_num_cores(const si_t *sih) in si_get_num_cores() argument
3544 const si_info_t *sii = SI_INFO(sih); in si_get_num_cores()
3549 si_d11_switch_addrbase(si_t *sih, uint coreunit) in si_d11_switch_addrbase() argument
3551 return si_setcore(sih, D11_CORE_ID, coreunit); in si_d11_switch_addrbase()
3556 si_coreunit(const si_t *sih) in si_coreunit() argument
3558 const si_info_t *sii = SI_INFO(sih); in si_coreunit()
3566 return nci_coreunit(sih); in si_coreunit()
3574 coreid = si_coreid(sih); in si_coreunit()
3585 BCMATTACHFN(si_corevendor)(const si_t *sih) in BCMATTACHFN()
3587 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3588 return sb_corevendor(sih); in BCMATTACHFN()
3589 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3590 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3591 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3592 return ai_corevendor(sih); in BCMATTACHFN()
3593 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3594 return ub_corevendor(sih); in BCMATTACHFN()
3595 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3596 return nci_corevendor(sih); in BCMATTACHFN()
3604 BCMINITFN(si_backplane64)(const si_t *sih) in BCMINITFN()
3606 return ((sih->cccaps & CC_CAP_BKPLN64) != 0); in BCMINITFN()
3610 BCMPOSTTRAPFN(si_corerev)(const si_t *sih) in BCMPOSTTRAPFN()
3612 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3613 return sb_corerev(sih); in BCMPOSTTRAPFN()
3614 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3615 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3616 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3617 return ai_corerev(sih); in BCMPOSTTRAPFN()
3618 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3619 return ub_corerev(sih); in BCMPOSTTRAPFN()
3620 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3621 return nci_corerev(sih); in BCMPOSTTRAPFN()
3629 si_corerev_minor(const si_t *sih) in si_corerev_minor() argument
3631 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_corerev_minor()
3632 return ai_corerev_minor(sih); in si_corerev_minor()
3634 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_corerev_minor()
3635 return nci_corerev_minor(sih); in si_corerev_minor()
3643 BCMPOSTTRAPFN(si_findcoreidx)(const si_t *sih, uint coreid, uint coreunit) in BCMPOSTTRAPFN()
3645 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3650 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3651 return nci_findcoreidx(sih, coreid, coreunit); in BCMPOSTTRAPFN()
3668 BCMPOSTTRAPFN(si_hwa_present)(const si_t *sih) in BCMPOSTTRAPFN()
3670 if (si_findcoreidx(sih, HWA_CORE_ID, 0) != BADIDX) { in BCMPOSTTRAPFN()
3677 BCMPOSTTRAPFN(si_sysmem_present)(const si_t *sih) in BCMPOSTTRAPFN()
3679 if (si_findcoreidx(sih, SYSMEM_CORE_ID, 0) != BADIDX) { in BCMPOSTTRAPFN()
3687 si_findcoreid(const si_t *sih, uint coreidx) in si_findcoreid() argument
3689 const si_info_t *sii = SI_INFO(sih); in si_findcoreid()
3695 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_findcoreid()
3696 return nci_coreid(sih, coreidx); in si_findcoreid()
3703 BCMPOSTTRAPFN(si_numcoreunits)(const si_t *sih, uint coreid) in BCMPOSTTRAPFN()
3705 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3710 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3711 return nci_numcoreunits(sih, coreid); in BCMPOSTTRAPFN()
3724 BCMPOSTTRAPRAMFN(si_numd11coreunits)(const si_t *sih) in BCMPOSTTRAPRAMFN()
3726 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPRAMFN()
3727 return nci_numcoreunits(sih, D11_CORE_ID); in BCMPOSTTRAPRAMFN()
3729 return si_numcoreunits(sih, D11_CORE_ID); in BCMPOSTTRAPRAMFN()
3734 si_corelist(const si_t *sih, uint coreid[]) in si_corelist() argument
3736 const si_info_t *sii = SI_INFO(sih); in si_corelist()
3739 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_corelist()
3740 return nci_corelist(sih, coreid); in si_corelist()
3749 BCMPOSTTRAPFN(si_wrapperregs)(const si_t *sih) in BCMPOSTTRAPFN()
3751 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3760 BCMPOSTTRAPFN(si_coreregs)(const si_t *sih) in BCMPOSTTRAPFN()
3762 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3775 BCMPOSTTRAPFN(si_setcore)(si_t *sih, uint coreid, uint coreunit) in BCMPOSTTRAPFN()
3777 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3780 idx = si_findcoreidx(sih, coreid, coreunit); in BCMPOSTTRAPFN()
3785 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3786 return sb_setcoreidx(sih, idx); in BCMPOSTTRAPFN()
3787 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3788 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3789 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3790 return ai_setcoreidx(sih, idx); in BCMPOSTTRAPFN()
3791 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3792 return ub_setcoreidx(sih, idx); in BCMPOSTTRAPFN()
3793 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3794 return nci_setcoreidx(sih, idx); in BCMPOSTTRAPFN()
3802 BCMPOSTTRAPFN(si_setcoreidx)(si_t *sih, uint coreidx) in BCMPOSTTRAPFN()
3804 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3805 return sb_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
3806 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3807 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3808 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3809 return ai_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
3810 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3811 return ub_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
3812 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3813 return nci_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
3822 BCMPOSTTRAPFN(si_switch_core)(si_t *sih, uint coreid, uint *origidx, bcm_int_bitmask_t *intr_val) in BCMPOSTTRAPFN()
3825 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3835 else if (coreid == BUSCORETYPE(sih->buscoretype)) in BCMPOSTTRAPFN()
3840 cc = si_setcore(sih, coreid, 0); in BCMPOSTTRAPFN()
3848 BCMPOSTTRAPFN(si_restore_core)(si_t *sih, uint coreid, bcm_int_bitmask_t *intr_val) in BCMPOSTTRAPFN()
3850 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3852 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype)))) in BCMPOSTTRAPFN()
3855 si_setcoreidx(sih, coreid); in BCMPOSTTRAPFN()
3862 BCMPOSTTRAPFN(si_corerev_ext)(si_t *sih, uint coreid, uint coreunit) in BCMPOSTTRAPFN()
3867 coreidx = si_coreidx(sih); in BCMPOSTTRAPFN()
3868 (void)si_setcore(sih, coreid, coreunit); in BCMPOSTTRAPFN()
3870 corerev = si_corerev(sih); in BCMPOSTTRAPFN()
3872 si_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
3876 uint si_get_corerev(si_t *sih, uint core_id) in si_get_corerev() argument
3881 si_switch_core(sih, core_id, &orig_coreid, &intr_val); in si_get_corerev()
3882 corerev = si_corerev(sih); in si_get_corerev()
3883 si_restore_core(sih, orig_coreid, &intr_val); in si_get_corerev()
3889 BCMATTACHFN(si_numaddrspaces)(const si_t *sih) in BCMATTACHFN()
3891 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3892 return sb_numaddrspaces(sih); in BCMATTACHFN()
3893 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3894 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3895 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3896 return ai_numaddrspaces(sih); in BCMATTACHFN()
3897 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3898 return ub_numaddrspaces(sih); in BCMATTACHFN()
3899 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3900 return nci_numaddrspaces(sih); in BCMATTACHFN()
3915 si_addrspace(const si_t *sih, uint spidx, uint baidx) in si_addrspace() argument
3917 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_addrspace()
3918 return sb_addrspace(sih, baidx); in si_addrspace()
3919 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_addrspace()
3920 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_addrspace()
3921 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_addrspace()
3922 return ai_addrspace(sih, spidx, baidx); in si_addrspace()
3923 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_addrspace()
3924 return ub_addrspace(sih, baidx); in si_addrspace()
3925 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_addrspace()
3926 return nci_addrspace(sih, spidx, baidx); in si_addrspace()
3940 BCMATTACHFN(si_addrspacesize)(const si_t *sih, uint spidx, uint baidx) in BCMATTACHFN()
3942 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3943 return sb_addrspacesize(sih, baidx); in BCMATTACHFN()
3944 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3945 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3946 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3947 return ai_addrspacesize(sih, spidx, baidx); in BCMATTACHFN()
3948 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3949 return ub_addrspacesize(sih, baidx); in BCMATTACHFN()
3950 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3951 return nci_addrspacesize(sih, spidx, baidx); in BCMATTACHFN()
3959 si_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size) in si_coreaddrspaceX() argument
3962 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_coreaddrspaceX()
3963 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_coreaddrspaceX()
3964 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_coreaddrspaceX()
3965 ai_coreaddrspaceX(sih, asidx, addr, size); in si_coreaddrspaceX()
3966 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_coreaddrspaceX()
3967 nci_coreaddrspaceX(sih, asidx, addr, size); in si_coreaddrspaceX()
3973 BCMPOSTTRAPFN(si_core_cflags)(const si_t *sih, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
3975 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3976 return sb_core_cflags(sih, mask, val); in BCMPOSTTRAPFN()
3977 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3978 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3979 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3980 return ai_core_cflags(sih, mask, val); in BCMPOSTTRAPFN()
3981 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3982 return ub_core_cflags(sih, mask, val); in BCMPOSTTRAPFN()
3983 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3984 return nci_core_cflags(sih, mask, val); in BCMPOSTTRAPFN()
3992 si_core_cflags_wo(const si_t *sih, uint32 mask, uint32 val) in si_core_cflags_wo() argument
3994 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_cflags_wo()
3995 sb_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
3996 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_cflags_wo()
3997 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_cflags_wo()
3998 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_cflags_wo()
3999 ai_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
4000 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_cflags_wo()
4001 ub_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
4002 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_cflags_wo()
4003 nci_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
4009 si_core_sflags(const si_t *sih, uint32 mask, uint32 val) in si_core_sflags() argument
4011 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_sflags()
4012 return sb_core_sflags(sih, mask, val); in si_core_sflags()
4013 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_sflags()
4014 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_sflags()
4015 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_sflags()
4016 return ai_core_sflags(sih, mask, val); in si_core_sflags()
4017 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_sflags()
4018 return ub_core_sflags(sih, mask, val); in si_core_sflags()
4019 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_sflags()
4020 return nci_core_sflags(sih, mask, val); in si_core_sflags()
4028 si_commit(si_t *sih) in si_commit() argument
4030 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_commit()
4031 sb_commit(sih); in si_commit()
4032 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_commit()
4033 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_commit()
4034 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_commit()
4036 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_commit()
4038 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_commit()
4046 BCMPOSTTRAPFN(si_iscoreup)(const si_t *sih) in BCMPOSTTRAPFN()
4048 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4049 return sb_iscoreup(sih); in BCMPOSTTRAPFN()
4050 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4051 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4052 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4053 return ai_iscoreup(sih); in BCMPOSTTRAPFN()
4054 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4055 return ub_iscoreup(sih); in BCMPOSTTRAPFN()
4056 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4057 return nci_iscoreup(sih); in BCMPOSTTRAPFN()
4066 BCMPOSTTRAPFN(si_wrapperreg)(const si_t *sih, uint32 offset, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
4069 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4070 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4071 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4072 return (ai_wrap_reg(sih, offset, mask, val)); in BCMPOSTTRAPFN()
4073 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4074 return (nci_get_wrap_reg(sih, offset, mask, val)); in BCMPOSTTRAPFN()
4111 si_invalidate_second_bar0win(si_t *sih) in si_invalidate_second_bar0win() argument
4113 si_info_t *sii = SI_INFO(sih); in si_invalidate_second_bar0win()
4118 si_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read) in si_backplane_access() argument
4122 si_info_t *sii = SI_INFO(sih); in si_backplane_access()
4125 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_backplane_access()
4187 si_backplane_access_64(si_t *sih, uint addr, uint size, uint64 *val, bool read) in si_backplane_access_64() argument
4195 si_info_t *sii = SI_INFO(sih); in si_backplane_access_64()
4198 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_backplane_access_64()
4246 BCMPOSTTRAPFN(si_corereg)(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) in BCMPOSTTRAPFN()
4248 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4249 return sb_corereg(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4250 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4251 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4252 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4253 return ai_corereg(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4254 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4255 return ub_corereg(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4256 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4257 return nci_corereg(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4265 BCMPOSTTRAPFN(si_corereg_writeonly)(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) in BCMPOSTTRAPFN()
4267 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
4268 return nci_corereg_writeonly(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4271 return ai_corereg_writeonly(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
4291 BCMPOSTTRAPFN(si_pmu_corereg)(si_t *sih, uint32 idx, uint regoff, uint mask, uint val) in BCMPOSTTRAPFN()
4296 if (mask != 0 && PMUREV(sih->pmurev) >= 22 && in BCMPOSTTRAPFN()
4298 pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) : in BCMPOSTTRAPFN()
4301 while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING) in BCMPOSTTRAPFN()
4305 return si_corereg(sih, idx, regoff, mask, val); in BCMPOSTTRAPFN()
4318 BCMPOSTTRAPFN(si_corereg_addr)(si_t *sih, uint coreidx, uint regoff) in BCMPOSTTRAPFN()
4320 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4321 return sb_corereg_addr(sih, coreidx, regoff); in BCMPOSTTRAPFN()
4322 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4323 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4324 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4325 return ai_corereg_addr(sih, coreidx, regoff); in BCMPOSTTRAPFN()
4326 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4327 return nci_corereg_addr(sih, coreidx, regoff); in BCMPOSTTRAPFN()
4334 si_core_disable(const si_t *sih, uint32 bits) in si_core_disable() argument
4336 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_disable()
4337 sb_core_disable(sih, bits); in si_core_disable()
4338 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_disable()
4339 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_disable()
4340 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_disable()
4341 ai_core_disable(sih, bits); in si_core_disable()
4342 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_disable()
4343 nci_core_disable(sih, bits); in si_core_disable()
4344 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_disable()
4345 ub_core_disable(sih, bits); in si_core_disable()
4349 BCMPOSTTRAPFN(si_core_reset)(si_t *sih, uint32 bits, uint32 resetbits) in BCMPOSTTRAPFN()
4351 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4352 sb_core_reset(sih, bits, resetbits); in BCMPOSTTRAPFN()
4353 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4354 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4355 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4356 ai_core_reset(sih, bits, resetbits); in BCMPOSTTRAPFN()
4357 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4358 nci_core_reset(sih, bits, resetbits); in BCMPOSTTRAPFN()
4359 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4360 ub_core_reset(sih, bits, resetbits); in BCMPOSTTRAPFN()
4365 si_corebist(const si_t *sih) in si_corebist() argument
4371 cflags = si_core_cflags(sih, 0, 0); in si_corebist()
4374 si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC)); in si_corebist()
4377 SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000); in si_corebist()
4379 if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR) in si_corebist()
4383 si_core_cflags(sih, 0xffff, cflags); in si_corebist()
4389 si_num_slaveports(const si_t *sih, uint coreid) in si_num_slaveports() argument
4391 uint idx = si_findcoreidx(sih, coreid, 0); in si_num_slaveports()
4395 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_num_slaveports()
4396 num = ai_num_slaveports(sih, idx); in si_num_slaveports()
4398 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_num_slaveports()
4399 num = nci_num_slaveports(sih, idx); in si_num_slaveports()
4407 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint core_id, uint coreunit) in si_get_slaveport_addr() argument
4409 const si_info_t *sii = SI_INFO(sih); in si_get_slaveport_addr()
4413 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_slaveport_addr()
4414 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_slaveport_addr()
4415 (CHIPTYPE(sih->socitype) == SOCI_NAI) || in si_get_slaveport_addr()
4416 (CHIPTYPE(sih->socitype) == SOCI_NCI))) in si_get_slaveport_addr()
4419 si_setcore(sih, core_id, coreunit); in si_get_slaveport_addr()
4421 addr = si_addrspace(sih, spidx, baidx); in si_get_slaveport_addr()
4423 si_setcoreidx(sih, origidx); in si_get_slaveport_addr()
4431 si_get_d11_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint coreunit) in si_get_d11_slaveport_addr() argument
4433 const si_info_t *sii = SI_INFO(sih); in si_get_d11_slaveport_addr()
4437 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_d11_slaveport_addr()
4438 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_d11_slaveport_addr()
4439 (CHIPTYPE(sih->socitype) == SOCI_NAI) || in si_get_d11_slaveport_addr()
4440 (CHIPTYPE(sih->socitype) == SOCI_NCI))) in si_get_d11_slaveport_addr()
4443 si_setcore(sih, D11_CORE_ID, coreunit); in si_get_d11_slaveport_addr()
4445 addr = si_addrspace(sih, spidx, baidx); in si_get_d11_slaveport_addr()
4447 si_setcoreidx(sih, origidx); in si_get_d11_slaveport_addr()
4567 si_chip_hostif(const si_t *sih) in si_chip_hostif() argument
4571 switch (CHIPID(sih->chip)) { in si_chip_hostif()
4585 if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB)) in si_chip_hostif()
4593 if (CST4369_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
4595 else if (CST4369_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
4607 if (CST4362_CHIPMODE_SDIOD(sih->chipst)) { in si_chip_hostif()
4609 } else if (CST4362_CHIPMODE_PCIE(sih->chipst)) { in si_chip_hostif()
4623 BCMINITFN(si_clock)(si_t *sih) in BCMINITFN()
4625 const si_info_t *sii = SI_INFO(sih); in BCMINITFN()
4633 if (PMUCTL_ENAB(sih)) { in BCMINITFN()
4634 rate = si_pmu_si_clock(sih, sii->osh); in BCMINITFN()
4639 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMINITFN()
4643 pll_type = sih->cccaps & CC_CAP_PLL_MASK; in BCMINITFN()
4658 si_setcoreidx(sih, idx); in BCMINITFN()
4667 BCMINITFN(si_alp_clock)(si_t *sih) in BCMINITFN()
4669 if (PMUCTL_ENAB(sih)) { in BCMINITFN()
4670 return si_pmu_alp_clock(sih, si_osh(sih)); in BCMINITFN()
4678 BCMINITFN(si_ilp_clock)(si_t *sih) in BCMINITFN()
4680 if (PMUCTL_ENAB(sih)) in BCMINITFN()
4681 return si_pmu_ilp_clock(sih, si_osh(sih)); in BCMINITFN()
4689 si_watchdog(si_t *sih, uint ticks) in si_watchdog() argument
4694 if (PMUCTL_ENAB(sih) && pmu_wdt) { in si_watchdog()
4695 nb = (CCREV(sih->ccrev) < 26) ? 16 : ((CCREV(sih->ccrev) >= 37) ? 32 : 24); in si_watchdog()
4710 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_watchdog()
4711 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_watchdog()
4712 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_watchdog()
4713 PMU_REG_NEW(sih, min_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
4714 PMU_REG_NEW(sih, watchdog_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
4715 PMU_REG_NEW(sih, pmustatus, PST_WDRESET, PST_WDRESET); in si_watchdog()
4716 PMU_REG_NEW(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, 0); in si_watchdog()
4717 SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO), in si_watchdog()
4721 pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks); in si_watchdog()
4725 si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC); in si_watchdog()
4731 if (CCREV(sih->ccrev) >= 65) { in si_watchdog()
4732 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, in si_watchdog()
4736 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks); in si_watchdog()
4743 si_watchdog_ms(si_t *sih, uint32 ms) in si_watchdog_ms() argument
4745 si_watchdog(sih, wd_msticks * ms); in si_watchdog_ms()
4754 si_taclear(si_t *sih, bool details) in si_taclear() argument
4758 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_taclear()
4759 return sb_taclear(sih, details); in si_taclear()
4760 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_taclear()
4761 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_taclear()
4762 (CHIPTYPE(sih->socitype) == SOCI_NCI) || in si_taclear()
4763 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_taclear()
4765 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_taclear()
4781 BCMATTACHFN(si_d11_devid)(si_t *sih) in BCMATTACHFN()
4783 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
4792 if ((device = (uint16)si_getdevpathintvar(sih, rstr_devid)) != 0) in BCMATTACHFN()
4800 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
4810 BCMATTACHFN(si_corepciid)(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, in BCMATTACHFN()
4817 uint32 core = si_coreid(sih); in BCMATTACHFN()
4824 switch (si_corevendor(sih)) { in BCMATTACHFN()
4936 device = si_d11_devid(sih); in BCMATTACHFN()
4958 si_dumpregs(si_t *sih, struct bcmstrbuf *b) in si_dumpregs() argument
4960 si_info_t *sii = SI_INFO(sih); in si_dumpregs()
4967 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_dumpregs()
4968 sb_dumpregs(sih, b); in si_dumpregs()
4969 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_dumpregs()
4970 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_dumpregs()
4971 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_dumpregs()
4972 ai_dumpregs(sih, b); in si_dumpregs()
4973 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_dumpregs()
4974 ub_dumpregs(sih, b); in si_dumpregs()
4975 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_dumpregs()
4976 nci_dumpregs(sih, b); in si_dumpregs()
4980 si_setcoreidx(sih, origidx); in si_dumpregs()
4988 si_view(si_t *sih, bool verbose) in si_view() argument
4990 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_view()
4991 sb_view(sih, verbose); in si_view()
4992 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_view()
4993 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_view()
4994 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_view()
4995 ai_view(sih, verbose); in si_view()
4996 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_view()
4997 ub_view(sih, verbose); in si_view()
4998 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_view()
4999 nci_view(sih, verbose); in si_view()
5005 si_viewall(si_t *sih, bool verbose) in si_viewall() argument
5007 si_info_t *sii = SI_INFO(sih); in si_viewall()
5014 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_viewall()
5015 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_viewall()
5016 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_viewall()
5017 ai_viewall(sih, verbose); in si_viewall()
5018 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_viewall()
5019 nci_viewall(sih, verbose); in si_viewall()
5023 si_setcoreidx(sih, i); in si_viewall()
5024 si_view(sih, verbose); in si_viewall()
5027 si_setcoreidx(sih, curidx); in si_viewall()
5122 BCMINITFN(si_clkctl_init)(si_t *sih) in BCMINITFN()
5129 if (!CCCTL_ENAB(sih)) in BCMINITFN()
5132 sii = SI_INFO(sih); in BCMINITFN()
5136 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
5143 if (CCREV(sih->ccrev) >= 10) in BCMINITFN()
5153 si_setcoreidx(sih, origidx); in BCMINITFN()
5159 BCMINITFN(si_clkctl_fast_pwrup_delay)(si_t *sih) in BCMINITFN()
5161 si_info_t *sii = SI_INFO(sih); in BCMINITFN()
5169 if (PMUCTL_ENAB(sih)) { in BCMINITFN()
5171 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh); in BCMINITFN()
5176 if (!CCCTL_ENAB(sih)) in BCMINITFN()
5184 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
5199 si_setcoreidx(sih, origidx); in BCMINITFN()
5207 si_clkctl_xtal(si_t *sih, uint what, bool on) in si_clkctl_xtal() argument
5212 sii = SI_INFO(sih); in si_clkctl_xtal()
5214 switch (BUSTYPE(sih->bustype)) { in si_clkctl_xtal()
5290 si_clkctl_cc(si_t *sih, uint mode) in si_clkctl_cc() argument
5294 sii = SI_INFO(sih); in si_clkctl_cc()
5297 if (CCREV(sih->ccrev) < 6) in si_clkctl_cc()
5398 BCMNMIATTACHFN(si_devpath)(const si_t *sih, char *path, int size) in BCMNMIATTACHFN()
5408 switch (BUSTYPE(sih->bustype)) { in BCMNMIATTACHFN()
5410 slen = snprintf(path, (size_t)size, "sb/%u/", si_coreidx(sih)); in BCMNMIATTACHFN()
5413 ASSERT((SI_INFO(sih))->osh != NULL); in BCMNMIATTACHFN()
5415 OSL_PCI_BUS((SI_INFO(sih))->osh), in BCMNMIATTACHFN()
5416 OSL_PCI_SLOT((SI_INFO(sih))->osh)); in BCMNMIATTACHFN()
5421 slen = snprintf(path, (size_t)size, "sd/%u/", si_coreidx(sih)); in BCMNMIATTACHFN()
5439 BCMNMIATTACHFN(si_devpath_pcie)(const si_t *sih, char *path, int size) in BCMNMIATTACHFN()
5447 ASSERT((SI_INFO(sih))->osh != NULL); in BCMNMIATTACHFN()
5449 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh), in BCMNMIATTACHFN()
5450 OSL_PCIE_BUS((SI_INFO(sih))->osh)); in BCMNMIATTACHFN()
5456 BCMATTACHFN(si_coded_devpathvar)(const si_t *sih, char *varname, int var_len, const char *name) in BCMATTACHFN()
5470 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5472 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh), in BCMATTACHFN()
5473 OSL_PCIE_BUS((SI_INFO(sih))->osh)); in BCMATTACHFN()
5478 if (si_devpath(sih, devpath, SI_DEVPATH_BUFSZ) == 0) { in BCMATTACHFN()
5515 BCMATTACHFN(si_getdevpathvar)(const si_t *sih, const char *name) in BCMATTACHFN()
5520 si_devpathvar(sih, varname, sizeof(varname), name); in BCMATTACHFN()
5525 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5526 si_pcie_devpathvar(sih, varname, sizeof(varname), name); in BCMATTACHFN()
5532 if (si_coded_devpathvar(sih, varname, sizeof(varname), name) == NULL) in BCMATTACHFN()
5540 BCMATTACHFN(si_getdevpathintvar)(const si_t *sih, const char *name) in BCMATTACHFN()
5543 BCM_REFERENCE(sih); in BCMATTACHFN()
5549 si_devpathvar(sih, varname, sizeof(varname), name); in BCMATTACHFN()
5554 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5555 si_pcie_devpathvar(sih, varname, sizeof(varname), name); in BCMATTACHFN()
5561 if (si_coded_devpathvar(sih, varname, sizeof(varname), name) == NULL) in BCMATTACHFN()
5575 BCMATTACHFN(si_devpathvar)(const si_t *sih, char *var, int len, const char *name) in BCMATTACHFN()
5582 if (si_devpath(sih, var, len) == 0) { in BCMATTACHFN()
5595 BCMATTACHFN(si_pcie_devpathvar)(const si_t *sih, char *var, int len, const char *name) in BCMATTACHFN()
5602 if (si_devpath_pcie(sih, var, len) == 0) { in BCMATTACHFN()
5615 BCMPOSTTRAPFN(si_ccreg)(si_t *sih, uint32 offset, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
5620 sii = SI_INFO(sih); in BCMPOSTTRAPFN()
5632 sih_write_sraon(si_t *sih, int offset, int len, const uint32* data) in sih_write_sraon() argument
5635 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in sih_write_sraon()
5636 W_REG(si_osh(sih), &cc->sr_memrw_addr, offset); in sih_write_sraon()
5638 W_REG(si_osh(sih), &cc->sr_memrw_data, *data); in sih_write_sraon()
5646 si_dump_pmu(si_t *sih, void *arg) in si_dump_pmu() argument
5654 pmu_var->pmu_control = si_ccreg(sih, PMU_CTL, 0, 0); in si_dump_pmu()
5655 pmu_var->pmu_capabilities = si_ccreg(sih, PMU_CAP, 0, 0); in si_dump_pmu()
5656 pmu_var->pmu_status = si_ccreg(sih, PMU_ST, 0, 0); in si_dump_pmu()
5657 pmu_var->res_state = si_ccreg(sih, PMU_RES_STATE, 0, 0); in si_dump_pmu()
5658 pmu_var->res_pending = si_ccreg(sih, PMU_RES_PENDING, 0, 0); in si_dump_pmu()
5659 pmu_var->pmu_timer1 = si_ccreg(sih, PMU_TIMER, 0, 0); in si_dump_pmu()
5660 pmu_var->min_res_mask = si_ccreg(sih, MINRESMASKREG, 0, 0); in si_dump_pmu()
5661 pmu_var->max_res_mask = si_ccreg(sih, MAXRESMASKREG, 0, 0); in si_dump_pmu()
5665 pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0); in si_dump_pmu()
5670 pmu_var->pmu_regcontrol[i] = si_pmu_vreg_control(sih, i, 0, 0); in si_dump_pmu()
5675 pmu_var->pmu_pllcontrol[i] = si_pmu_pllcontrol(sih, i, 0, 0); in si_dump_pmu()
5680 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmu()
5681 pmu_var->pmu_rsrc_up_down_timer[i] = si_corereg(sih, SI_CC_IDX, in si_dump_pmu()
5687 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmu()
5688 pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0); in si_dump_pmu()
5693 si_pmu_keep_on(const si_t *sih, int32 int_val) in si_pmu_keep_on() argument
5695 const si_info_t *sii = SI_INFO(sih); in si_pmu_keep_on()
5696 chipcregs_t *cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_pmu_keep_on()
5715 si_pmu_keep_on_get(const si_t *sih) in si_pmu_keep_on_get() argument
5718 const si_info_t *sii = SI_INFO(sih); in si_pmu_keep_on_get()
5719 chipcregs_t *cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_pmu_keep_on_get()
5739 si_power_island_set(si_t *sih, uint32 int_val) in si_power_island_set() argument
5764 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x003c0000, j); in si_power_island_set()
5773 si_power_island_get(si_t *sih) in si_power_island_get() argument
5781 reg_val = si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0, 0); in si_power_island_get()
5800 si_pciereg(const si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type) in si_pciereg() argument
5802 const si_info_t *sii = SI_INFO(sih); in si_pciereg()
5813 si_pcieserdesreg(const si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val) in si_pcieserdesreg() argument
5815 const si_info_t *sii = SI_INFO(sih); in si_pcieserdesreg()
5845 si_pci_pmeen(const si_t *sih) in si_pci_pmeen() argument
5847 pcicore_pmeen(SI_INFO(sih)->pch); in si_pci_pmeen()
5852 si_pci_pmestat(const si_t *sih) in si_pci_pmestat() argument
5854 return pcicore_pmestat(SI_INFO(sih)->pch); in si_pci_pmestat()
5859 si_pci_pmeclr(const si_t *sih) in si_pci_pmeclr() argument
5861 pcicore_pmeclr(SI_INFO(sih)->pch); in si_pci_pmeclr()
5865 si_pci_pmestatclr(const si_t *sih) in si_pci_pmestatclr() argument
5867 pcicore_pmestatclr(SI_INFO(sih)->pch); in si_pci_pmestatclr()
5873 si_sdio_init(si_t *sih) in si_sdio_init() argument
5875 const si_info_t *sii = SI_INFO(sih); in si_sdio_init()
5877 if (BUSCORETYPE(sih->buscoretype) == SDIOD_CORE_ID) { in si_sdio_init()
5884 ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0)); in si_sdio_init()
5888 sdpregs = (sdpcmd_regs_t *)si_setcore(sih, SDIOD_CORE_ID, 0); in si_sdio_init()
5893 sih->buscorerev, idx, sii->curidx, OSL_OBFUSCATE_BUF(sdpregs))); in si_sdio_init()
5900 si_setcoreidx(sih, idx); in si_sdio_init()
5917 si_pcie_war_ovr_update(const si_t *sih, uint8 aspm) in si_pcie_war_ovr_update() argument
5919 const si_info_t *sii = SI_INFO(sih); in si_pcie_war_ovr_update()
5928 si_pcie_power_save_enable(const si_t *sih, bool enable) in si_pcie_power_save_enable() argument
5930 const si_info_t *sii = SI_INFO(sih); in si_pcie_power_save_enable()
5939 si_pcie_set_maxpayload_size(const si_t *sih, uint16 size) in si_pcie_set_maxpayload_size() argument
5941 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_maxpayload_size()
5950 si_pcie_get_maxpayload_size(const si_t *sih) in si_pcie_get_maxpayload_size() argument
5952 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_maxpayload_size()
5961 si_pcie_set_request_size(const si_t *sih, uint16 size) in si_pcie_set_request_size() argument
5963 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_request_size()
5972 BCMATTACHFN(si_pcie_get_request_size)(const si_t *sih) in BCMATTACHFN()
5974 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
5983 si_pcie_get_ssid(const si_t *sih) in si_pcie_get_ssid() argument
5985 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_ssid()
5994 si_pcie_get_bar0(const si_t *sih) in si_pcie_get_bar0() argument
5996 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_bar0()
6005 si_pcie_configspace_cache(const si_t *sih) in si_pcie_configspace_cache() argument
6007 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_cache()
6016 si_pcie_configspace_restore(const si_t *sih) in si_pcie_configspace_restore() argument
6018 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_restore()
6027 si_pcie_configspace_get(const si_t *sih, uint8 *buf, uint size) in si_pcie_configspace_get() argument
6029 const si_info_t *sii = SI_INFO(sih); in si_pcie_configspace_get()
6038 si_pcie_hw_L1SS_war(const si_t *sih) in si_pcie_hw_L1SS_war() argument
6040 const si_info_t *sii = SI_INFO(sih); in si_pcie_hw_L1SS_war()
6050 BCMINITFN(si_pci_up)(const si_t *sih) in BCMINITFN()
6055 if (BUSTYPE(sih->bustype) != PCI_BUS) in BCMINITFN()
6058 sii = SI_INFO(sih); in BCMINITFN()
6067 BCMUNINITFN(si_pci_sleep)(const si_t *sih) in BCMUNINITFN()
6072 pcicore_sleep(SI_INFO(sih)->pch); in BCMUNINITFN()
6077 BCMINITFN(si_pci_down)(const si_t *sih) in BCMINITFN()
6079 const si_info_t *sii = SI_INFO(sih); in BCMINITFN()
6083 if (BUSTYPE(sih->bustype) != PCI_BUS) in BCMINITFN()
6094 BCMATTACHFN(si_pci_setup)(si_t *sih, uint coremask) in BCMATTACHFN()
6096 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
6112 siflag = si_flag(sih); in BCMATTACHFN()
6115 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx); in BCMATTACHFN()
6133 si_setint(sih, siflag); in BCMATTACHFN()
6154 si_setcoreidx(sih, idx); in BCMATTACHFN()
6160 BCMATTACHFN(si_get_armcoreidx)(si_t *sih) in BCMATTACHFN()
6162 uint saveidx = si_coreidx(sih); in BCMATTACHFN()
6165 if (si_setcore(sih, ARMCR4_CORE_ID, 0) != NULL || in BCMATTACHFN()
6166 si_setcore(sih, ARMCA7_CORE_ID, 0) != NULL) { in BCMATTACHFN()
6167 coreidx = si_coreidx(sih); in BCMATTACHFN()
6170 si_setcoreidx(sih, saveidx); in BCMATTACHFN()
6180 BCMATTACHFN(si_pcie_setup)(si_t *sih, uint coreidx) in BCMATTACHFN()
6182 si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
6186 osl_t *osh = si_osh(sih); in BCMATTACHFN()
6187 uint saveidx = si_coreidx(sih); in BCMATTACHFN()
6193 if ((oobrregs = si_setcore(sih, HND_OOBR_CORE_ID, 0)) == NULL) { in BCMATTACHFN()
6197 ASSERT(BUSTYPE(sih->bustype) == PCI_BUS); in BCMATTACHFN()
6198 ASSERT(BUSTYPE(sih->buscoretype) == PCIE2_CORE_ID); in BCMATTACHFN()
6205 main_intr = hnd_oobr_get_intr_config(sih, coreidx, in BCMATTACHFN()
6206 HND_CORE_MAIN_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6211 armcidx = si_get_armcoreidx(sih); in BCMATTACHFN()
6219 main_intr = hnd_oobr_get_intr_config(sih, coreidx, in BCMATTACHFN()
6221 alt_intr = hnd_oobr_get_intr_config(sih, coreidx, in BCMATTACHFN()
6222 HND_CORE_ALT_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6231 hnd_oobr_set_intr_src(sih, sih->buscoreidx, pciepidx, main_intr); in BCMATTACHFN()
6240 main_intr = hnd_oobr_get_intr_config(sih, coreidx, in BCMATTACHFN()
6241 HND_CORE_MAIN_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6257 si_setcoreidx(sih, saveidx); in BCMATTACHFN()
6265 si_pci_setup(sih, coremask); in BCMATTACHFN()
6272 si_pcieclkreq(const si_t *sih, uint32 mask, uint32 val) in si_pcieclkreq() argument
6274 const si_info_t *sii = SI_INFO(sih); in si_pcieclkreq()
6283 si_pcielcreg(const si_t *sih, uint32 mask, uint32 val) in si_pcielcreg() argument
6285 const si_info_t *sii = SI_INFO(sih); in si_pcielcreg()
6294 si_pcieltrenable(const si_t *sih, uint32 mask, uint32 val) in si_pcieltrenable() argument
6296 const si_info_t *sii = SI_INFO(sih); in si_pcieltrenable()
6305 BCMATTACHFN(si_pcieobffenable)(const si_t *sih, uint32 mask, uint32 val) in BCMATTACHFN()
6307 const si_info_t *sii = SI_INFO(sih); in BCMATTACHFN()
6316 si_pcieltr_reg(const si_t *sih, uint32 reg, uint32 mask, uint32 val) in si_pcieltr_reg() argument
6318 const si_info_t *sii = SI_INFO(sih); in si_pcieltr_reg()
6327 si_pcieltrspacing_reg(const si_t *sih, uint32 mask, uint32 val) in si_pcieltrspacing_reg() argument
6329 const si_info_t *sii = SI_INFO(sih); in si_pcieltrspacing_reg()
6338 si_pcieltrhysteresiscnt_reg(const si_t *sih, uint32 mask, uint32 val) in si_pcieltrhysteresiscnt_reg() argument
6340 const si_info_t *sii = SI_INFO(sih); in si_pcieltrhysteresiscnt_reg()
6349 si_pcie_set_error_injection(const si_t *sih, uint32 mode) in si_pcie_set_error_injection() argument
6351 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_error_injection()
6360 si_pcie_set_L1substate(const si_t *sih, uint32 substate) in si_pcie_set_L1substate() argument
6362 const si_info_t *sii = SI_INFO(sih); in si_pcie_set_L1substate()
6369 si_pcie_get_L1substate(const si_t *sih) in si_pcie_get_L1substate() argument
6371 const si_info_t *sii = SI_INFO(sih); in si_pcie_get_L1substate()
6381 si_pcie_readreg(void *sih, uint addrtype, uint offset) in si_pcie_readreg() argument
6383 return pcie_readreg(sih, (sbpcieregs_t *)PCIEREGS(((si_info_t *)sih)), in si_pcie_readreg()
6389 si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val) in si_pcie_writereg() argument
6391 return pcie_writereg(sih, (sbpcieregs_t *)PCIEREGS(((si_info_t *)sih)), in si_pcie_writereg()
6402 si_pci_fixcfg(si_t *sih) in si_pci_fixcfg() argument
6412 si_info_t *sii = SI_INFO(sih); in si_pci_fixcfg()
6454 si_dump_pcieinfo(const si_t *sih, struct bcmstrbuf *b) in si_dump_pcieinfo() argument
6456 const si_info_t *sii = SI_INFO(sih); in si_dump_pcieinfo()
6465 si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b) in si_dump_pmuregs() argument
6471 bcm_bprintf(b, "===pmu(rev %d)===\n", sih->pmurev); in si_dump_pmuregs()
6472 if (!(sih->pmurev == 0x11 || (sih->pmurev >= 0x15 && sih->pmurev <= 0x19))) { in si_dump_pmuregs()
6476 pmu_cap = si_ccreg(sih, PMU_CAP, 0, 0); in si_dump_pmuregs()
6477 bcm_bprintf(b, "pmu_control 0x%x\n", si_ccreg(sih, PMU_CTL, 0, 0)); in si_dump_pmuregs()
6479 bcm_bprintf(b, "pmu_status 0x%x\n", si_ccreg(sih, PMU_ST, 0, 0)); in si_dump_pmuregs()
6480 bcm_bprintf(b, "res_state 0x%x\n", si_ccreg(sih, PMU_RES_STATE, 0, 0)); in si_dump_pmuregs()
6481 bcm_bprintf(b, "res_pending 0x%x\n", si_ccreg(sih, PMU_RES_PENDING, 0, 0)); in si_dump_pmuregs()
6482 bcm_bprintf(b, "pmu_timer1 %d\n", si_ccreg(sih, PMU_TIMER, 0, 0)); in si_dump_pmuregs()
6483 bcm_bprintf(b, "min_res_mask 0x%x\n", si_ccreg(sih, MINRESMASKREG, 0, 0)); in si_dump_pmuregs()
6484 bcm_bprintf(b, "max_res_mask 0x%x\n", si_ccreg(sih, MAXRESMASKREG, 0, 0)); in si_dump_pmuregs()
6490 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_chipcontrol(sih, i, 0, 0)); in si_dump_pmuregs()
6497 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_vreg_control(sih, i, 0, 0)); in si_dump_pmuregs()
6503 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_pllcontrol(sih, i, 0, 0)); in si_dump_pmuregs()
6509 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmuregs()
6510 bcm_bprintf(b, "[%d]=0x%x ", i, si_corereg(sih, SI_CC_IDX, RSRCUPDWNTIME, 0, 0)); in si_dump_pmuregs()
6516 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmuregs()
6517 bcm_bprintf(b, "[%d]=0x%x ", i, si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0)); in si_dump_pmuregs()
6523 si_dump_pcieregs(const si_t *sih, struct bcmstrbuf *b) in si_dump_pcieregs() argument
6525 const si_info_t *sii = SI_INFO(sih); in si_dump_pcieregs()
6537 si_dump(const si_t *sih, struct bcmstrbuf *b) in si_dump() argument
6539 const si_info_t *sii = SI_INFO(sih); in si_dump()
6544 OSL_OBFUSCATE_BUF(sii), sih->chip, sih->chiprev, in si_dump()
6545 sih->boardtype, sih->boardvendor, sih->bustype); in si_dump()
6549 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_dump()
6550 bcm_bprintf(b, "sonicsrev %d ", sih->socirev); in si_dump()
6552 CCREV(sih->ccrev), sih->buscoretype, sih->buscorerev, sii->curidx); in si_dump()
6555 if ((BUSTYPE(sih->bustype) == PCI_BUS) && (sii->pch)) in si_dump()
6566 si_ccreg_dump(si_t *sih, struct bcmstrbuf *b) in si_ccreg_dump() argument
6568 const si_info_t *sii = SI_INFO(sih); in si_ccreg_dump()
6575 if (CCREV(sih->ccrev) != 23) in si_ccreg_dump()
6582 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_ccreg_dump()
6585 bcm_bprintf(b, "\n===cc(rev %d) registers(offset val)===\n", CCREV(sih->ccrev)); in si_ccreg_dump()
6601 if (sih->cccaps & CC_CAP_PMU) { in si_ccreg_dump()
6608 si_setcoreidx(sih, origidx); in si_ccreg_dump()
6614 si_clkctl_dump(si_t *sih, struct bcmstrbuf *b) in si_clkctl_dump() argument
6616 const si_info_t *sii = SI_INFO(sih); in si_clkctl_dump()
6621 if (!(sih->cccaps & CC_CAP_PWR_CTL)) in si_clkctl_dump()
6626 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in si_clkctl_dump()
6631 if ((CCREV(sih->ccrev) >= 6) && (CCREV(sih->ccrev) < 10)) in si_clkctl_dump()
6633 if (CCREV(sih->ccrev) >= 10) { in si_clkctl_dump()
6638 if (BUSTYPE(sih->bustype) == PCI_BUS) in si_clkctl_dump()
6643 if (sih->cccaps & CC_CAP_PMU) { in si_clkctl_dump()
6648 si_setcoreidx(sih, origidx); in si_clkctl_dump()
6654 si_gpiodump(si_t *sih, struct bcmstrbuf *b) in si_gpiodump() argument
6656 const si_info_t *sii = SI_INFO(sih); in si_gpiodump()
6663 origidx = si_coreidx(sih); in si_gpiodump()
6665 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_gpiodump()
6680 si_setcoreidx(sih, origidx); in si_gpiodump()
6692 si_gpiosetcore(si_t *sih) in si_gpiosetcore() argument
6694 return (si_setcoreidx(sih, SI_CC_IDX)); in si_gpiosetcore()
6704 BCMPOSTTRAPFN(si_gpiocontrol)(si_t *sih, uint32 mask, uint32 val, uint8 priority) in BCMPOSTTRAPFN()
6714 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6721 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in BCMPOSTTRAPFN()
6726 BCMPOSTTRAPFN(si_gpioouten)(si_t *sih, uint32 mask, uint32 val, uint8 priority) in BCMPOSTTRAPFN()
6736 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6743 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in BCMPOSTTRAPFN()
6748 BCMPOSTTRAPFN(si_gpioout)(si_t *sih, uint32 mask, uint32 val, uint8 priority) in BCMPOSTTRAPFN()
6758 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6765 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in BCMPOSTTRAPFN()
6770 si_gpioreserve(const si_t *sih, uint32 gpio_bitmask, uint8 priority) in si_gpioreserve() argument
6775 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpioreserve()
6776 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpioreserve()
6801 si_gpiorelease(const si_t *sih, uint32 gpio_bitmask, uint8 priority) in si_gpiorelease() argument
6806 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpiorelease()
6807 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpiorelease()
6828 si_gpioin(si_t *sih) in si_gpioin() argument
6833 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0)); in si_gpioin()
6838 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpiointpolarity() argument
6843 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointpolarity()
6850 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpiointpolarity()
6855 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpiointmask() argument
6860 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointmask()
6867 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpiointmask()
6871 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpioeventintmask() argument
6875 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpioeventintmask()
6881 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpioeventintmask()
6885 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val) in si_gpiopull() argument
6889 if (CCREV(sih->ccrev) < 20) in si_gpiopull()
6893 return (si_corereg(sih, SI_CC_IDX, offs, mask, val)); in si_gpiopull()
6897 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val) in si_gpioevent() argument
6901 if (CCREV(sih->ccrev) < 11) in si_gpioevent()
6913 return (si_corereg(sih, SI_CC_IDX, offs, mask, val)); in si_gpioevent()
6917 BCMATTACHFN(si_gpio_int_enable)(si_t *sih, bool enable) in BCMATTACHFN()
6921 if (CCREV(sih->ccrev) < 11) in BCMATTACHFN()
6925 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0))); in BCMATTACHFN()
6930 si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events, in si_gci_shif_config_wake_pin() argument
6936 switch (CHIPID(sih->chip)) { in si_gci_shif_config_wake_pin()
6945 si_gci_gpio_chipcontrol(sih, gpio_n, in si_gci_shif_config_wake_pin()
6949 si_gci_gpio_intmask(sih, gpio_n, wake_events, wake_events); in si_gci_shif_config_wake_pin()
6950 si_gci_gpio_wakemask(sih, gpio_n, wake_events, wake_events); in si_gci_shif_config_wake_pin()
6953 si_gci_gpio_status(sih, gpio_n, in si_gci_shif_config_wake_pin()
6957 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, in si_gci_shif_config_wake_pin()
6963 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_intmask), in si_gci_shif_config_wake_pin()
6966 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_wakemask), in si_gci_shif_config_wake_pin()
6978 si_gci_gpio_chipcontrol(sih, gpio_n, in si_gci_shif_config_wake_pin()
6982 si_gci_gpio_intmask(sih, gpio_n, wake_events, wake_events); in si_gci_shif_config_wake_pin()
6983 si_gci_gpio_wakemask(sih, gpio_n, wake_events, wake_events); in si_gci_shif_config_wake_pin()
6986 si_gci_gpio_status(sih, gpio_n, in si_gci_shif_config_wake_pin()
6990 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, in si_gci_shif_config_wake_pin()
6996 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_intmask), in si_gci_shif_config_wake_pin()
6999 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_wakemask), in si_gci_shif_config_wake_pin()
7008 si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events, bool enable) in si_shif_int_enable() argument
7011 si_gci_gpio_intmask(sih, gpio_n, wake_events, wake_events); in si_shif_int_enable()
7012 si_gci_gpio_wakemask(sih, gpio_n, wake_events, wake_events); in si_shif_int_enable()
7014 si_gci_gpio_intmask(sih, gpio_n, wake_events, 0); in si_shif_int_enable()
7015 si_gci_gpio_wakemask(sih, gpio_n, wake_events, 0); in si_shif_int_enable()
7035 si_sysmem_size(si_t *sih) in si_sysmem_size() argument
7037 const si_info_t *sii = SI_INFO(sih); in si_sysmem_size()
7050 origidx = si_coreidx(sih); in si_sysmem_size()
7053 if (!(regs = si_setcore(sih, SYSMEM_CORE_ID, 0))) in si_sysmem_size()
7057 if (!(wasup = si_iscoreup(sih))) in si_sysmem_size()
7058 si_core_reset(sih, 0, 0); in si_sysmem_size()
7062 if (si_corerev(sih) < 12) { in si_sysmem_size()
7072 si_setcoreidx(sih, origidx); in si_sysmem_size()
7095 void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda) in si_socram_set_bankpda() argument
7097 const si_info_t *sii = SI_INFO(sih); in si_socram_set_bankpda()
7106 origidx = si_coreidx(sih); in si_socram_set_bankpda()
7109 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_set_bankpda()
7112 if (!(wasup = si_iscoreup(sih))) in si_socram_set_bankpda()
7113 si_core_reset(sih, 0, 0); in si_socram_set_bankpda()
7115 corerev = si_corerev(sih); in si_socram_set_bankpda()
7123 si_core_disable(sih, 0); in si_socram_set_bankpda()
7124 si_setcoreidx(sih, origidx); in si_socram_set_bankpda()
7132 si_socram_size(si_t *sih) in si_socram_size() argument
7134 const si_info_t *sii = SI_INFO(sih); in si_socram_size()
7146 origidx = si_coreidx(sih); in si_socram_size()
7149 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_size()
7153 if (!(wasup = si_iscoreup(sih))) in si_socram_size()
7154 si_core_reset(sih, 0, 0); in si_socram_size()
7155 corerev = si_corerev(sih); in si_socram_size()
7188 si_core_disable(sih, 0); in si_socram_size()
7189 si_setcoreidx(sih, origidx); in si_socram_size()
7199 si_is_bus_mpu_present(si_t *sih) in si_is_bus_mpu_present() argument
7204 const si_info_t *sii = SI_INFO(sih); in si_is_bus_mpu_present()
7208 origidx = si_coreidx(sih); in si_is_bus_mpu_present()
7210 cr4regs = si_setcore(sih, ARMCR4_CORE_ID, 0); in si_is_bus_mpu_present()
7215 sysmemregs = si_setcore(sih, SYSMEM_CORE_ID, 0); in si_is_bus_mpu_present()
7223 if (!(wasup = si_iscoreup(sih))) { in si_is_bus_mpu_present()
7224 si_core_reset(sih, 0, 0); in si_is_bus_mpu_present()
7235 si_core_disable(sih, 0); in si_is_bus_mpu_present()
7239 si_setcoreidx(sih, origidx); in si_is_bus_mpu_present()
7248 si_tcm_size(si_t *sih) in si_tcm_size() argument
7250 const si_info_t *sii = SI_INFO(sih); in si_tcm_size()
7269 origidx = si_coreidx(sih); in si_tcm_size()
7272 if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0))) in si_tcm_size()
7278 if (!(wasup = si_iscoreup(sih))) in si_tcm_size()
7279 si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT); in si_tcm_size()
7304 si_core_disable(sih, 0); in si_tcm_size()
7305 si_setcoreidx(sih, origidx); in si_tcm_size()
7314 si_has_flops(si_t *sih) in si_has_flops() argument
7319 origidx = si_coreidx(sih); in si_has_flops()
7320 if (si_setcore(sih, ARMCR4_CORE_ID, 0)) { in si_has_flops()
7321 cr4_rev = si_corerev(sih); in si_has_flops()
7322 si_setcoreidx(sih, origidx); in si_has_flops()
7332 si_socram_srmem_size(si_t *sih) in si_socram_srmem_size() argument
7334 const si_info_t *sii = SI_INFO(sih); in si_socram_srmem_size()
7346 origidx = si_coreidx(sih); in si_socram_srmem_size()
7349 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_srmem_size()
7353 if (!(wasup = si_iscoreup(sih))) in si_socram_srmem_size()
7354 si_core_reset(sih, 0, 0); in si_socram_srmem_size()
7355 corerev = si_corerev(sih); in si_socram_srmem_size()
7371 si_core_disable(sih, 0); in si_socram_srmem_size()
7372 si_setcoreidx(sih, origidx); in si_socram_srmem_size()
7382 BCMPOSTTRAPFN(si_seci_uart)(const si_t *sih) in BCMPOSTTRAPFN()
7384 return (sih->cccaps_ext & CC_CAP_EXT_SECI_PUART_PRESENT); in BCMPOSTTRAPFN()
7389 BCMPOSTTRAPFN(si_seci_clkreq)(si_t *sih, bool enable) in BCMPOSTTRAPFN()
7396 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
7399 chipcregs_t *cc = seci_set_core(sih, &origidx, &fast); in BCMPOSTTRAPFN()
7402 if (!si_seci(sih) && !si_seci_uart(sih)) in BCMPOSTTRAPFN()
7405 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7412 si_gci_set_functionsel(sih, fast_uart_tx, fast_uart_functionsel); in BCMPOSTTRAPFN()
7414 si_gci_set_functionsel(sih, fast_uart_rx, fast_uart_functionsel); in BCMPOSTTRAPFN()
7415 si_gci_set_functionsel(sih, fast_uart_cts_in, in BCMPOSTTRAPFN()
7435 si_gci_set_functionsel(sih, fast_uart_tx, fast_uart_pup); in BCMPOSTTRAPFN()
7438 si_gci_set_functionsel(sih, fast_uart_rx, fast_uart_pup); in BCMPOSTTRAPFN()
7439 si_gci_set_functionsel(sih, fast_uart_cts_in, fast_uart_pup); in BCMPOSTTRAPFN()
7448 si_corereg(sih, SI_CC_IDX, offset, in BCMPOSTTRAPFN()
7455 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
7458 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
7459 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
7461 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
7464 (void)si_pmu_wait_for_steady_state(sih, sii->osh, pmu); in BCMPOSTTRAPFN()
7466 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
7468 SPINWAIT(!(si_corereg(sih, 0, offset, 0, 0) & CLKCTL_STS_SECI_CLK_AVAIL), in BCMPOSTTRAPFN()
7471 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7483 BCMPOSTTRAPFN(seci_set_core)(si_t *sih, uint32 *origidx, bool *fast) in BCMPOSTTRAPFN()
7486 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
7491 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMPOSTTRAPFN()
7500 BCMPOSTTRAPFN(si_seci_access_preamble)(si_t *sih, const si_info_t *sii, uint32 *origidx, bool *fast) in BCMPOSTTRAPFN()
7502 chipcregs_t *cc = seci_set_core(sih, origidx, fast); in BCMPOSTTRAPFN()
7507 si_seci_clkreq(sih, TRUE); in BCMPOSTTRAPFN()
7516 BCMPOSTTRAPFN(si_seci_access)(si_t *sih, uint32 val, int access) in BCMPOSTTRAPFN()
7520 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
7525 if (!si_seci_uart(sih)) in BCMPOSTTRAPFN()
7529 if (!(cc = si_seci_access_preamble(sih, sii, &origidx, &fast))) in BCMPOSTTRAPFN()
7535 retval = si_corereg(sih, SI_CC_IDX, offset, ALLONES_32, val); in BCMPOSTTRAPFN()
7539 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7543 retval = si_corereg(sih, SI_CC_IDX, offset, in BCMPOSTTRAPFN()
7548 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7555 retval = si_corereg(sih, SI_CC_IDX, offset, in BCMPOSTTRAPFN()
7560 retval = si_corereg(sih, SI_CC_IDX, offset, in BCMPOSTTRAPFN()
7567 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7573 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0) & 0xff; in BCMPOSTTRAPFN()
7577 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7592 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
7599 void si_seci_clk_force(si_t *sih, bool val) in si_seci_clk_force() argument
7603 si_seci_clkreq(sih, TRUE); in si_seci_clk_force()
7605 si_seci_down(sih); in si_seci_clk_force()
7609 bool si_seci_clk_force_status(si_t *sih) in si_seci_clk_force_status() argument
7617 BCMINITFN(si_seci_init)(si_t *sih, uint8 seci_mode) in BCMINITFN()
7627 if (sih->ccrev < 35) in BCMINITFN()
7632 if (!si_seci_uart(sih)) in BCMINITFN()
7637 if (!si_seci(sih)) in BCMINITFN()
7646 sii = SI_INFO(sih); in BCMINITFN()
7650 if ((ptr = si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
7659 si_seci_clkreq(sih, TRUE); in BCMINITFN()
7688 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFF); /* 4MBaud */ in BCMINITFN()
7689 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMINITFN()
7690 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMINITFN()
7691 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMINITFN()
7692 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) { in BCMINITFN()
7695 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFE); in BCMINITFN()
7697 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44); in BCMINITFN()
7699 si_corereg(sih, SI_CC_IDX, offset, in BCMINITFN()
7703 else if (CCREV(sih->ccrev) >= 62) { in BCMINITFN()
7706 si_corereg(sih, SI_CC_IDX, offset, 0xff, 0x01); in BCMINITFN()
7708 si_corereg(sih, SI_CC_IDX, offset, SECI_UART_MCR_AUTO_RTS, in BCMINITFN()
7715 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x22); in BCMINITFN()
7717 si_corereg(sih, SI_CC_IDX, offset, in BCMINITFN()
7723 si_corereg(sih, SI_CC_IDX, offset, 0xFF, in BCMINITFN()
7726 si_corereg(sih, SI_CC_IDX, offset, in BCMINITFN()
7732 si_corereg(sih, SI_CC_IDX, offset, ALLONES_32, ECI_MACCTRLLO_BITS); in BCMINITFN()
7734 si_corereg(sih, SI_CC_IDX, offset, 0xFFFF, ECI_MACCTRLHI_BITS); in BCMINITFN()
7751 si_setcoreidx(sih, origidx); in BCMINITFN()
7757 #define NOTIFY_BT_FM_DISABLE(sih, val) \ argument
7758 si_eci_notify_bt((sih), ECI_OUT_FM_DISABLE_MASK(CCREV(sih->ccrev)), \
7759 ((val) << ECI_OUT_FM_DISABLE_SHIFT(CCREV(sih->ccrev))), FALSE)
7763 BCMINITFN(si_query_FMDisabled_from_OTP)(si_t *sih, uint16 *FMDisabled) in BCMINITFN()
7773 if (!(wasup = si_is_otp_powered(sih))) { in BCMINITFN()
7774 si_otp_power(sih, TRUE, &min_res_mask); in BCMINITFN()
7777 if ((oh = otp_init(sih)) != NULL) in BCMINITFN()
7783 si_otp_power(sih, FALSE, &min_res_mask); in BCMINITFN()
7791 si_eci(const si_t *sih) in si_eci() argument
7793 return (!!(sih->cccaps & CC_CAP_ECI)); in si_eci()
7797 BCMPOSTTRAPFN(si_seci)(const si_t *sih) in BCMPOSTTRAPFN()
7799 return (sih->cccaps_ext & CC_CAP_EXT_SECI_PRESENT); in BCMPOSTTRAPFN()
7803 si_gci(const si_t *sih) in si_gci() argument
7805 return (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT); in si_gci()
7809 si_sraon(const si_t *sih) in si_sraon() argument
7811 return (sih->cccaps_ext & CC_CAP_SR_AON_PRESENT); in si_sraon()
7816 BCMINITFN(si_eci_init)(si_t *sih) in BCMINITFN()
7825 if (!(sih->cccaps & CC_CAP_ECI)) in BCMINITFN()
7828 sii = SI_INFO(sih); in BCMINITFN()
7832 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
7839 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7849 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7859 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7870 si_setcoreidx(sih, origidx); in BCMINITFN()
7873 if (!si_query_FMDisabled_from_OTP(sih, &FMDisabled)) { in BCMINITFN()
7875 NOTIFY_BT_FM_DISABLE(sih, 1); in BCMINITFN()
7884 si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool is_interrupt) in si_eci_notify_bt() argument
7888 if ((sih->cccaps & CC_CAP_ECI) || in si_eci_notify_bt()
7889 (si_seci(sih))) in si_eci_notify_bt()
7894 si_corereg(sih, SI_CC_IDX, in si_eci_notify_bt()
7895 (CCREV(sih->ccrev) < 35 ? in si_eci_notify_bt()
7901 if (CCREV(sih->ccrev) >= 35) { in si_eci_notify_bt()
7915 si_corereg(sih, SI_CC_IDX, offset, mask, val); in si_eci_notify_bt()
7919 si_corereg(sih, SI_CC_IDX, in si_eci_notify_bt()
7920 (CCREV(sih->ccrev) < 35 ? in si_eci_notify_bt()
7925 } else if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT) { in si_eci_notify_bt()
7929 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_output[1]), mask, val); in si_eci_notify_bt()
7935 BCMPOSTTRAPFN(seci_restore_coreidx)(si_t *sih, uint32 origidx, bool fast) in BCMPOSTTRAPFN()
7938 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
7943 BCMPOSTTRAPFN(si_seci_down)(si_t *sih) in BCMPOSTTRAPFN()
7947 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
7951 if (!si_seci(sih) && !si_seci_uart(sih)) in BCMPOSTTRAPFN()
7955 if (!(si_corereg(sih, 0, offset, 0, 0) & CLKCTL_STS_SECI_CLK_REQ)) in BCMPOSTTRAPFN()
7957 if (!(cc = si_seci_access_preamble(sih, sii, &origidx, &fast))) in BCMPOSTTRAPFN()
7962 si_seci_clkreq(sih, FALSE); in BCMPOSTTRAPFN()
7965 seci_restore_coreidx(sih, origidx, fast); in BCMPOSTTRAPFN()
7969 si_seci_upd(si_t *sih, bool enable) in si_seci_upd() argument
7972 const si_info_t *sii = SI_INFO(sih); in si_seci_upd()
7978 if (!si_seci(sih)) in si_seci_upd()
7985 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in si_seci_upd()
7993 if ((CHIPID(sih->chip) == BCM4352_CHIP_ID) || (CHIPID(sih->chip) == BCM4360_CHIP_ID)) { in si_seci_upd()
8020 si_setcoreidx(sih, origidx); in si_seci_upd()
8026 BCMINITFN(si_gci_init)(si_t *sih) in BCMINITFN()
8029 const si_info_t *sii = SI_INFO(sih); in BCMINITFN()
8032 if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT) in BCMINITFN()
8034 si_gci_reset(sih); in BCMINITFN()
8036 if (sih->boardflags4 & BFL4_BTCOEX_OVER_SECI) { in BCMINITFN()
8037 si_gci_seci_init(sih); in BCMINITFN()
8043 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_control_1), in BCMINITFN()
8047 hndgci_init(sih, sii->osh, HND_GCI_PLAIN_UART_MODE, in BCMINITFN()
8065 si_btcgpiowar(si_t *sih) in si_btcgpiowar() argument
8067 const si_info_t *sii = SI_INFO(sih); in si_btcgpiowar()
8075 if (!(sih->cccaps & CC_CAP_UARTGPIO)) in si_btcgpiowar()
8081 origidx = si_coreidx(sih); in si_btcgpiowar()
8083 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_btcgpiowar()
8089 si_setcoreidx(sih, origidx); in si_btcgpiowar()
8095 si_chipcontrl_restore(si_t *sih, uint32 val) in si_chipcontrl_restore() argument
8097 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_restore()
8099 uint origidx = si_coreidx(sih); in si_chipcontrl_restore()
8101 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_restore()
8106 si_setcoreidx(sih, origidx); in si_chipcontrl_restore()
8110 si_chipcontrl_read(si_t *sih) in si_chipcontrl_read() argument
8112 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_read()
8114 uint origidx = si_coreidx(sih); in si_chipcontrl_read()
8117 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_read()
8122 si_setcoreidx(sih, origidx); in si_chipcontrl_read()
8128 si_chipcontrl_srom4360(si_t *sih, bool on) in si_chipcontrl_srom4360() argument
8130 const si_info_t *sii = SI_INFO(sih); in si_chipcontrl_srom4360()
8132 uint origidx = si_coreidx(sih); in si_chipcontrl_srom4360()
8135 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_srom4360()
8153 si_setcoreidx(sih, origidx); in si_chipcontrl_srom4360()
8161 si_srom_clk_set(si_t *sih) in si_srom_clk_set() argument
8163 const si_info_t *sii = SI_INFO(sih); in si_srom_clk_set()
8165 uint origidx = si_coreidx(sih); in si_srom_clk_set()
8169 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_srom_clk_set()
8178 si_setcoreidx(sih, origidx); in si_srom_clk_set()
8182 si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag) in si_pmu_avb_clk_set() argument
8185 switch (CHIPID(sih->chip)) { in si_pmu_avb_clk_set()
8188 si_pmu_avbtimer_enable(sih, osh, set_flag); in si_pmu_avb_clk_set()
8197 si_btc_enable_chipcontrol(si_t *sih) in si_btc_enable_chipcontrol() argument
8199 const si_info_t *sii = SI_INFO(sih); in si_btc_enable_chipcontrol()
8201 uint origidx = si_coreidx(sih); in si_btc_enable_chipcontrol()
8203 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_btc_enable_chipcontrol()
8212 si_setcoreidx(sih, origidx); in si_btc_enable_chipcontrol()
8216 void si_set_device_removed(si_t *sih, bool status) in si_set_device_removed() argument
8218 si_info_t *sii = SI_INFO(sih); in si_set_device_removed()
8225 si_deviceremoved(const si_t *sih) in si_deviceremoved() argument
8228 const si_info_t *sii = SI_INFO(sih); in si_deviceremoved()
8234 switch (BUSTYPE(sih->bustype)) { in si_deviceremoved()
8236 ASSERT(SI_INFO(sih)->osh != NULL); in si_deviceremoved()
8237 w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32)); in si_deviceremoved()
8255 si_is_sprom_available(si_t *sih) in si_is_sprom_available() argument
8257 if (CCREV(sih->ccrev) >= 31) { in si_is_sprom_available()
8263 if ((sih->cccaps & CC_CAP_SROM) == 0) in si_is_sprom_available()
8266 sii = SI_INFO(sih); in si_is_sprom_available()
8268 cc = si_setcoreidx(sih, SI_CC_IDX); in si_is_sprom_available()
8271 si_setcoreidx(sih, origidx); in si_is_sprom_available()
8275 switch (CHIPID(sih->chip)) { in si_is_sprom_available()
8277 if (CHIPREV(sih->chiprev) == 0) { in si_is_sprom_available()
8281 return (sih->chipst & CST4369_SPROM_PRESENT) != 0; in si_is_sprom_available()
8285 return (sih->chipst & CST43602_SPROM_PRESENT) != 0; in si_is_sprom_available()
8291 return (sih->chipst & CST4362_SPROM_PRESENT) != 0; in si_is_sprom_available()
8294 return (sih->chipst & CST4378_SPROM_PRESENT) != 0; in si_is_sprom_available()
8297 return (sih->chipst & CST4387_SPROM_PRESENT) != 0; in si_is_sprom_available()
8309 si_is_sflash_available(const si_t *sih) in si_is_sflash_available() argument
8311 switch (CHIPID(sih->chip)) { in si_is_sflash_available()
8313 return (sih->chipst & CST4387_SFLASH_PRESENT) != 0; in si_is_sflash_available()
8321 si_is_otp_disabled(const si_t *sih) in si_is_otp_disabled() argument
8323 switch (CHIPID(sih->chip)) { in si_is_otp_disabled()
8350 si_is_otp_powered(si_t *sih) in si_is_otp_powered() argument
8352 if (PMUCTL_ENAB(sih)) in si_is_otp_powered()
8353 return si_pmu_is_otp_powered(sih, si_osh(sih)); in si_is_otp_powered()
8358 si_otp_power(si_t *sih, bool on, uint32* min_res_mask) in si_otp_power() argument
8360 if (PMUCTL_ENAB(sih)) in si_otp_power()
8361 si_pmu_otp_power(sih, si_osh(sih), on, min_res_mask); in si_otp_power()
8367 si_cis_source(const si_t *sih) in si_cis_source() argument
8370 if (BUSTYPE(sih->bustype) == PCI_BUS) { in si_cis_source()
8374 switch (CHIPID(sih->chip)) { in si_cis_source()
8379 if ((sih->chipst & CST4360_OTP_ENABLED)) in si_cis_source()
8384 if (sih->chipst & CST43602_SPROM_PRESENT) { in si_cis_source()
8394 if (CHIPREV(sih->chiprev) == 0) { in si_cis_source()
8397 } else if (sih->chipst & CST4369_SPROM_PRESENT) { in si_cis_source()
8402 return ((sih->chipst & CST4362_SPROM_PRESENT)? CIS_SROM : CIS_OTP); in si_cis_source()
8405 if (sih->chipst & CST4378_SPROM_PRESENT) in si_cis_source()
8410 if (sih->chipst & CST4387_SPROM_PRESENT) in si_cis_source()
8423 uint16 BCMATTACHFN(si_fabid)(si_t *sih) in BCMATTACHFN()
8428 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
8442 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, fabid), 0, 0); in BCMATTACHFN()
8454 uint32 BCMATTACHFN(si_get_sromctl)(si_t *sih) in BCMATTACHFN()
8457 uint origidx = si_coreidx(sih); in BCMATTACHFN()
8459 osl_t *osh = si_osh(sih); in BCMATTACHFN()
8461 cc = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
8467 si_setcoreidx(sih, origidx); in BCMATTACHFN()
8471 int BCMATTACHFN(si_set_sromctl)(si_t *sih, uint32 value) in BCMATTACHFN()
8474 uint origidx = si_coreidx(sih); in BCMATTACHFN()
8475 osl_t *osh = si_osh(sih); in BCMATTACHFN()
8478 cc = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
8482 if (si_corerev(sih) >= 32) { in BCMATTACHFN()
8497 si_setcoreidx(sih, origidx); in BCMATTACHFN()
8503 BCMPOSTTRAPFN(si_core_wrapperreg)(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
8508 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
8510 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
8514 si_setcoreidx(sih, coreidx); in BCMPOSTTRAPFN()
8516 ret_val = si_wrapperreg(sih, offset, mask, val); in BCMPOSTTRAPFN()
8519 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
8526 si_pmu_sr_upd(si_t *sih) in si_pmu_sr_upd() argument
8530 const si_info_t *sii = SI_INFO(sih); in si_pmu_sr_upd()
8533 if (PMUCTL_ENAB(sih)) in si_pmu_sr_upd()
8534 si_pmu_res_minmax_update(sih, sii->osh); in si_pmu_sr_upd()
8544 si_update_masks(si_t *sih) in si_update_masks() argument
8546 const si_info_t *sii = SI_INFO(sih); in si_update_masks()
8548 switch (CHIPID(sih->chip)) { in si_update_masks()
8560 if (PMUCTL_ENAB(sih)) in si_update_masks()
8561 si_pmu_res_minmax_update(sih, sii->osh); in si_update_masks()
8567 si_pmu_sr_upd(sih); in si_update_masks()
8568 PMU_REG(sih, mac_res_req_timer, ~0x0, PMU43012_MAC_RES_REQ_TIMER); in si_update_masks()
8569 PMU_REG(sih, mac_res_req_mask, ~0x0, PMU43012_MAC_RES_REQ_MASK); in si_update_masks()
8579 si_force_islanding(si_t *sih, bool enable) in si_force_islanding() argument
8581 switch (CHIPID(sih->chip)) { in si_force_islanding()
8587 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x00000053, 0x0); in si_force_islanding()
8590 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000003, 0x000003); in si_force_islanding()
8594 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050); in si_force_islanding()
8598 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050); in si_force_islanding()
8617 si_pmu_res_req_timer_clr(si_t *sih) in si_pmu_res_req_timer_clr() argument
8624 pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0); in si_pmu_res_req_timer_clr()
8626 return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0); in si_pmu_res_req_timer_clr()
8631 si_pmu_rfldo(si_t *sih, bool on) in si_pmu_rfldo() argument
8634 switch (CHIPID(sih->chip)) { in si_pmu_rfldo()
8639 si_pmu_vreg_control(sih, PMU_VREG_0, RCTRL4360_RFLDO_PWR_DOWN, in si_pmu_rfldo()
8654 si_pcie_disable_oobselltr(const si_t *sih) in si_pcie_disable_oobselltr() argument
8656 ASSERT(si_coreid(sih) == PCIE2_CORE_ID); in si_pcie_disable_oobselltr()
8657 if (PCIECOREREV(sih->buscorerev) >= 23) in si_pcie_disable_oobselltr()
8658 si_wrapperreg(sih, AI_OOBSELIND74, ~0, 0); in si_pcie_disable_oobselltr()
8660 si_wrapperreg(sih, AI_OOBSELIND30, ~0, 0); in si_pcie_disable_oobselltr()
8664 si_pcie_ltr_war(const si_t *sih) in si_pcie_ltr_war() argument
8667 const si_info_t *sii = SI_INFO(sih); in si_pcie_ltr_war()
8670 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0)); in si_pcie_ltr_war()
8675 si_pcie_hw_LTR_war(const si_t *sih) in si_pcie_hw_LTR_war() argument
8678 const si_info_t *sii = SI_INFO(sih); in si_pcie_hw_LTR_war()
8686 si_pciedev_reg_pm_clk_period(const si_t *sih) in si_pciedev_reg_pm_clk_period() argument
8689 const si_info_t *sii = SI_INFO(sih); in si_pciedev_reg_pm_clk_period()
8697 si_pciedev_crwlpciegen2(const si_t *sih) in si_pciedev_crwlpciegen2() argument
8700 const si_info_t *sii = SI_INFO(sih); in si_pciedev_crwlpciegen2()
8708 si_pcie_prep_D3(const si_t *sih, bool enter_D3) in si_pcie_prep_D3() argument
8711 const si_info_t *sii = SI_INFO(sih); in si_pcie_prep_D3()
8720 BCMPOSTTRAPFN(si_corereg_ifup)(si_t *sih, uint core_id, uint regoff, uint mask, uint val) in BCMPOSTTRAPFN()
8727 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
8728 regs = si_setcore(sih, core_id, 0); in BCMPOSTTRAPFN()
8732 coreidx = si_coreidx(sih); in BCMPOSTTRAPFN()
8734 isup = si_iscoreup(sih); in BCMPOSTTRAPFN()
8736 ret_val = si_corereg(sih, coreidx, regoff, mask, val); in BCMPOSTTRAPFN()
8742 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
8750 void si_43012_lp_enable(si_t *sih) in si_43012_lp_enable() argument
8752 const si_info_t *sii = SI_INFO(sih); in si_43012_lp_enable()
8760 origidx = si_coreidx(sih); in si_43012_lp_enable()
8763 si_pmu_chipcontrol(sih, CHIPCTRLREG5, PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN, in si_43012_lp_enable()
8767 si_pmu_chipcontrol(sih, CHIPCTRLREG5, PMUCCTL05_43012_DISABLE_SPM_CLK, in si_43012_lp_enable()
8771 si_pmu_chipcontrol(sih, CHIPCTRLREG6, PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB, in si_43012_lp_enable()
8775 CHIPC_REG(sih, clk_ctl_st, CCS_SFLASH_CLKREQ | CCS_HQCLKREQ, CCS_HQCLKREQ); in si_43012_lp_enable()
8778 if (!(gciregs = si_setcore(sih, GCI_CORE_ID, 0))) { in si_43012_lp_enable()
8783 if (!(sih->lpflags & LPFLAGS_SI_GCI_FORCE_REGCLK_DISABLE)) { in si_43012_lp_enable()
8784 si_gci_direct(sih, GET_GCI_OFFSET(sih, gci_corectrl), in si_43012_lp_enable()
8789 if (!(sih->lpflags & LPFLAGS_SI_SFLASH_DISABLE)) { in si_43012_lp_enable()
8790 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, in si_43012_lp_enable()
8801 if (!(sih->lpflags & LPFLAGS_SI_BTLDO3P3_DISABLE)) { in si_43012_lp_enable()
8802 si_pmu_chipcontrol(sih, CHIPCTRLREG2, PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF, in si_43012_lp_enable()
8807 si_setcoreidx(sih, origidx); in si_43012_lp_enable()
8813 si_lowpwr_opt(si_t *sih) in si_lowpwr_opt() argument
8818 if (BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8819 uint hosti = si_chip_hostif(sih); in si_lowpwr_opt()
8820 uint origidx = si_coreidx(sih); in si_lowpwr_opt()
8823 regs = si_setcore(sih, CC_CORE_ID, 0); in si_lowpwr_opt()
8830 if (hosti != CHIP_HOSTIF_USBMODE && !BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8831 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << USBAPP_CLK_BIT), 0); in si_lowpwr_opt()
8835 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << PCIE_CLK_BIT), 0); in si_lowpwr_opt()
8841 switch (CHIPID(sih->chip)) { in si_lowpwr_opt()
8843 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, in si_lowpwr_opt()
8849 uint32 tapsel = si_corereg(sih, SI_CC_IDX, in si_lowpwr_opt()
8854 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in si_lowpwr_opt()
8860 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in si_lowpwr_opt()
8869 if (BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8873 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL4, ~0, val); in si_lowpwr_opt()
8874 si_pmu_pllupd(sih); in si_lowpwr_opt()
8875 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, in si_lowpwr_opt()
8881 si_setcoreidx(sih, origidx); in si_lowpwr_opt()
8883 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_lowpwr_opt()
8884 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_lowpwr_opt()
8885 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_lowpwr_opt()
8887 if (sih->lpflags & LPFLAGS_SI_GLOBAL_DISABLE) { in si_lowpwr_opt()
8898 si_corereg_ifup(sih, SDIOD_CORE_ID, SI_PWR_CTL_ST, mask, val); in si_lowpwr_opt()
8899 si_corereg_ifup(sih, SOCRAM_CORE_ID, SI_PWR_CTL_ST, mask, val); in si_lowpwr_opt()
8901 si_43012_lp_enable(sih); in si_lowpwr_opt()
8910 BCMPOSTTRAPFN(si_clear_backplane_to_per_core)(si_t *sih, uint coreid, uint coreunit, void * wrap) in BCMPOSTTRAPFN()
8912 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
8913 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in BCMPOSTTRAPFN()
8914 return ai_clear_backplane_to_per_core(sih, coreid, coreunit, wrap); in BCMPOSTTRAPFN()
8921 BCMPOSTTRAPFN(si_clear_backplane_to)(si_t *sih) in BCMPOSTTRAPFN()
8923 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
8924 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in BCMPOSTTRAPFN()
8925 return ai_clear_backplane_to(sih); in BCMPOSTTRAPFN()
8932 BCMATTACHFN(si_update_backplane_timeouts)(const si_t *sih, bool enable, uint32 timeout_exp, in BCMATTACHFN()
8937 if (CHIPTYPE(sih->socitype) != SOCI_AI) { in BCMATTACHFN()
8941 ai_update_backplane_timeouts(sih, enable, timeout_exp, cid); in BCMATTACHFN()
8950 si_slave_wrapper_add(si_t *sih) in si_slave_wrapper_add() argument
8956 if ((CHIPTYPE(sih->socitype) != SOCI_AI) && in si_slave_wrapper_add()
8957 (CHIPTYPE(sih->socitype) != SOCI_DVTBUS)) { in si_slave_wrapper_add()
8964 ai_update_backplane_timeouts(sih, TRUE, axi_to, 0); in si_slave_wrapper_add()
8967 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE_CORE_ID); in si_slave_wrapper_add()
8968 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE2_CORE_ID); in si_slave_wrapper_add()
8982 BCMPOSTTRAPFN(si_bpind_access)(si_t *sih, uint32 addr_high, uint32 addr_low, in BCMPOSTTRAPFN()
8991 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_addrlow), ~0, addr_low); in BCMPOSTTRAPFN()
8992 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_addrhigh), ~0, addr_high); in BCMPOSTTRAPFN()
8996 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), ~0, in BCMPOSTTRAPFN()
9000 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_data), ~0, *data); in BCMPOSTTRAPFN()
9001 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), ~0, in BCMPOSTTRAPFN()
9008 SPINWAIT(((status = si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), 0, 0)) & in BCMPOSTTRAPFN()
9022 *data = si_ccreg(sih, OFFSETOF(chipcregs_t, bp_data), 0, 0); in BCMPOSTTRAPFN()
9030 si_pll_sr_reinit(si_t *sih) in si_pll_sr_reinit() argument
9033 osl_t *osh = si_osh(sih); in si_pll_sr_reinit()
9034 const si_info_t *sii = SI_INFO(sih); in si_pll_sr_reinit()
9038 switch (CHIPID(sih->chip)) { in si_pll_sr_reinit()
9041 data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0); in si_pll_sr_reinit()
9047 si_pmu_pll_init(sih, osh, sii->xtalfreq); in si_pll_sr_reinit()
9048 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, PMU1_PLLCTL8_OPENLOOP_MASK, 0); in si_pll_sr_reinit()
9049 si_pmu_pllupd(sih); in si_pll_sr_reinit()
9057 si_pmu_init(sih, osh); in si_pll_sr_reinit()
9058 si_pmu_chip_init(sih, osh); in si_pll_sr_reinit()
9061 si_pmustatstimer_init(sih); in si_pll_sr_reinit()
9070 sr_save_restore_init(sih); in si_pll_sr_reinit()
9073 si_pmu_res_init(sih, sii->osh); in si_pll_sr_reinit()
9074 si_pmu_swreg_init(sih, osh); in si_pll_sr_reinit()
9075 si_lowpwr_opt(sih); in si_pll_sr_reinit()
9080 BCMATTACHFN(si_pll_closeloop)(si_t *sih) in BCMATTACHFN()
9088 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9095 data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0); in BCMATTACHFN()
9098 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, in BCMATTACHFN()
9100 si_pmu_pllupd(sih); in BCMATTACHFN()
9115 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, in BCMATTACHFN()
9127 BCMPOSTTRAPFN(si_introff)(const si_t *sih, bcm_int_bitmask_t *intr_val) in BCMPOSTTRAPFN()
9129 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9134 BCMPOSTTRAPFN(si_intrrestore)(const si_t *sih, bcm_int_bitmask_t *intr_val) in BCMPOSTTRAPFN()
9136 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9141 si_get_nvram_rfldo3p3_war(const si_t *sih) in si_get_nvram_rfldo3p3_war() argument
9143 const si_info_t *sii = SI_INFO(sih); in si_get_nvram_rfldo3p3_war()
9148 si_nvram_res_masks(const si_t *sih, uint32 *min_mask, uint32 *max_mask) in si_nvram_res_masks() argument
9150 const si_info_t *sii = SI_INFO(sih); in si_nvram_res_masks()
9164 si_getspurmode(const si_t *sih) in si_getspurmode() argument
9166 const si_info_t *sii = SI_INFO(sih); in si_getspurmode()
9171 si_xtalfreq(const si_t *sih) in si_xtalfreq() argument
9173 const si_info_t *sii = SI_INFO(sih); in si_xtalfreq()
9178 si_get_openloop_dco_code(const si_t *sih) in si_get_openloop_dco_code() argument
9180 const si_info_t *sii = SI_INFO(sih); in si_get_openloop_dco_code()
9185 si_set_openloop_dco_code(si_t *sih, uint32 _openloop_dco_code) in si_set_openloop_dco_code() argument
9187 si_info_t *sii = SI_INFO(sih); in si_set_openloop_dco_code()
9192 BCMPOSTTRAPFN(si_get_armpllclkfreq)(const si_t *sih) in BCMPOSTTRAPFN()
9194 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9218 BCMPOSTTRAPFN(si_get_ccidiv)(const si_t *sih) in BCMPOSTTRAPFN()
9220 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9232 BCMATTACHFN(si_wrapper_dump_buf_size)(const si_t *sih) in BCMATTACHFN()
9234 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMATTACHFN()
9235 return ai_wrapper_dump_buf_size(sih); in BCMATTACHFN()
9240 BCMPOSTTRAPFN(si_wrapper_dump_binary)(const si_t *sih, uchar *p) in BCMPOSTTRAPFN()
9242 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9243 return ai_wrapper_dump_binary(sih, p); in BCMPOSTTRAPFN()
9249 BCMPOSTTRAPFN(si_wrapper_dump_last_timeout)(const si_t *sih, uint32 *error, uint32 *core, in BCMPOSTTRAPFN()
9252 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9253 return ai_wrapper_dump_last_timeout(sih, error, core, ba, p); in BCMPOSTTRAPFN()
9261 BCMPOSTTRAPFN(si_findcoreidx_by_axiid)(const si_t *sih, uint32 axiid) in BCMPOSTTRAPFN()
9263 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9264 return ai_findcoreidx_by_axiid(sih, axiid); in BCMPOSTTRAPFN()
9269 BCMPOSTTRAPFN(si_wrapper_get_last_error)(const si_t *sih, uint32 *error_status, uint32 *core, in BCMPOSTTRAPFN()
9273 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9274 ai_wrapper_get_last_error(sih, error_status, core, lo, hi, id); in BCMPOSTTRAPFN()
9280 si_get_axi_timeout_reg(const si_t *sih) in si_get_axi_timeout_reg() argument
9283 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_get_axi_timeout_reg()
9296 #define PWRREQ_OFFSET(sih) OFFSETOF(chipcregs_t, powerctl) argument
9299 BCMPOSTTRAPFN(si_corereg_pciefast_write)(const si_t *sih, uint regoff, uint val) in BCMPOSTTRAPFN()
9302 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9304 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in BCMPOSTTRAPFN()
9313 BCMPOSTTRAPFN(si_corereg_pciefast_read)(const si_t *sih, uint regoff) in BCMPOSTTRAPFN()
9316 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9318 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in BCMPOSTTRAPFN()
9327 BCMPOSTTRAPFN(si_srpwr_request)(const si_t *sih, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
9329 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9330 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in BCMPOSTTRAPFN()
9331 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in BCMPOSTTRAPFN()
9334 volatile uint32 *fast_srpwr_addr = (volatile uint32 *)((uintptr)SI_ENUM_BASE(sih) in BCMPOSTTRAPFN()
9346 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9349 r = si_corereg_pciefast_read(sih, offset); in BCMPOSTTRAPFN()
9358 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9362 si_corereg_pciefast_write(sih, offset, r); in BCMPOSTTRAPFN()
9363 r = si_corereg_pciefast_read(sih, offset); in BCMPOSTTRAPFN()
9371 si_srpwr_stat_spinwait(sih, mask2, val2); in BCMPOSTTRAPFN()
9374 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9377 r = si_corereg_pciefast_read(sih, offset); in BCMPOSTTRAPFN()
9386 BCMPOSTTRAPFN(si_srpwr_request_on_rev80)(si_t *sih, uint32 mask, uint32 val, uint32 ucode_awake) in BCMPOSTTRAPFN()
9388 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9390 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in BCMPOSTTRAPFN()
9393 volatile uint32 *fast_srpwr_addr = (volatile uint32 *)((uintptr)SI_ENUM_BASE(sih) in BCMPOSTTRAPFN()
9400 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9403 r = si_corereg(sih, cidx, offset, 0, 0); in BCMPOSTTRAPFN()
9413 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9417 r = si_corereg(sih, cidx, offset, ~0, r); in BCMPOSTTRAPFN()
9440 si_srpwr_stat_spinwait(sih, mask2, val2); in BCMPOSTTRAPFN()
9443 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9446 r = si_corereg(sih, cidx, offset, 0, 0); in BCMPOSTTRAPFN()
9458 BCMPOSTTRAPFN(si_srpwr_stat_spinwait)(const si_t *sih, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
9460 const si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
9461 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in BCMPOSTTRAPFN()
9462 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in BCMPOSTTRAPFN()
9463 volatile uint32 *fast_srpwr_addr = (volatile uint32 *)((uintptr)SI_ENUM_BASE(sih) in BCMPOSTTRAPFN()
9476 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9482 SPINWAIT(((si_corereg_pciefast_read(sih, offset) & mask) != val), in BCMPOSTTRAPFN()
9484 r = si_corereg_pciefast_read(sih, offset) & mask; in BCMPOSTTRAPFN()
9488 r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih); in BCMPOSTTRAPFN()
9494 si_srpwr_stat(si_t *sih) in si_srpwr_stat() argument
9496 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_stat()
9497 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_stat()
9498 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_stat()
9500 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_stat()
9501 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_stat()
9503 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_stat()
9506 r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih); in si_srpwr_stat()
9512 si_srpwr_domain(si_t *sih) in si_srpwr_domain() argument
9514 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_domain()
9515 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_domain()
9516 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_domain()
9522 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_domain()
9523 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_domain()
9525 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_domain()
9534 si_srpwr_domain_wl(si_t *sih) in si_srpwr_domain_wl() argument
9540 si_srpwr_cap(si_t *sih) in si_srpwr_cap() argument
9547 return si_srpwr_domain(sih) != 0 ? TRUE : FALSE; in si_srpwr_cap()
9551 BCMPOSTTRAPFN(si_srpwr_domain_all_mask)(const si_t *sih) in BCMPOSTTRAPFN()
9558 if (si_scan_core_present(sih)) { in BCMPOSTTRAPFN()
9566 si_srpwr_bt_status(si_t *sih) in si_srpwr_bt_status() argument
9569 uint32 offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_bt_status()
9570 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_bt_status()
9571 uint32 cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_bt_status()
9573 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_bt_status()
9574 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_bt_status()
9576 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_bt_status()
9587 si_raw_reg(const si_t *sih, uint32 reg, uint32 val, uint32 wrire_req) in si_raw_reg() argument
9589 const si_info_t *sii = SI_INFO(sih); in si_raw_reg()
9600 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_raw_reg()
9605 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_raw_reg()
9654 BCMPOSTTRAPFN(si_check_enable_backplane_log)(const si_t *sih) in BCMPOSTTRAPFN()
9656 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in BCMPOSTTRAPFN()
9657 return ai_check_enable_backplane_log(sih); in BCMPOSTTRAPFN()
9664 si_lhl_ps_mode(const si_t *sih) in si_lhl_ps_mode() argument
9666 const si_info_t *sii = SI_INFO(sih); in si_lhl_ps_mode()
9671 si_hib_ext_wakeup_isenab(const si_t *sih) in si_hib_ext_wakeup_isenab() argument
9673 const si_info_t *sii = SI_INFO(sih); in si_hib_ext_wakeup_isenab()
9678 BCMATTACHFN(si_oob_war_BT_F1)(si_t *sih) in BCMATTACHFN()
9680 uint origidx = si_coreidx(sih); in BCMATTACHFN()
9686 regs = si_setcore(sih, AXI2AHB_BRIDGE_ID, 0); in BCMATTACHFN()
9690 si_wrapperreg(sih, AI_OOBSELINA30, 0xF00, 0x300); in BCMATTACHFN()
9692 si_setcoreidx(sih, origidx); in BCMATTACHFN()
9735 si_rffe_rfem_init(si_t *sih) in si_rffe_rfem_init() argument
9737 ASSERT(GCI_OFFSETOF(sih, gci_chipctrl) == OFFSETOF(gciregs_t, gci_chipctrl)); in si_rffe_rfem_init()
9741 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_15, ALLONES_32, 0x60000000); in si_rffe_rfem_init()
9745 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_23, 0x3 << 29, 0x3 << 29); in si_rffe_rfem_init()
9747 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_clk_ctrl), ALLONES_32, 0x101); in si_rffe_rfem_init()
9750 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlmc), ALLONES_32, 0); in si_rffe_rfem_init()
9751 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlac), ALLONES_32, 0); in si_rffe_rfem_init()
9752 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlsc), ALLONES_32, 0); in si_rffe_rfem_init()
9753 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_btmc), ALLONES_32, 0); in si_rffe_rfem_init()
9754 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_btsc), ALLONES_32, 0); in si_rffe_rfem_init()
9761 if (sih->ccrev == 68) { in si_rffe_rfem_init()
9762 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_misc_ctrl), ALLONES_32, 0x0016EC72); in si_rffe_rfem_init()
9764 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_misc_ctrl), ALLONES_32, 0x0016EC32); in si_rffe_rfem_init()
9770 if (sih->ccrev >= 71) { in si_rffe_rfem_init()
9771 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_clk_ctrl), in si_rffe_rfem_init()
9776 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, ALLONES_32, ANTENNA_0_ENABLE); in si_rffe_rfem_init()
9777 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, ALLONES_32, ANTENNA_1_ENABLE); in si_rffe_rfem_init()
9781 si_rffe_set_debug_mode(si_t *sih, bool enable) in si_rffe_set_debug_mode() argument
9788 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_misc_ctrl), RFFE_MISC_EN_PHYCYCLES, in si_rffe_set_debug_mode()
9791 sih->rffe_debug_mode = enable; in si_rffe_set_debug_mode()
9795 si_rffe_get_debug_mode(si_t *sih) in si_rffe_get_debug_mode() argument
9797 return sih->rffe_debug_mode; in si_rffe_get_debug_mode()
9801 si_rffe_get_elnabyp_mode(si_t *sih) in si_rffe_get_elnabyp_mode() argument
9803 return sih->rffe_elnabyp_mode; in si_rffe_get_elnabyp_mode()
9807 si_rffe_set_elnabyp_mode(si_t *sih, uint8 mode) in si_rffe_set_elnabyp_mode() argument
9847 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_14, RF_SW_CTRL_ELNABYP_ANT_MASK, in si_rffe_set_elnabyp_mode()
9849 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_15, RF_SW_CTRL_ELNABYP_ANT_MASK, in si_rffe_set_elnabyp_mode()
9852 sih->rffe_elnabyp_mode = mode; in si_rffe_set_elnabyp_mode()
9858 BCMPOSTTRAPFN(si_rffe_rfem_read)(si_t *sih, uint8 dev_id, uint8 antenna, uint16 reg_addr, in BCMPOSTTRAPFN()
9863 uint32 gci_rffe_ctrl = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0); in BCMPOSTTRAPFN()
9864 uint32 gci_chipcontrol_03 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, 0, 0); in BCMPOSTTRAPFN()
9865 uint32 gci_chipcontrol_02 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, 0, 0); in BCMPOSTTRAPFN()
9867 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, 0); in BCMPOSTTRAPFN()
9885 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_config), ALLONES_32, in BCMPOSTTRAPFN()
9887 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_rfem_addr), ALLONES_32, reg_addr); in BCMPOSTTRAPFN()
9888 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, ANTENNA_0_ENABLE, antenna_0_enable); in BCMPOSTTRAPFN()
9889 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, ANTENNA_1_ENABLE, antenna_1_enable); in BCMPOSTTRAPFN()
9891 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), in BCMPOSTTRAPFN()
9894 SPINWAIT(si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9896 if (si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9901 *val = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_rfem_data0), 0, 0); in BCMPOSTTRAPFN()
9903 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), in BCMPOSTTRAPFN()
9909 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, gci_rffe_ctrl); in BCMPOSTTRAPFN()
9910 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, ALLONES_32, gci_chipcontrol_03); in BCMPOSTTRAPFN()
9911 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, ALLONES_32, gci_chipcontrol_02); in BCMPOSTTRAPFN()
9916 BCMPOSTTRAPFN(si_rffe_rfem_write)(si_t *sih, uint8 dev_id, uint8 antenna, uint16 reg_addr, in BCMPOSTTRAPFN()
9921 uint32 gci_rffe_ctrl = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0); in BCMPOSTTRAPFN()
9922 uint32 gci_chipcontrol_03 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, 0, 0); in BCMPOSTTRAPFN()
9923 uint32 gci_chipcontrol_02 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, 0, 0); in BCMPOSTTRAPFN()
9924 uint8 repeat = (sih->ccrev == 69) ? 2 : 1; /* WAR for 4387c0 */ in BCMPOSTTRAPFN()
9926 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, 0); in BCMPOSTTRAPFN()
9946 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_config), ALLONES_32, in BCMPOSTTRAPFN()
9948 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_rfem_addr), ALLONES_32, reg_addr); in BCMPOSTTRAPFN()
9949 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, ANTENNA_0_ENABLE, antenna_0_enable); in BCMPOSTTRAPFN()
9950 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, ANTENNA_1_ENABLE, antenna_1_enable); in BCMPOSTTRAPFN()
9951 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_rfem_data0), ALLONES_32, data); in BCMPOSTTRAPFN()
9954 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), RFFE_CTRL_START | in BCMPOSTTRAPFN()
9957 SPINWAIT(si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9959 if (si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9968 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, gci_rffe_ctrl); in BCMPOSTTRAPFN()
9969 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, ALLONES_32, gci_chipcontrol_03); in BCMPOSTTRAPFN()
9970 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, ALLONES_32, gci_chipcontrol_02); in BCMPOSTTRAPFN()
9977 si_chipcap_sdio_ate_only(const si_t *sih) in si_chipcap_sdio_ate_only() argument
9980 switch (CHIPID(sih->chip)) { in si_chipcap_sdio_ate_only()
9982 if (CST4369_CHIPMODE_SDIOD(sih->chipst) && in si_chipcap_sdio_ate_only()
9983 CST4369_CHIPMODE_PCIE(sih->chipst)) { in si_chipcap_sdio_ate_only()
9997 if (CST4362_CHIPMODE_SDIOD(sih->chipst) && in si_chipcap_sdio_ate_only()
9998 CST4362_CHIPMODE_PCIE(sih->chipst)) { in si_chipcap_sdio_ate_only()
10011 si_dump_APB_Bridge_registers(const si_t *sih) in si_dump_APB_Bridge_registers() argument
10013 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_dump_APB_Bridge_registers()
10014 ai_dump_APB_Bridge_registers(sih); in si_dump_APB_Bridge_registers()
10020 si_force_clocks(const si_t *sih, uint clock_state) in si_force_clocks() argument
10022 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_force_clocks()
10023 ai_force_clocks(sih, clock_state); in si_force_clocks()
10041 si_set_slice_id(si_t *sih, uint8 slice) in si_set_slice_id() argument
10043 si_info_t *sii = SI_INFO(sih); in si_set_slice_id()
10049 si_get_slice_id(const si_t *sih) in si_get_slice_id() argument
10051 const si_info_t *sii = SI_INFO(sih); in si_get_slice_id()
10057 BCMPOSTTRAPRAMFN(si_scan_core_present)(const si_t *sih) in BCMPOSTTRAPRAMFN()
10059 return (si_numcoreunits(sih, D11_CORE_ID) > 2); in BCMPOSTTRAPRAMFN()
10064 si_btc_bt_status_in_reset(si_t *sih) in si_btc_bt_status_in_reset() argument
10067 switch (CHIPID(sih->chip)) { in si_btc_bt_status_in_reset()
10069 chipst = si_corereg(sih, SI_CC_IDX, in si_btc_bt_status_in_reset()
10082 si_btc_bt_status_in_pds(si_t *sih) in si_btc_bt_status_in_pds() argument
10084 return !((si_gci_chipstatus(sih, GCI_CHIPSTATUS_04) >> in si_btc_bt_status_in_pds()
10089 si_btc_bt_pds_wakeup_force(si_t *sih, bool force) in si_btc_bt_pds_wakeup_force() argument
10092 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, in si_btc_bt_pds_wakeup_force()
10094 SPINWAIT((si_btc_bt_status_in_pds(sih) == TRUE), PMU_MAX_TRANSITION_DLY); in si_btc_bt_pds_wakeup_force()
10095 if (si_btc_bt_status_in_pds(sih) == TRUE) { in si_btc_bt_pds_wakeup_force()
10103 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, PMU_CC0_4387_BT_PU_WAKE_MASK, 0); in si_btc_bt_pds_wakeup_force()
10113 BCMATTACHFN(si_core_d11_type)(si_t *sih, uint coreunit) in BCMATTACHFN()
10124 coreidx = si_coreidx(sih); in BCMATTACHFN()
10125 regs = si_setcore(sih, D11_CORE_ID, coreunit); in BCMATTACHFN()
10129 coretype = (si_core_sflags(sih, 0, 0) & SISF_CORE_BITS_SCAN) != 0 ? in BCMATTACHFN()
10132 si_setcoreidx(sih, coreidx); in BCMATTACHFN()
10139 BCMATTACHFN(si_pkgopt_d11_allowed)(si_t *sih, uint coreunit) in BCMATTACHFN()
10145 coreidx = si_coreidx(sih); in BCMATTACHFN()
10146 regs = si_setcore(sih, D11_CORE_ID, coreunit); in BCMATTACHFN()
10150 allowed = ((si_core_sflags(sih, 0, 0) & SISF_CORE_BITS_SCAN) == 0 || in BCMATTACHFN()
10151 (si_gci_chipstatus(sih, GCI_CHIPSTATUS_09) & GCI_CST9_SCAN_DIS) == 0); in BCMATTACHFN()
10153 si_setcoreidx(sih, coreidx); in BCMATTACHFN()
10158 si_configure_pwrthrottle_gpio(si_t *sih, uint8 pwrthrottle_gpio_in) in si_configure_pwrthrottle_gpio() argument
10161 if (CHIPID(sih->chip) == BCM4369_CHIP_ID || CHIPID(sih->chip) == BCM4377_CHIP_ID) { in si_configure_pwrthrottle_gpio()
10162 si_gci_set_functionsel(sih, pwrthrottle_gpio_in, 1); in si_configure_pwrthrottle_gpio()
10165 si_gpiocontrol(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_pwrthrottle_gpio()
10166 si_gpioouten(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_pwrthrottle_gpio()
10170 si_configure_onbody_gpio(si_t *sih, uint8 onbody_gpio_in) in si_configure_onbody_gpio() argument
10173 if (CHIPID(sih->chip) == BCM4369_CHIP_ID || CHIPID(sih->chip) == BCM4377_CHIP_ID) { in si_configure_onbody_gpio()
10174 si_gci_set_functionsel(sih, onbody_gpio_in, 1); in si_configure_onbody_gpio()
10177 si_gpiocontrol(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_onbody_gpio()
10178 si_gpioouten(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_onbody_gpio()
10184 si_jtag_udr_pwrsw_main_toggle(si_t *sih, bool on) in si_jtag_udr_pwrsw_main_toggle() argument
10189 switch (CHIPID(sih->chip)) { in si_jtag_udr_pwrsw_main_toggle()
10191 jtag_setbit_128(sih, 8, 99, val); in si_jtag_udr_pwrsw_main_toggle()
10192 jtag_setbit_128(sih, 8, 101, val); in si_jtag_udr_pwrsw_main_toggle()
10193 jtag_setbit_128(sih, 8, 105, val); in si_jtag_udr_pwrsw_main_toggle()
10205 BCMATTACHFN(si_d11_core_sssr_addr)(si_t *sih, uint unit, uint32 *sssr_size) in BCMATTACHFN()
10210 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
10232 si_cur_hib_time(si_t *sih) in si_cur_hib_time() argument
10236 hib_time = LHL_REG(sih, lhl_hibtim_adr, 0, 0); in si_cur_hib_time()
10243 if (hib_time != LHL_REG(sih, lhl_hibtim_adr, 0, 0)) { in si_cur_hib_time()
10244 hib_time = LHL_REG(sih, lhl_hibtim_adr, 0, 0); in si_cur_hib_time()