902 			si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT),  in BCMATTACHFN()
930 	pmu_chipcontrol = si_pmu_chipcontrol(sih, 1, 0, 0);  in BCMATTACHFN()
1036 	si_pmu_chipcontrol(sih, 1, ~0, pmu_chipcontrol);  in BCMATTACHFN()
1405 	si_pmu_chipcontrol(sih, PMU_CHIPCTL2, pmu_cc2_mask, pmu_cc2_value);  in BCMINITFN()
1430 	pmu_chipcontrol2 = si_pmu_chipcontrol(sih, PMU_CHIPCTL2, 0, 0);  in BCMPOSTTRAPFN()
1432 	si_pmu_chipcontrol(sih, PMU_CHIPCTL2, ~0, pmu_chipcontrol2);  in BCMPOSTTRAPFN()
5665 		pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0);  in si_dump_pmu()
5764 		si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x003c0000, j);  in si_power_island_set()
5781 	reg_val = si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0, 0);  in si_power_island_get()
6490 		bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_chipcontrol(sih, i, 0, 0));  in si_dump_pmuregs()
6957 				si_pmu_chipcontrol(sih, PMU_CHIPCTL2,  in si_gci_shif_config_wake_pin()
6990 				si_pmu_chipcontrol(sih, PMU_CHIPCTL2,  in si_gci_shif_config_wake_pin()
8587 			si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x00000053, 0x0);  in si_force_islanding()
8590 			si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000003, 0x000003);  in si_force_islanding()
8594 			si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050);  in si_force_islanding()
8598 			si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050);  in si_force_islanding()
8763 	si_pmu_chipcontrol(sih, CHIPCTRLREG5, PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN,  in si_43012_lp_enable()
8767 	si_pmu_chipcontrol(sih, CHIPCTRLREG5, PMUCCTL05_43012_DISABLE_SPM_CLK,  in si_43012_lp_enable()
8771 	si_pmu_chipcontrol(sih, CHIPCTRLREG6, PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB,  in si_43012_lp_enable()
8802 		si_pmu_chipcontrol(sih, CHIPCTRLREG2, PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF,  in si_43012_lp_enable()
8831 			si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << USBAPP_CLK_BIT), 0);  in si_lowpwr_opt()
8835 			si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << PCIE_CLK_BIT), 0);  in si_lowpwr_opt()
8843 				si_pmu_chipcontrol(sih, PMU_CHIPCTL3,  in si_lowpwr_opt()
8854 					si_pmu_chipcontrol(sih, PMU_CHIPCTL5,  in si_lowpwr_opt()
8860 				si_pmu_chipcontrol(sih, PMU_CHIPCTL5,  in si_lowpwr_opt()
8875 			si_pmu_chipcontrol(sih, PMU_CHIPCTL2,  in si_lowpwr_opt()
9115 			si_pmu_chipcontrol(sih, PMU_CHIPCTL1,  in BCMATTACHFN()
10092 		si_pmu_chipcontrol(sih, PMU_CHIPCTL0,  in si_btc_bt_pds_wakeup_force()
10103 		si_pmu_chipcontrol(sih, PMU_CHIPCTL0, PMU_CC0_4387_BT_PU_WAKE_MASK, 0);  in si_btc_bt_pds_wakeup_force()