5653 	pmu_reg_t *pmu_var = (pmu_reg_t*)arg;  in si_dump_pmu()  local
5654 	pmu_var->pmu_control = si_ccreg(sih, PMU_CTL, 0, 0);  in si_dump_pmu()
5655 	pmu_var->pmu_capabilities = si_ccreg(sih, PMU_CAP, 0, 0);  in si_dump_pmu()
5656 	pmu_var->pmu_status = si_ccreg(sih, PMU_ST, 0, 0);  in si_dump_pmu()
5657 	pmu_var->res_state = si_ccreg(sih, PMU_RES_STATE, 0, 0);  in si_dump_pmu()
5658 	pmu_var->res_pending = si_ccreg(sih, PMU_RES_PENDING, 0, 0);  in si_dump_pmu()
5659 	pmu_var->pmu_timer1 = si_ccreg(sih, PMU_TIMER, 0, 0);  in si_dump_pmu()
5660 	pmu_var->min_res_mask = si_ccreg(sih, MINRESMASKREG, 0, 0);  in si_dump_pmu()
5661 	pmu_var->max_res_mask = si_ccreg(sih, MAXRESMASKREG, 0, 0);  in si_dump_pmu()
5662 	pmu_chip_ctl_reg = (pmu_var->pmu_capabilities & 0xf8000000);  in si_dump_pmu()
5665 		pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0);  in si_dump_pmu()
5667 	pmu_chip_reg_reg = (pmu_var->pmu_capabilities & 0x07c00000);  in si_dump_pmu()
5670 		pmu_var->pmu_regcontrol[i] = si_pmu_vreg_control(sih, i, 0, 0);  in si_dump_pmu()
5672 	pmu_chip_pll_reg = (pmu_var->pmu_capabilities & 0x003e0000);  in si_dump_pmu()
5675 		pmu_var->pmu_pllcontrol[i] = si_pmu_pllcontrol(sih, i, 0, 0);  in si_dump_pmu()
5677 	pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00);  in si_dump_pmu()
5681 		pmu_var->pmu_rsrc_up_down_timer[i] = si_corereg(sih, SI_CC_IDX,  in si_dump_pmu()
5684 	pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00);  in si_dump_pmu()
5688 		pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0);  in si_dump_pmu()