Lines Matching refs:clk_ctl_st
907 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, in BCMATTACHFN()
3241 CHIPC_REG(sih, clk_ctl_st, CCS_SFLASH_CLKREQ, 0); in BCMATTACHFN()
5340 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT); in _si_clkctl_cc()
5346 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0), in _si_clkctl_cc()
5348 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); in _si_clkctl_cc()
5369 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); in _si_clkctl_cc()
5375 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0), in _si_clkctl_cc()
5377 ASSERT(!(R_REG(sii->osh, &cc->clk_ctl_st) & htavail)); in _si_clkctl_cc()
7391 uint32 clk_ctl_st; in BCMPOSTTRAPFN() local
7404 offset = OFFSETOF(chipcregs_t, clk_ctl_st); in BCMPOSTTRAPFN()
7405 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7407 if (enable && !(clk_ctl_st & CLKCTL_STS_SECI_CLK_REQ)) { in BCMPOSTTRAPFN()
7420 } else if (!enable && (clk_ctl_st & CLKCTL_STS_SECI_CLK_REQ)) { in BCMPOSTTRAPFN()
7471 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7473 if (!(clk_ctl_st & CLKCTL_STS_SECI_CLK_AVAIL)) { in BCMPOSTTRAPFN()
7505 if (((R_REG(sii->osh, &cc->clk_ctl_st) & CCS_SECICLKREQ) != CCS_SECICLKREQ)) { in BCMPOSTTRAPFN()
7954 offset = OFFSETOF(chipcregs_t, clk_ctl_st); in BCMPOSTTRAPFN()
8775 CHIPC_REG(sih, clk_ctl_st, CCS_SFLASH_CLKREQ | CCS_HQCLKREQ, CCS_HQCLKREQ); in si_43012_lp_enable()