354 		SI_MSG(("si_kattach done. ccrev = %d, wd_msticks = %d\n",  in BCMATTACHFN()
428 		SI_MSG(("F0 REG0 rd = 0x%x\n", regdata));  in BCMATTACHFN()
450 	SI_MSG(("si_get_pmu_reg_addr: pmu access, offset: %x\n", offset));  in si_get_pmu_reg_addr()
457 		SI_MSG(("si_get_pmu_reg_addr: AOBENAB: %x\n", offset));  in si_get_pmu_reg_addr()
470 	SI_MSG(("%s: addrRET: %x\n", __FUNCTION__, pmuaddr));  in si_get_pmu_reg_addr()
539 	SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",  in BCMATTACHFN()
914 			SI_MSG(("si_swdenable: set arm_dbgclk, ForceHTClock and tap_sel bit\n"));  in BCMATTACHFN()
989 				SI_MSG(("si_muxenab: Invalid uart OTP setting\n"));  in BCMATTACHFN()
1151 	SI_MSG(("si_gci_gpio_chipcontrol:rngidx is %d, pos is %d, opt is %d, mask is 0x%04x,"  in BCMPOSTTRAPFN()
1168 	SI_MSG(("si_gci_gpio_reg:rngidx is %d, pos is %d, val is %d, mask is 0x%04x,"  in BCMPOSTTRAPFN()
1200 	SI_MSG(("si_gci_enable_gpio:rngidx is %d, pos is %d, val is %d, mask is 0x%04x,"  in BCMPOSTTRAPFN()
1614 	SI_MSG(("si_gci_gpioint_handler_register: gci_gpio  is %d\n", gci_gpio));  in si_gci_gpioint_handler_register()
1673 	SI_MSG(("si_gci_gpioint_handler_process: status 0x%04x, 0x%04x\n",  in si_gci_gpioint_handler_process()
1700 		SI_MSG(("si_gci_handler_process: gci_intstatus is 0x%04x\n", gci_intstatus));  in si_gci_handler_process()
2460 	SI_MSG(("si_gci_get_chipctrlreg_ringidx_base4:%d:%d:%d\n", pin, *regidx, *pos));  in BCMPOSTTRAPFN()
2474 	SI_MSG(("si_gci_get_chipctrlreg_ringidx_base8:%d:%d:%d\n", pin, *regidx, *pos));  in BCMPOSTTRAPFN()
2485 	SI_MSG(("si_gci_set_functionsel:%d\n", pin));  in BCMPOSTTRAPFN()
2497 	SI_MSG(("si_gci_get_functionsel: %d\n", pin));  in si_gci_get_functionsel()
2509 	SI_MSG(("si_gci_clear_functionsel: %d\n", fnsel));  in si_gci_clear_functionsel()
2847 			SI_MSG(("Found chip type SB (0x%08x)\n", w));  in BCMATTACHFN()
2854 				SI_MSG(("Found chip type AI (0x%08x)\n", w));  in BCMATTACHFN()
2856 				SI_MSG(("Found chip type NAI (0x%08x)\n", w));  in BCMATTACHFN()
2858 				SI_MSG(("Found chip type DVT (0x%08x)\n", w));  in BCMATTACHFN()
2873 			SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip));  in BCMATTACHFN()
5891 		SI_MSG(("si_sdio_init: For SDIO Corerev %d, enable ints from core %d "  in si_sdio_init()
6213 			SI_MSG(("si_pcie_setup: arm core not found\n"));  in BCMATTACHFN()
6224 			SI_MSG(("si_pcie_setup: coreidx %u main (=%d) or "  in BCMATTACHFN()
8888 			SI_MSG(("si_lowpwr_opt: Disable lower power configuration!\n"));  in si_lowpwr_opt()
8892 		SI_MSG(("si_lowpwr_opt: Enable lower power configuration!\n"));  in si_lowpwr_opt()
9153 		SI_MSG(("Applying rmin=%d to min_mask\n", sii->nvram_min_mask));  in si_nvram_res_masks()
9158 		SI_MSG(("Applying rmax=%d to max_mask\n", sii->nvram_max_mask));  in si_nvram_res_masks()
9211 	SI_MSG(("armpllclkfreq = %d\n", armpllclkfreq));  in BCMPOSTTRAPFN()