Lines Matching refs:SI_ERROR
281 SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh))); in BCMATTACHFN()
287 SI_ERROR(("si_dvfs_info_init failed\n")); in BCMATTACHFN()
332 SI_ERROR(("si_kattach: si_doattach failed\n")); in BCMATTACHFN()
402 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", in BCMATTACHFN()
514 SI_ERROR(("si_buscore_setup: si_findcoreidx failed\n")); in BCMATTACHFN()
671 SI_ERROR(("si_buscore_setup: si_pci_fixcfg failed\n")); in BCMATTACHFN()
779 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", in BCMATTACHFN()
788 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", in BCMATTACHFN()
835 SI_ERROR(("si_doattach: unknown board type\n")); in BCMATTACHFN()
957 SI_ERROR(("si_muxenab: wrong index %d for hostwake\n", in BCMATTACHFN()
1002 SI_ERROR(("si_muxenab: wrong index %d for hostwake\n", in BCMATTACHFN()
1297 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMPOSTTRAPFN()
1316 SI_ERROR(("Time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_gci_time_sync_gpio_enable()
1348 SI_ERROR(("time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1473 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1548 SI_ERROR(("0x%04x: don't know about device_wake_opt %d\n", in si_enable_device_wake()
1553 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_enable_device_wake()
1572 SI_ERROR(("si_gci_gpioint_handler_unregister: not GCI capable\n")); in si_gci_gpioint_handler_unregister()
1610 SI_ERROR(("si_gci_gpioint_handler_register: not GCI capable\n")); in si_gci_gpioint_handler_register()
1616 SI_ERROR(("isi_gci_gpioint_handler_register: Invalid GCI GPIO NUM %d\n", gci_gpio)); in si_gci_gpioint_handler_register()
1624 SI_ERROR(("si_gci_gpioint_handler_register: GCI Item MALLOC failure\n")); in si_gci_gpioint_handler_register()
1811 SI_ERROR(("si_wci2_rxfifo_handler_register: not GCI capable\n")); in si_wci2_rxfifo_handler_register()
1817 SI_ERROR(("si_wci2_rxfifo_handler_register: WCI2 RXFIFO INFO MALLOC failure\n")); in si_wci2_rxfifo_handler_register()
1824 SI_ERROR(("si_wci2_rxfifo_handler_register: WCI2 RXFIFO INFO MALLOC failure\n")); in si_wci2_rxfifo_handler_register()
1832 SI_ERROR(("si_wci2_rxfifo_handler_register: WCI2 RXFIFO INFO MALLOC failure\n")); in si_wci2_rxfifo_handler_register()
1856 SI_ERROR(("si_wci2_rxfifo_handler_unregister: not GCI capable\n")); in si_wci2_rxfifo_handler_unregister()
1895 SI_ERROR(("*** rx fifo overflow *** \n")); in si_wci2_rxfifo_intr_handler_process()
2662 SI_ERROR(("si_attach: malloc failed for cores_info! malloced" in BCMATTACHFN()
2729 SI_ERROR(("si_doattach: %zu bytes MALLOC FAILED", in BCMATTACHFN()
2741 SI_ERROR(("si_doattach: incoming bus is PCI but it's a lie, switching to SI " in BCMATTACHFN()
2769 SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n", in BCMATTACHFN()
2778 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", bustype)); in BCMATTACHFN()
2867 SI_ERROR(("FATAL: Wrapper count 0\n")); in BCMATTACHFN()
2877 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w)); in BCMATTACHFN()
2954 SI_ERROR(("si_doattach: nvram_init failed \n")); in BCMATTACHFN()
3302 SI_ERROR(("si_doattach Failed. Error at %d\n", err_at)); in BCMATTACHFN()
3396 SI_ERROR(("osh is already set....\n")); in si_setosh()
4126 SI_ERROR(("Valid only for pcie bus \n")); in si_backplane_access()
4174 SI_ERROR(("Invalid size %d \n", size)); in si_backplane_access()
4190 SI_ERROR(("NDIS/EFI won't support 64 bit access\n")); in si_backplane_access_64()
4199 SI_ERROR(("Valid only for pcie bus \n")); in si_backplane_access_64()
4209 SI_ERROR(("Address is not aligned\n")); in si_backplane_access_64()
4235 SI_ERROR(("Invalid size %d \n", size)); in si_backplane_access_64()
5021 SI_ERROR(("si_viewall: num_cores %d\n", sii->numcores)); in si_viewall()
5420 SI_ERROR(("si_devpath: device 0 assumed\n")); in BCMNMIATTACHFN()
5805 SI_ERROR(("si_pciereg: Not a PCIE device\n")); in si_pciereg()
5818 SI_ERROR(("si_pcieserdesreg: Not a PCIE device\n")); in si_pcieserdesreg()
7474 SI_ERROR(("SECI clock is not available\n")); in BCMPOSTTRAPFN()
8102 SI_ERROR(("si_chipcontrl_restore: Failed to find CORE ID!\n")); in si_chipcontrl_restore()
8118 SI_ERROR(("si_chipcontrl_read: Failed to find CORE ID!\n")); in si_chipcontrl_read()
8136 SI_ERROR(("si_chipcontrl_srom4360: Failed to find CORE ID!\n")); in si_chipcontrl_srom4360()
8170 SI_ERROR(("si_srom_clk_set: Failed to find CORE ID!\n")); in si_srom_clk_set()
8204 SI_ERROR(("si_btc_enable_chipcontrol: Failed to find CORE ID!\n")); in si_btc_enable_chipcontrol()
9013 SI_ERROR(("Action Failed for address 0x%08x:0x%08x \t status: 0x%x\n", in BCMPOSTTRAPFN()
10096 SI_ERROR(("si_btc_bt_pds_wakeup_force" in si_btc_bt_pds_wakeup_force()
10196 SI_ERROR(("si_jtag_udr_pwrsw_main_toggle: add support for this chip!\n")); in si_jtag_udr_pwrsw_main_toggle()