Lines Matching refs:R_REG

497 		sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);  in BCMATTACHFN()
500 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); in BCMATTACHFN()
504 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); in BCMATTACHFN()
519 sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities); in BCMATTACHFN()
534 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); in BCMATTACHFN()
2792 w = R_REG(osh, &cc->chipid); in BCMATTACHFN()
2898 capabilities = R_REG(osh, &cc->capabilities); in BCMATTACHFN()
2901 sromprsnt = R_REG(osh, &cc->sromcontrol); in BCMATTACHFN()
2905 clkdiv2 = (R_REG(osh, &cc->clkdiv2) & ~CLKD2_SROM); in BCMATTACHFN()
3439 return R_REG(sii->osh, ((uint32 *)(uintptr) in BCMPOSTTRAPFN()
4157 *val = R_REG(sii->osh, (volatile uint8*)r); in si_backplane_access()
4163 *val = R_REG(sii->osh, (volatile uint16*)r); in si_backplane_access()
4169 *val = R_REG(sii->osh, (volatile uint32*)r); in si_backplane_access()
4229 *val = R_REG(sii->osh, (volatile uint64*)r); in si_backplane_access_64()
4642 n = R_REG(sii->osh, &cc->clockcontrol_n); in BCMINITFN()
4645 m = R_REG(sii->osh, &cc->clockcontrol_m3); in BCMINITFN()
4647 m = R_REG(sii->osh, &cc->clockcontrol_m2); in BCMINITFN()
4649 m = R_REG(sii->osh, &cc->clockcontrol_sb); in BCMINITFN()
5050 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK); in si_slowclk_src()
5065 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); in si_slowclk_freq()
5075 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1); in si_slowclk_freq()
5086 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; in si_slowclk_freq()
5194 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) + in BCMINITFN()
5346 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0), in _si_clkctl_cc()
5348 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); in _si_clkctl_cc()
5356 scc = R_REG(sii->osh, &cc->slow_clk_ctl); in _si_clkctl_cc()
5375 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0), in _si_clkctl_cc()
5377 ASSERT(!(R_REG(sii->osh, &cc->clk_ctl_st) & htavail)); in _si_clkctl_cc()
5703 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on()
5707 max_res_mask = R_REG(sii->osh, &cc->max_res_mask); in si_pmu_keep_on()
5724 min_res_mask = R_REG(sii->osh, &cc->min_res_mask); in si_pmu_keep_on_get()
5728 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on_get()
6148 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6150 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6437 val16 = R_REG(sii->osh, reg16); in si_pci_fixcfg()
6670 bcm_bprintf(b, "gpioin 0x%x ", R_REG(sii->osh, &cc->gpioin)); in si_gpiodump()
6671 bcm_bprintf(b, "gpioout 0x%x ", R_REG(sii->osh, &cc->gpioout)); in si_gpiodump()
6672 bcm_bprintf(b, "gpioouten 0x%x ", R_REG(sii->osh, &cc->gpioouten)); in si_gpiodump()
6673 bcm_bprintf(b, "gpiocontrol 0x%x ", R_REG(sii->osh, &cc->gpiocontrol)); in si_gpiodump()
6674 bcm_bprintf(b, "gpiointpolarity 0x%x ", R_REG(sii->osh, &cc->gpiointpolarity)); in si_gpiodump()
6675 bcm_bprintf(b, "gpiointmask 0x%x ", R_REG(sii->osh, &cc->gpiointmask)); in si_gpiodump()
7028 bankinfo = R_REG(sii->osh, &regs->bankinfo); in sysmem_banksize()
7059 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_sysmem_size()
7090 bankinfo = R_REG(sii->osh, &regs->bankinfo); in socram_banksize()
7156 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_socram_size()
7228 ret = R_REG(sii->osh, &cr4regs->corecapabilities) & CAP_MPU_MASK; in si_is_bus_mpu_present()
7231 ret = R_REG(sii->osh, &sysmemregs->mpucapabilities) & in si_is_bus_mpu_present()
7282 corecap = R_REG(sii->osh, arm_cap_reg); in si_tcm_size()
7293 bxinfo = R_REG(sii->osh, arm_binfo); in si_tcm_size()
7356 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_socram_srmem_size()
7364 if (R_REG(sii->osh, &regs->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK) in si_socram_srmem_size()
7440 SPINWAIT(!(R_REG(sii->osh, &cc->SECI_status) & SECI_STAT_BI), 1000); in BCMPOSTTRAPFN()
7505 if (((R_REG(sii->osh, &cc->clk_ctl_st) & CCS_SECICLKREQ) != CCS_SECICLKREQ)) { in BCMPOSTTRAPFN()
7662 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7679 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7739 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7745 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7994 regval = R_REG(sii->osh, &cc->chipcontrol); in si_seci_upd()
8007 regval = R_REG(sii->osh, &cc->SECI_config); in si_seci_upd()
8010 SPINWAIT((R_REG(sii->osh, &cc->SECI_config) & SECI_UPD_SECI), 1000); in si_seci_upd()
8086 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04); in si_btcgpiowar()
8121 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_read()
8139 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_srom4360()
8174 val = R_REG(sii->osh, &cc->clkdiv2); in si_srom_clk_set()
8210 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK); in si_btc_enable_chipcontrol()
8270 sromctrl = R_REG(sii->osh, &cc->sromcontrol); in si_is_sprom_available()
8464 sromctl = R_REG(osh, &cc->sromcontrol); in BCMATTACHFN()
8486 if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 && in BCMATTACHFN()
8487 (R_REG(osh, &cc->sromcontrol) & SRC_PRESENT)) { in BCMATTACHFN()
9323 return R_REG(sii->osh, r); in BCMPOSTTRAPFN()
9347 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9360 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9375 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9401 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9415 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9444 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9448 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & in BCMPOSTTRAPFN()
9477 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & mask) != val), in BCMPOSTTRAPFN()
9479 r = R_REG(sii->osh, fast_srpwr_addr) & mask; in BCMPOSTTRAPFN()
9639 val = R_REG(sii->osh, addr); in si_raw_reg()