Lines Matching +full:srom +full:- +full:page +full:- +full:mode
2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
162 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
230 * As si_kattach goes thru full srom initialisation same can be used
264 * devid - pci device id (used to determine chip#)
265 * osh - opaque OS handle
266 * regs - virtual address of initial core registers
267 * bustype - pci/sb/sdio/etc
268 * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
270 * varsz - pointer to int to return the size of the vars
296 sii->vars = vars ? *vars : NULL; in BCMATTACHFN()
297 sii->varsz = varsz ? *varsz : 0; in BCMATTACHFN()
321 * system has been initialized. Pass non-NULL vars & varsz only in BCMATTACHFN()
370 si_clkctl_xtal(&sii->pub, XTAL|PLL, ON); in BCMATTACHFN()
374 /* PR 39902, 43618, 44891, 41539 -- avoid backplane accesses that may in BCMATTACHFN()
414 /* Also, disable the extra SDIO pull-ups */ in BCMATTACHFN()
419 /* Avoid backplane accesses before wake-wlan (i.e. htavail) for spi. in BCMATTACHFN()
420 * F1 read accesses may return correct data but with data-not-available dstatus bit set. in BCMATTACHFN()
451 if (!(sii->pub.cccaps & CC_CAP_PMU)) { in si_get_pmu_reg_addr()
454 if (AOB_ENAB(&sii->pub)) { in si_get_pmu_reg_addr()
458 origidx = sii->curidx; in si_get_pmu_reg_addr()
459 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in si_get_pmu_reg_addr()
460 pmu = si_setcoreidx(&sii->pub, pmucoreidx); in si_get_pmu_reg_addr()
478 const si_cores_info_t *cores_info = sii->cores_info; in BCMATTACHFN()
485 si_slave_wrapper_add(&sii->pub); in BCMATTACHFN()
487 sii->curidx = 0; in BCMATTACHFN()
489 cc = si_setcoreidx(&sii->pub, SI_CC_IDX); in BCMATTACHFN()
493 sii->pub.ccrev = (int)si_corerev(&sii->pub); in BCMATTACHFN()
496 if (CCREV(sii->pub.ccrev) >= 11) in BCMATTACHFN()
497 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus); in BCMATTACHFN()
500 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); in BCMATTACHFN()
503 if (CCREV(sii->pub.ccrev) >= 35) /* PR77565 */ in BCMATTACHFN()
504 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); in BCMATTACHFN()
507 if (sii->pub.cccaps & CC_CAP_PMU) { in BCMATTACHFN()
508 if (AOB_ENAB(&sii->pub)) { in BCMATTACHFN()
512 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in BCMATTACHFN()
513 if (!GOODIDX(pmucoreidx, sii->numcores)) { in BCMATTACHFN()
518 pmu = si_setcoreidx(&sii->pub, pmucoreidx); in BCMATTACHFN()
519 sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities); in BCMATTACHFN()
520 si_setcoreidx(&sii->pub, SI_CC_IDX); in BCMATTACHFN()
522 sii->pub.gcirev = si_corereg(&sii->pub, GCI_CORE_IDX(&sii->pub), in BCMATTACHFN()
523 GCI_OFFSETOF(&sii->pub, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK; in BCMATTACHFN()
525 if (GCIREV(sii->pub.gcirev) >= 9) { in BCMATTACHFN()
526 sii->pub.lhlrev = si_corereg(&sii->pub, GCI_CORE_IDX(&sii->pub), in BCMATTACHFN()
530 sii->pub.lhlrev = NOREV; in BCMATTACHFN()
534 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); in BCMATTACHFN()
536 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; in BCMATTACHFN()
540 CCREV(sii->pub.ccrev), sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev, in BCMATTACHFN()
541 sii->pub.pmucaps)); in BCMATTACHFN()
545 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) { in BCMATTACHFN()
546 sii->pub.buscoretype = NODEV_CORE_ID; in BCMATTACHFN()
548 sii->pub.buscorerev = NOREV; in BCMATTACHFN()
549 sii->pub.buscoreidx = BADIDX; in BCMATTACHFN()
556 for (i = 0; i < sii->numcores; i++) { in BCMATTACHFN()
559 si_setcoreidx(&sii->pub, i); in BCMATTACHFN()
560 cid = si_coreid(&sii->pub); in BCMATTACHFN()
561 crev = si_corerev(&sii->pub); in BCMATTACHFN()
564 if (CHIPTYPE(sii->pub.socitype) != SOCI_NCI) { in BCMATTACHFN()
566 i, cid, crev, cores_info->coresba[i], cores_info->coresba_size[i], in BCMATTACHFN()
567 OSL_OBFUSCATE_BUF(cores_info->regs[i]))); in BCMATTACHFN()
602 sii->pub.buscorerev = (int16)crev; in BCMATTACHFN()
603 sii->pub.buscoretype = (uint16)cid; in BCMATTACHFN()
604 sii->pub.buscoreidx = (uint16)i; in BCMATTACHFN()
609 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
610 if (regs == sii->curmap) { in BCMATTACHFN()
615 if ((savewin && (savewin == cores_info->coresba[i])) || in BCMATTACHFN()
616 (regs == cores_info->regs[i])) { in BCMATTACHFN()
634 sii->pub.buscoretype = PCIE2_CORE_ID; in BCMATTACHFN()
636 sii->pub.buscoretype = PCIE_CORE_ID; in BCMATTACHFN()
637 sii->pub.buscorerev = (int16)pcierev; in BCMATTACHFN()
638 sii->pub.buscoreidx = (uint16)pcieidx; in BCMATTACHFN()
645 sii->pub.buscoretype = PCI_CORE_ID; in BCMATTACHFN()
646 sii->pub.buscorerev = (int16)pcirev; in BCMATTACHFN()
647 sii->pub.buscoreidx = (uint16)pciidx; in BCMATTACHFN()
650 sii->pub.buscoretype = PCIE2_CORE_ID; in BCMATTACHFN()
652 sii->pub.buscoretype = PCIE_CORE_ID; in BCMATTACHFN()
653 sii->pub.buscorerev = (int16)pcierev; in BCMATTACHFN()
654 sii->pub.buscoreidx = (uint16)pcieidx; in BCMATTACHFN()
658 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype, in BCMATTACHFN()
659 sii->pub.buscorerev)); in BCMATTACHFN()
663 if (!FWSIGN_ENAB() && BUSTYPE(sii->pub.bustype) == PCI_BUS) { in BCMATTACHFN()
665 if (!sii->pch && in BCMATTACHFN()
666 ((sii->pch = (void *)(uintptr)pcicore_init(&sii->pub, sii->osh, in BCMATTACHFN()
670 if (si_pci_fixcfg(&sii->pub)) { in BCMATTACHFN()
678 /* Make sure any on-chip ARM is off (in case strapping is wrong), or downloaded code was in BCMATTACHFN()
682 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || in BCMATTACHFN()
683 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) in BCMATTACHFN()
684 si_core_disable(&sii->pub, 0); in BCMATTACHFN()
689 si_setcoreidx(&sii->pub, *origidx); in BCMATTACHFN()
729 if ((sii->pub.boardvendor != VENDOR_APPLE)) { in BCMATTACHFN()
733 switch (sii->pub.boardtype) in BCMATTACHFN()
735 /* Check for the SROM value */ in BCMATTACHFN()
743 sii->pub.boardtype = (conf_vid >> 16) & 0xffff; in BCMATTACHFN()
764 switch (BUSTYPE(sii->pub.bustype)) { in BCMATTACHFN()
767 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); in BCMATTACHFN()
770 if ((sii->pub.boardvendor = (uint16)si_getdevpathintvar(&sii->pub, in BCMATTACHFN()
774 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
777 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
780 sii->pub.boardvendor, w & 0xffff)); in BCMATTACHFN()
783 if ((sii->pub.boardtype = (uint16)si_getdevpathintvar(&sii->pub, rstr_boardtype)) in BCMATTACHFN()
785 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
786 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
789 sii->pub.boardtype, (w >> 16) & 0xffff)); in BCMATTACHFN()
800 sii->pub.boardvendor = getintvar(pvars, rstr_manfid); in BCMATTACHFN()
801 sii->pub.boardtype = getintvar(pvars, rstr_prodid); in BCMATTACHFN()
805 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
806 sii->pub.boardtype = QT4710_BOARD; in BCMATTACHFN()
812 if (BCMPCIEDEV_ENAB() && si_is_sprom_available(&sii->pub) && pvars && in BCMATTACHFN()
814 sii->pub.boardvendor = getintvar(pvars, rstr_subvid); in BCMATTACHFN()
817 sii->pub.boardvendor = VENDOR_BROADCOM; in BCMATTACHFN()
818 if (pvars == NULL || ((sii->pub.boardtype = getintvar(pvars, rstr_prodid)) == 0)) in BCMATTACHFN()
819 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
820 sii->pub.boardtype = 0xffff; in BCMATTACHFN()
822 if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) { in BCMATTACHFN()
824 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); in BCMATTACHFN()
825 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
826 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
834 if (sii->pub.boardtype == 0) { in BCMATTACHFN()
836 ASSERT(sii->pub.boardtype); in BCMATTACHFN()
839 sii->pub.lpflags = getintvar(pvars, rstr_lpflags); in BCMATTACHFN()
840 sii->pub.boardrev = getintvar(pvars, rstr_boardrev); in BCMATTACHFN()
841 sii->pub.boardflags = getintvar(pvars, rstr_boardflags); in BCMATTACHFN()
844 sii->pub.boardflags2 |= ((!CHIP_HOSTIF_USB(&(sii->pub))) ? ((si_arm_sflags(&(sii->pub)) in BCMATTACHFN()
848 sii->pub.boardflags4 = getintvar(pvars, rstr_boardflags4); in BCMATTACHFN()
864 /* note: each index corr to MUXENAB43012_HOSTWAKE_MASK > shift - 1 */
875 /* note: each index corr to MUXENAB_DEF_HOSTWAKE mask >> shift - 1 */
895 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
934 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
956 sizeof(mux43012_hostwakeopt)/sizeof(mux43012_hostwakeopt[0]) - 1) { in BCMATTACHFN()
971 uint8 uartopt_idx = (w & MUXENAB_DEF_UART_MASK) - 1; in BCMATTACHFN()
981 if (CHIPREV(sih->chiprev) >= 3) { in BCMATTACHFN()
1001 sizeof(mux_hostwakeopt[0]) - 1)) { in BCMATTACHFN()
1189 * @param[in] gpio chip specific package pin number. See Toplevel Arch page, GCI chipcontrol reg
1223 int fnsel = -1; /* Valid fnsel is a small positive number */ in si_gpio_enable()
1235 switch (CHIPID(sih->chip)) in si_gpio_enable()
1247 if (fnsel != -1) { in si_gpio_enable()
1283 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
1297 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMPOSTTRAPFN()
1305 switch (CHIPID(sih->chip)) { in si_gci_time_sync_gpio_enable()
1316 SI_ERROR(("Time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_gci_time_sync_gpio_enable()
1336 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
1348 SI_ERROR(("time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1471 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
1473 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1488 sii->device_wake_opt = (uint8)getintvar(NULL, rstr_device_wake_opt); in BCMINITFN()
1489 return sii->device_wake_opt; in BCMINITFN()
1499 device_wake_opt = sii->device_wake_opt; in si_enable_device_wake()
1512 switch (CHIPID(sih->chip)) { in si_enable_device_wake()
1549 CHIPID(sih->chip), device_wake_opt)); in si_enable_device_wake()
1553 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_enable_device_wake()
1571 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_gci_gpioint_handler_unregister()
1575 ASSERT(sii->gci_gpio_head != NULL); in si_gci_gpioint_handler_unregister()
1577 if ((void*)sii->gci_gpio_head == gci_i) { in si_gci_gpioint_handler_unregister()
1578 sii->gci_gpio_head = sii->gci_gpio_head->next; in si_gci_gpioint_handler_unregister()
1579 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t)); in si_gci_gpioint_handler_unregister()
1582 p = sii->gci_gpio_head; in si_gci_gpioint_handler_unregister()
1583 n = p->next; in si_gci_gpioint_handler_unregister()
1586 p->next = n->next; in si_gci_gpioint_handler_unregister()
1587 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t)); in si_gci_gpioint_handler_unregister()
1591 n = n->next; in si_gci_gpioint_handler_unregister()
1609 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_gci_gpioint_handler_register()
1620 gci_i = MALLOC(sii->osh, (sizeof(gci_gpio_item_t))); in si_gci_gpioint_handler_register()
1628 if (sii->gci_gpio_head) in si_gci_gpioint_handler_register()
1629 gci_i->next = sii->gci_gpio_head; in si_gci_gpioint_handler_register()
1631 gci_i->next = NULL; in si_gci_gpioint_handler_register()
1633 sii->gci_gpio_head = gci_i; in si_gci_gpioint_handler_register()
1635 gci_i->handler = cb; in si_gci_gpioint_handler_register()
1636 gci_i->arg = arg; in si_gci_gpioint_handler_register()
1637 gci_i->gci_gpio = gci_gpio; in si_gci_gpioint_handler_register()
1638 gci_i->status = gpio_status; in si_gci_gpioint_handler_register()
1671 gci_i = sii->gci_gpio_head; in si_gci_gpioint_handler_process()
1677 if (gci_i->gci_gpio < 8) in si_gci_gpioint_handler_process()
1678 status = ((gpio_status[0] >> (gci_i->gci_gpio * 4)) & 0x0F); in si_gci_gpioint_handler_process()
1680 status = ((gpio_status[1] >> ((gci_i->gci_gpio - 8) * 4)) & 0x0F); in si_gci_gpioint_handler_process()
1683 ASSERT(gci_i->handler); in si_gci_gpioint_handler_process()
1684 if (gci_i->status & status) in si_gci_gpioint_handler_process()
1685 gci_i->handler(status, gci_i->arg); in si_gci_gpioint_handler_process()
1686 gci_i = gci_i->next; in si_gci_gpioint_handler_process()
1769 /* first 12 nibbles configured for format-0 */ in si_gci_seci_init()
1784 if (CHIPID(sih->chip) == BCM43602_CHIP_ID) { in si_gci_seci_init()
1810 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_wci2_rxfifo_handler_register()
1815 if ((wci2_info = (wci2_rxfifo_info_t *)MALLOCZ(sii->osh, in si_wci2_rxfifo_handler_register()
1821 if ((wci2_info->rx_buf = (char *)MALLOCZ(sii->osh, WCI2_UART_RX_BUF_SIZE)) == NULL) { in si_wci2_rxfifo_handler_register()
1822 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_register()
1828 if ((wci2_info->cbs = (wci2_cbs_t *)MALLOCZ(sii->osh, sizeof(wci2_cbs_t))) == NULL) { in si_wci2_rxfifo_handler_register()
1829 MFREE(sii->osh, wci2_info->rx_buf, WCI2_UART_RX_BUF_SIZE); in si_wci2_rxfifo_handler_register()
1830 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_register()
1836 sii->wci2_info = wci2_info; in si_wci2_rxfifo_handler_register()
1839 wci2_info->cbs->handler = rx_cb; in si_wci2_rxfifo_handler_register()
1840 wci2_info->cbs->context = ctx; in si_wci2_rxfifo_handler_register()
1855 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) { in si_wci2_rxfifo_handler_unregister()
1860 wci2_info = sii->wci2_info; in si_wci2_rxfifo_handler_unregister()
1866 if (wci2_info->rx_buf != NULL) { in si_wci2_rxfifo_handler_unregister()
1867 MFREE(sii->osh, wci2_info->rx_buf, WCI2_UART_RX_BUF_SIZE); in si_wci2_rxfifo_handler_unregister()
1870 if (wci2_info->cbs != NULL) { in si_wci2_rxfifo_handler_unregister()
1871 MFREE(sii->osh, wci2_info->cbs, sizeof(wci2_cbs_t)); in si_wci2_rxfifo_handler_unregister()
1874 MFREE(sii->osh, wci2_info, sizeof(wci2_rxfifo_info_t)); in si_wci2_rxfifo_handler_unregister()
1888 wci2_info = sii->wci2_info; in si_wci2_rxfifo_intr_handler_process()
1910 wci2_info->rx_buf[wci2_info->rx_idx] = ubyte; in si_wci2_rxfifo_intr_handler_process()
1911 wci2_info->rx_idx++; in si_wci2_rxfifo_intr_handler_process()
1916 if (wci2_info->rx_idx == WCI2_UART_RX_BUF_SIZE) { in si_wci2_rxfifo_intr_handler_process()
1925 if (call_cb && wci2_info && wci2_info->cbs) { in si_wci2_rxfifo_intr_handler_process()
1926 wci2_info->cbs->handler(wci2_info->cbs->context, wci2_info->rx_buf, in si_wci2_rxfifo_intr_handler_process()
1927 wci2_info->rx_idx); in si_wci2_rxfifo_intr_handler_process()
1928 bzero(wci2_info->rx_buf, WCI2_UART_RX_BUF_SIZE); in si_wci2_rxfifo_intr_handler_process()
1929 wci2_info->rx_idx = 0; in si_wci2_rxfifo_intr_handler_process()
1962 /* enable ERCX (pure gpio) mode, Keep SECI in Reset Mode Only */ in si_ercx_init()
1963 /* Hopefully, keeping SECI in Reset Mode will draw lesser current */ in si_ercx_init()
2002 /* NOTE: We are keeping Input PADs in Pull Down Mode to take care of the case in si_ercx_init()
2021 * NOTE: LTE chip has to enable its internal pull-down whenever WL goes down in si_ercx_init()
2054 /* Extract PAD GPIO number (1-byte) from "ltecx_padnum" for each LTECX pin */ in si_wci2_init()
2057 /* Extract FunctionSel (1-nibble) from "ltecx_fnsel" for each LTECX pin */ in si_wci2_init()
2060 /* Extract GCI-GPIO number (1-nibble) from "ltecx_gcigpio" for each LTECX pin */ in si_wci2_init()
2102 if (GCIREV(sih->gcirev) >= 1) { in si_wci2_init()
2109 if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2136 if (GCIREV(sih->gcirev) >= 16) { in si_wci2_init()
2154 if (GCIREV(sih->gcirev) >= 5) { in si_wci2_init()
2166 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2169 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2179 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2186 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2189 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2206 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2213 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2224 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2231 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2234 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2248 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2255 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2258 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2275 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2286 * bauddiv = 256-Integer Part of (GCI clk freq/baudrate) in si_wci2_init()
2288 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2296 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2304 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2307 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2325 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2333 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2341 if (GCIREV(sih->gcirev) >= 15) { in si_wci2_init()
2344 } else if (GCIREV(sih->gcirev) >= 4) { in si_wci2_init()
2356 if (GCIREV(sih->gcirev) >= 1) { in si_wci2_init()
2357 /* Route Rx-data through AUX register */ in si_wci2_init()
2370 /* GPIO 3-7 as BT_SIG complaint */ in si_wci2_init()
2371 /* config GPIO pins 3-7 as input */ in si_wci2_init()
2376 /* gpio mapping: frmsync-gpio7, mws_rx-gpio6, mws_tx-gpio5, in si_wci2_init()
2377 * pat[0]-gpio4, pat[1]-gpio3 in si_wci2_init()
2389 /* gpio mapping: wlan_rx_prio-gpio5, wlan_tx_on-gpio4 */ in si_wci2_init()
2401 /* This function is used in AIBSS mode by BTCX to enable strobing to BT */
2408 if (GCIREV(sih->gcirev) >= 1) { in si_btcx_wci2_init()
2437 hndgci_uart_config_rx_complete(-1, -1, 0, NULL, NULL); in si_gci_uart_init()
2448 * @param[in] input pin number, see respective chip Toplevel Arch page, GCI chipstatus regs
2521 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2536 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2553 return (sii->chipnew) ? sii->chipnew : sih->chip; in BCMINITFN()
2562 ASSERT(sii->chipnew == 0); in BCMATTACHFN()
2563 switch (sih->chip) { in BCMATTACHFN()
2565 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2566 sii->pub.chip = BCM4369_CHIP_ID; /* chip class */ in BCMATTACHFN()
2569 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2570 sii->pub.chip = BCM4375_CHIP_ID; /* chip class */ in BCMATTACHFN()
2573 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2574 sii->pub.chip = BCM4362_CHIP_ID; /* chip class */ in BCMATTACHFN()
2578 sii->chipnew = sih->chip; /* save it */ in BCMATTACHFN()
2579 sii->pub.chip = BCM4354_CHIP_ID; /* chip class */ in BCMATTACHFN()
2592 if (CHIPTYPE(_sih->socitype) == SOCI_AI) { in BCMPOSTTRAPFN()
2602 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_get_axi_errlog_info()
2603 return (const si_axi_error_info_t *)sih->err_info; in si_get_axi_errlog_info()
2612 if (sih->err_info) { in si_reset_axi_errlog_info()
2613 sih->err_info->count = 0; in si_reset_axi_errlog_info()
2622 if (sii->osh) { in BCMATTACHFN()
2623 sii->axi_wrapper = (axi_wrapper_t *)MALLOCZ(sii->osh, in BCMATTACHFN()
2626 if (sii->axi_wrapper == NULL) { in BCMATTACHFN()
2630 sii->axi_wrapper = NULL; in BCMATTACHFN()
2639 if (sii->axi_wrapper) { in BCMATTACHFN()
2641 MFREE(sii->osh, sii->axi_wrapper, (sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS)); in BCMATTACHFN()
2648 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2649 sii->nci_info = nci_init(&sii->pub, (void*)(uintptr)cc, sii->pub.bustype); in BCMATTACHFN()
2651 return sii->nci_info; in BCMATTACHFN()
2656 sii->cores_info = (si_cores_info_t *)&ksii_cores_info; in BCMATTACHFN()
2658 if (sii->cores_info == NULL) { in BCMATTACHFN()
2660 if ((sii->cores_info = (si_cores_info_t *)MALLOCZ(osh, in BCMATTACHFN()
2667 ASSERT(sii->cores_info == &ksii_cores_info); in BCMATTACHFN()
2671 return sii->cores_info; in BCMATTACHFN()
2680 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2681 if (sii->nci_info) { in BCMATTACHFN()
2682 nci_uninit(sii->nci_info); in BCMATTACHFN()
2683 sii->nci_info = NULL; in BCMATTACHFN()
2686 if (sii->cores_info && (sii->cores_info != &ksii_cores_info)) { in BCMATTACHFN()
2687 MFREE(osh, sii->cores_info, sizeof(si_cores_info_t)); in BCMATTACHFN()
2696 * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
2703 struct si_pub *sih = &sii->pub; in BCMATTACHFN()
2717 sih->buscoreidx = BADIDX; in BCMATTACHFN()
2718 sii->device_removed = FALSE; in BCMATTACHFN()
2720 sii->curmap = regs; in BCMATTACHFN()
2721 sii->sdh = sdh; in BCMATTACHFN()
2722 sii->osh = osh; in BCMATTACHFN()
2723 sii->second_bar0win = ~0x0; in BCMATTACHFN()
2724 sih->enum_base = si_enum_base(devid); in BCMATTACHFN()
2727 sih->err_info = MALLOCZ(osh, sizeof(si_axi_error_info_t)); in BCMATTACHFN()
2728 if (sih->err_info == NULL) { in BCMATTACHFN()
2740 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) { in BCMATTACHFN()
2748 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); in BCMATTACHFN()
2752 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih)); in BCMATTACHFN()
2760 cc = (chipcregs_t *)sii->curmap; in BCMATTACHFN()
2766 sih->bustype = (uint16)bustype; in BCMATTACHFN()
2792 w = R_REG(osh, &cc->chipid); in BCMATTACHFN()
2795 if ((w & 0xfffff) == 148277) w -= 65532; in BCMATTACHFN()
2797 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; in BCMATTACHFN()
2799 sih->chip = w & CID_ID_MASK; in BCMATTACHFN()
2800 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; in BCMATTACHFN()
2801 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; in BCMATTACHFN()
2809 sih->issim = IS_SIM(sih->chippkg); in BCMATTACHFN()
2812 sih->_multibp_enable = TRUE; in BCMATTACHFN()
2816 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
2822 ASSERT(sii->nci_info); in BCMATTACHFN()
2831 if ((sii->numcores = nci_scan(sih)) == 0u) { in BCMATTACHFN()
2836 nci_dump_erom(sii->nci_info); in BCMATTACHFN()
2846 if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) { in BCMATTACHFN()
2848 sb_scan(&sii->pub, regs, devid); in BCMATTACHFN()
2849 } else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) || in BCMATTACHFN()
2850 (CHIPTYPE(sii->pub.socitype) == SOCI_NAI) || in BCMATTACHFN()
2851 (CHIPTYPE(sii->pub.socitype) == SOCI_DVTBUS)) { in BCMATTACHFN()
2853 if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) in BCMATTACHFN()
2855 else if (CHIPTYPE(sii->pub.socitype) == SOCI_NAI) in BCMATTACHFN()
2864 ai_scan(&sii->pub, (void *)(uintptr)cc, devid); in BCMATTACHFN()
2866 if (sii->axi_num_wrappers == 0) { in BCMATTACHFN()
2872 else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) { in BCMATTACHFN()
2873 SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip)); in BCMATTACHFN()
2875 ub_scan(&sii->pub, (void *)(uintptr)cc, devid); in BCMATTACHFN()
2883 if (sii->numcores == 0) { in BCMATTACHFN()
2894 /* JIRA: SWWLAN-98321: SPROM read showing wrong values */ in BCMATTACHFN()
2895 /* Set the clkdiv2 divisor bits (2:0) to 0x4 if srom is present */ in BCMATTACHFN()
2898 capabilities = R_REG(osh, &cc->capabilities); in BCMATTACHFN()
2901 sromprsnt = R_REG(osh, &cc->sromcontrol); in BCMATTACHFN()
2904 /* SROM clock come from backplane clock/div2. Must <= 1Mhz */ in BCMATTACHFN()
2905 clkdiv2 = (R_REG(osh, &cc->clkdiv2) & ~CLKD2_SROM); in BCMATTACHFN()
2907 W_REG(osh, &cc->clkdiv2, clkdiv2); in BCMATTACHFN()
2914 /* JIRA:SWWLAN-18243: SPROM access taking too long */ in BCMATTACHFN()
2916 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
2917 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMATTACHFN()
2918 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2919 (CHIPREV(sih->chiprev) <= 2)) { in BCMATTACHFN()
2920 pcie_disable_TL_clk_gating(sii->pch); in BCMATTACHFN()
2921 pcie_set_L1_entry_time(sii->pch, 0x40); in BCMATTACHFN()
2932 if (CHIP_HOSTIF_PCIE(&(sii->pub))) { in BCMATTACHFN()
2933 uint32 sflags = si_arm_sflags(&(sii->pub)); in BCMATTACHFN()
2953 if (nvram_init(&(sii->pub)) != BCME_OK) { in BCMATTACHFN()
2976 if (srom_var_init(&sii->pub, BUSTYPE(bustype), (void *)regs, in BCMATTACHFN()
2977 sii->osh, &sromvars, varsz)) { in BCMATTACHFN()
2984 if (srom_var_init(&sii->pub, BUSTYPE(bustype), (void *)regs, in BCMATTACHFN()
2985 sii->osh, vars, varsz)) { in BCMATTACHFN()
2999 sii->xtalfreq = getintvar(NULL, rstr_xtalfreq); in BCMATTACHFN()
3013 sii->lhl_ps_mode = (uint8)getintvar(NULL, rstr_lhl_ps_mode); in BCMATTACHFN()
3016 sii->hib_ext_wakeup_enab = FALSE; in BCMATTACHFN()
3019 sii->hib_ext_wakeup_enab = TRUE; in BCMATTACHFN()
3021 sii->hib_ext_wakeup_enab = TRUE; in BCMATTACHFN()
3023 sii->hib_ext_wakeup_enab = FALSE; in BCMATTACHFN()
3027 sii->rfldo3p3_war = (bool)getintvar(NULL, rstr_rfldo3p3_cap_war); in BCMATTACHFN()
3039 sii->min_mask_valid = TRUE; in BCMATTACHFN()
3040 sii->nvram_min_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3042 sii->min_mask_valid = FALSE; in BCMATTACHFN()
3046 sii->max_mask_valid = TRUE; in BCMATTACHFN()
3047 sii->nvram_max_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3049 sii->max_mask_valid = FALSE; in BCMATTACHFN()
3054 if (BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip) || in BCMATTACHFN()
3055 BCM4389_CHIP(sih->chip) || in BCMATTACHFN()
3056 BCM4388_CHIP(sih->chip) || BCM4397_CHIP(sih->chip) || FALSE) { in BCMATTACHFN()
3058 sii->armpllclkfreq = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3059 ASSERT(sii->armpllclkfreq > 0); in BCMATTACHFN()
3061 sii->armpllclkfreq = 0; in BCMATTACHFN()
3085 if (CCREV(sii->pub.ccrev) >= 20) { in BCMATTACHFN()
3094 if (value != 0xFFFFFFFF) { /* non populated SROM fields are ffff */ in BCMATTACHFN()
3100 W_REG(osh, &cc->gpiopullup, gpiopullup); in BCMATTACHFN()
3101 W_REG(osh, &cc->gpiopulldown, gpiopulldown); in BCMATTACHFN()
3112 * 4389B0/C0 - WLAN and BT turn on WAR - synchronize WLAN and BT firmware using GCI in BCMATTACHFN()
3113 * semaphore - THREAD_0_GCI_SEM_3_ID to ensure that simultaneous register accesses in BCMATTACHFN()
3126 /* WLAN/BT turn On WAR - Remove wlsc_btsc_prisel override after semaphore acquire in BCMATTACHFN()
3127 * BT sets the override at power up when WL_REG_ON is low - wlsc_btsc_prisel is in in BCMATTACHFN()
3148 si_pmu_init(sih, sii->osh); in BCMATTACHFN()
3149 si_pmu_chip_init(sih, sii->osh); in BCMATTACHFN()
3161 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3175 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh); in BCMATTACHFN()
3177 sii->xtalfreq = xtalfreq; in BCMATTACHFN()
3178 si_pmu_pll_init(sih, sii->osh, xtalfreq); in BCMATTACHFN()
3182 sii->spurmode = getintvar(pvars, rstr_spurconfig) & 0xf; in BCMATTACHFN()
3213 si_pmu_res_init(sih, sii->osh); in BCMATTACHFN()
3214 si_pmu_swreg_init(sih, sii->osh); in BCMATTACHFN()
3231 ASSERT(sii->pch != NULL); in BCMATTACHFN()
3232 pcicore_attach(sii->pch, pvars, SI_DOATTACH); in BCMATTACHFN()
3236 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
3237 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
3238 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMATTACHFN()
3239 (CCREV(sih->ccrev) >= 62)) { in BCMATTACHFN()
3267 sii->device_wake_opt = CC_GCI_GPIO_INVALID; in BCMATTACHFN()
3269 /* clear any previous epidiag-induced target abort */ in BCMATTACHFN()
3281 if (((PCIECOREREV(sih->buscorerev) == 66) || (PCIECOREREV(sih->buscorerev) == 68)) && in BCMATTACHFN()
3282 CST4378_CHIPMODE_BTOP(sih->chipst)) { in BCMATTACHFN()
3284 * HW4378-413 : in BCMATTACHFN()
3294 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
3295 if (sii->pch) in BCMATTACHFN()
3296 pcicore_deinit(sii->pch); in BCMATTACHFN()
3297 sii->pch = NULL; in BCMATTACHFN()
3314 si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info; in BCMATTACHFN()
3324 sh_sflash_detach(sii->osh, sih); in BCMATTACHFN()
3327 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMATTACHFN()
3328 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMATTACHFN()
3329 if (sii->nci_info) { in BCMATTACHFN()
3330 nci_uninit(sii->nci_info); in BCMATTACHFN()
3331 sii->nci_info = NULL; in BCMATTACHFN()
3337 if (cores_info->regs[idx]) { in BCMATTACHFN()
3338 REG_UNMAP(cores_info->regs[idx]); in BCMATTACHFN()
3339 cores_info->regs[idx] = NULL; in BCMATTACHFN()
3351 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
3352 if (sii->pch) in BCMATTACHFN()
3353 pcicore_deinit(sii->pch); in BCMATTACHFN()
3354 sii->pch = NULL; in BCMATTACHFN()
3358 si_free_coresinfo(sii, sii->osh); in BCMATTACHFN()
3361 if (sih->err_info) { in BCMATTACHFN()
3362 MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t)); in BCMATTACHFN()
3363 sii->pub.err_info = NULL; in BCMATTACHFN()
3371 si_dvfs_info_deinit(sih, sii->osh); in BCMATTACHFN()
3376 MFREE(sii->osh, sii, sizeof(si_info_t)); in BCMATTACHFN()
3386 return sii->osh; in BCMPOSTTRAPFN()
3395 if (sii->osh != NULL) { in si_setosh()
3397 ASSERT(!sii->osh); in si_setosh()
3399 sii->osh = osh; in si_setosh()
3408 sii->intr_arg = intr_arg; in BCMATTACHFN()
3409 sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn; in BCMATTACHFN()
3410 sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn; in BCMATTACHFN()
3411 sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn; in BCMATTACHFN()
3415 sii->dev_coreid = si_coreid(sih); in BCMATTACHFN()
3424 sii->intrsoff_fn = NULL; in BCMPOSTTRAPFN()
3425 sii->intrsrestore_fn = NULL; in BCMPOSTTRAPFN()
3426 sii->intrsenabled_fn = NULL; in BCMPOSTTRAPFN()
3434 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3436 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3437 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3438 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3439 return R_REG(sii->osh, ((uint32 *)(uintptr) in BCMPOSTTRAPFN()
3440 (sii->oob_router + OOB_STATUSA))); in BCMPOSTTRAPFN()
3441 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3452 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_flag()
3454 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag()
3455 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag()
3456 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag()
3458 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_flag()
3460 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_flag()
3471 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag_alt()
3472 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag_alt()
3473 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag_alt()
3475 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_flag_alt()
3486 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3488 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3489 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3490 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3492 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3494 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3505 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_oobr_baseaddr()
3507 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_oobr_baseaddr()
3508 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_oobr_baseaddr()
3509 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_oobr_baseaddr()
3510 return (second ? sii->oob_router1 : sii->oob_router); in si_oobr_baseaddr()
3511 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_oobr_baseaddr()
3523 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3524 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3525 return nci_coreid(sih, sii->curidx); in BCMPOSTTRAPFN()
3528 return cores_info->coreid[sii->curidx]; in BCMPOSTTRAPFN()
3538 return sii->curidx; in BCMPOSTTRAPFN()
3545 return sii->numcores; in si_get_num_cores()
3554 /** return the core-type instantiation # of the current core */
3559 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_coreunit()
3565 if (CHIPTYPE(sii->pub.socitype) == SOCI_NCI) { in si_coreunit()
3571 idx = sii->curidx; in si_coreunit()
3573 ASSERT(GOODREGS(sii->curmap)); in si_coreunit()
3578 if (cores_info->coreid[i] == coreid) in si_coreunit()
3587 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3589 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3590 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3591 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3593 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3595 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3606 return ((sih->cccaps & CC_CAP_BKPLN64) != 0); in BCMINITFN()
3612 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3614 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3615 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3616 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3618 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3620 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3631 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_corerev_minor()
3634 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_corerev_minor()
3646 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3650 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3656 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3657 if (cores_info->coreid[i] == coreid) { in BCMPOSTTRAPFN()
3690 const si_cores_info_t *cores_info = sii->cores_info; in si_findcoreid()
3692 if (coreidx >= sii->numcores) { in si_findcoreid()
3695 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_findcoreid()
3698 return cores_info->coreid[coreidx]; in si_findcoreid()
3706 const si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info; in BCMPOSTTRAPFN()
3710 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
3713 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3714 if (cores_info->coreid[i] == coreid) { in BCMPOSTTRAPFN()
3726 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPRAMFN()
3737 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_corelist()
3739 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_corelist()
3742 (void)memcpy_s(coreid, (sii->numcores * sizeof(uint)), cores_info->coreid, in si_corelist()
3743 (sii->numcores * sizeof(uint))); in si_corelist()
3744 return (sii->numcores); in si_corelist()
3753 ASSERT(GOODREGS(sii->curwrap)); in BCMPOSTTRAPFN()
3755 return (sii->curwrap); in BCMPOSTTRAPFN()
3764 ASSERT(GOODREGS(sii->curmap)); in BCMPOSTTRAPFN()
3766 return (sii->curmap); in BCMPOSTTRAPFN()
3781 if (!GOODIDX(idx, sii->numcores)) { in BCMPOSTTRAPFN()
3785 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3787 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3788 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3789 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3791 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3793 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3804 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3806 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3807 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3808 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3810 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3812 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3835 else if (coreid == BUSCORETYPE(sih->buscoretype)) in BCMPOSTTRAPFN()
3839 *origidx = sii->curidx; in BCMPOSTTRAPFN()
3852 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype)))) in BCMPOSTTRAPFN()
3891 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3893 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3894 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3895 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3897 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3899 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3917 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_addrspace()
3919 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_addrspace()
3920 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_addrspace()
3921 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_addrspace()
3923 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_addrspace()
3925 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_addrspace()
3942 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMATTACHFN()
3944 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMATTACHFN()
3945 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMATTACHFN()
3946 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMATTACHFN()
3948 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMATTACHFN()
3950 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
3962 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_coreaddrspaceX()
3963 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_coreaddrspaceX()
3964 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_coreaddrspaceX()
3966 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_coreaddrspaceX()
3975 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
3977 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
3978 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
3979 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
3981 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
3983 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
3994 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_cflags_wo()
3996 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_cflags_wo()
3997 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_cflags_wo()
3998 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_cflags_wo()
4000 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_cflags_wo()
4002 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_cflags_wo()
4011 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_sflags()
4013 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_sflags()
4014 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_sflags()
4015 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_sflags()
4017 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_sflags()
4019 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_sflags()
4030 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_commit()
4032 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_commit()
4033 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_commit()
4034 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_commit()
4036 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_commit()
4038 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_commit()
4048 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4050 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4051 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4052 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4054 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4056 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4069 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4070 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4071 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4073 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4078 * it uses secondary bar-0 window which lies at an offset of 16K from primary bar-0
4114 sii->second_bar0win = ~0x0; in si_invalidate_second_bar0win()
4125 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_backplane_access()
4139 if (sii->second_bar0win != region) { in si_backplane_access()
4140 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region); in si_backplane_access()
4141 sii->second_bar0win = region; in si_backplane_access()
4145 * sii->curmap : bar-0 virtual address in si_backplane_access()
4146 * PCI_SECOND_BAR0_OFFSET : secondar bar-0 offset in si_backplane_access()
4149 r = (volatile uint32 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr); in si_backplane_access()
4152 (volatile char*)sii->curmap, region, addr, r, read)); in si_backplane_access()
4157 *val = R_REG(sii->osh, (volatile uint8*)r); in si_backplane_access()
4159 W_REG(sii->osh, (volatile uint8*)r, *val); in si_backplane_access()
4163 *val = R_REG(sii->osh, (volatile uint16*)r); in si_backplane_access()
4165 W_REG(sii->osh, (volatile uint16*)r, *val); in si_backplane_access()
4169 *val = R_REG(sii->osh, (volatile uint32*)r); in si_backplane_access()
4171 W_REG(sii->osh, (volatile uint32*)r, *val); in si_backplane_access()
4183 /* BLAZAR_BRANCH_101_10_DHD_002/build/dhd/linux-fc30/brix-brcm */
4198 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_backplane_access_64()
4214 if (sii->second_bar0win != region) { in si_backplane_access_64()
4215 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region); in si_backplane_access_64()
4216 sii->second_bar0win = region; in si_backplane_access_64()
4220 * sii->curmap : bar-0 virtual address in si_backplane_access_64()
4221 * PCI_SECOND_BAR0_OFFSET : secondar bar-0 offset in si_backplane_access_64()
4224 r = (volatile uint64 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr); in si_backplane_access_64()
4229 *val = R_REG(sii->osh, (volatile uint64*)r); in si_backplane_access_64()
4231 W_REG(sii->osh, (volatile uint64*)r, *val); in si_backplane_access_64()
4248 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4250 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4251 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4252 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4254 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4256 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4267 if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in BCMPOSTTRAPFN()
4296 if (mask != 0 && PMUREV(sih->pmurev) >= 22 && in BCMPOSTTRAPFN()
4320 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4322 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4323 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4324 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4326 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4336 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_disable()
4338 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_disable()
4339 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_disable()
4340 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_disable()
4342 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_core_disable()
4344 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_disable()
4351 if (CHIPTYPE(sih->socitype) == SOCI_SB) in BCMPOSTTRAPFN()
4353 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
4354 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in BCMPOSTTRAPFN()
4355 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in BCMPOSTTRAPFN()
4357 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMPOSTTRAPFN()
4359 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in BCMPOSTTRAPFN()
4363 /** Run bist on current core. Caller needs to take care of core-specific bist hazards */
4395 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_num_slaveports()
4398 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) { in si_num_slaveports()
4410 uint origidx = sii->curidx; in si_get_slaveport_addr()
4413 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_slaveport_addr()
4414 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_slaveport_addr()
4415 (CHIPTYPE(sih->socitype) == SOCI_NAI) || in si_get_slaveport_addr()
4416 (CHIPTYPE(sih->socitype) == SOCI_NCI))) in si_get_slaveport_addr()
4434 uint origidx = sii->curidx; in si_get_d11_slaveport_addr()
4437 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_d11_slaveport_addr()
4438 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_d11_slaveport_addr()
4439 (CHIPTYPE(sih->socitype) == SOCI_NAI) || in si_get_d11_slaveport_addr()
4440 (CHIPTYPE(sih->socitype) == SOCI_NCI))) in si_get_d11_slaveport_addr()
4571 switch (CHIPID(sih->chip)) { in si_chip_hostif()
4582 /* chippkg bit-0 == 0 is PCIE only pkgs in si_chip_hostif()
4583 * chippkg bit-0 == 1 has both PCIE and USB cores enabled in si_chip_hostif()
4585 if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB)) in si_chip_hostif()
4593 if (CST4369_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
4595 else if (CST4369_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
4607 if (CST4362_CHIPMODE_SDIOD(sih->chipst)) { in si_chip_hostif()
4609 } else if (CST4362_CHIPMODE_PCIE(sih->chipst)) { in si_chip_hostif()
4634 rate = si_pmu_si_clock(sih, sii->osh); in BCMINITFN()
4638 idx = sii->curidx; in BCMINITFN()
4642 n = R_REG(sii->osh, &cc->clockcontrol_n); in BCMINITFN()
4643 pll_type = sih->cccaps & CC_CAP_PLL_MASK; in BCMINITFN()
4645 m = R_REG(sii->osh, &cc->clockcontrol_m3); in BCMINITFN()
4647 m = R_REG(sii->osh, &cc->clockcontrol_m2); in BCMINITFN()
4649 m = R_REG(sii->osh, &cc->clockcontrol_sb); in BCMINITFN()
4695 nb = (CCREV(sih->ccrev) < 26) ? 16 : ((CCREV(sih->ccrev) >= 37) ? 32 : 24); in si_watchdog()
4697 * so we specially handle the 32-bit case. in si_watchdog()
4702 maxt = ((1 << nb) - 1); in si_watchdog()
4710 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_watchdog()
4711 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_watchdog()
4712 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_watchdog()
4724 /* make sure we come up in fast clock mode; or if clearing, clear clock */ in si_watchdog()
4727 maxt = (1 << 28) - 1; in si_watchdog()
4731 if (CCREV(sih->ccrev) >= 65) { in si_watchdog()
4758 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_taclear()
4760 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_taclear()
4761 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_taclear()
4762 (CHIPTYPE(sih->socitype) == SOCI_NCI) || in si_taclear()
4763 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_taclear()
4765 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_taclear()
4791 /* normal case: nvram variable with devpath->devid->wl0id */ in BCMATTACHFN()
4794 /* Get devid from OTP/SPROM depending on where the SROM is read */ in BCMATTACHFN()
4795 else if ((device = (uint16)getintvar(sii->vars, rstr_devid)) != 0) in BCMATTACHFN()
4798 else if ((device = (uint16)getintvar(sii->vars, rstr_wl0id)) != 0) in BCMATTACHFN()
4800 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in BCMATTACHFN()
4964 origidx = sii->curidx; in si_dumpregs()
4967 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_dumpregs()
4969 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_dumpregs()
4970 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_dumpregs()
4971 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_dumpregs()
4973 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_dumpregs()
4975 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_dumpregs()
4990 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_view()
4992 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_view()
4993 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_view()
4994 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_view()
4996 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_view()
4998 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_view()
5011 curidx = sii->curidx; in si_viewall()
5014 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_viewall()
5015 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_viewall()
5016 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_viewall()
5018 else if (CHIPTYPE(sih->socitype) == SOCI_NCI) in si_viewall()
5021 SI_ERROR(("si_viewall: num_cores %d\n", sii->numcores)); in si_viewall()
5022 for (i = 0; i < sii->numcores; i++) { in si_viewall()
5032 /** return the slow clock source - LPO, XTAL, or PCI */
5038 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); in si_slowclk_src()
5040 if (CCREV(sii->pub.ccrev) < 6) { in si_slowclk_src()
5041 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) && in si_slowclk_src()
5042 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) & in si_slowclk_src()
5047 } else if (CCREV(sii->pub.ccrev) < 10) { in si_slowclk_src()
5048 cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx); in si_slowclk_src()
5050 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK); in si_slowclk_src()
5051 } else /* Insta-clock */ in si_slowclk_src()
5062 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); in si_slowclk_freq()
5065 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); in si_slowclk_freq()
5068 if (CCREV(sii->pub.ccrev) < 6) { in si_slowclk_freq()
5073 } else if (CCREV(sii->pub.ccrev) < 10) { in si_slowclk_freq()
5075 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1); in si_slowclk_freq()
5086 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; in si_slowclk_freq()
5111 slowmaxfreq = si_slowclk_freq(sii, (CCREV(sii->pub.ccrev) >= 10) ? FALSE : TRUE, cc); in BCMINITFN()
5116 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay); in BCMINITFN()
5117 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay); in BCMINITFN()
5135 origidx = sii->curidx; in BCMINITFN()
5143 if (CCREV(sih->ccrev) >= 10) in BCMINITFN()
5144 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK, in BCMINITFN()
5171 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh); in BCMINITFN()
5182 origidx = sii->curidx; in BCMINITFN()
5194 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) + in BCMINITFN()
5195 (slowminfreq - 1)) / slowminfreq; in BCMINITFN()
5214 switch (BUSTYPE(sih->bustype)) { in si_clkctl_xtal()
5218 return (-1); in si_clkctl_xtal()
5224 return -1; in si_clkctl_xtal()
5226 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32)); in si_clkctl_xtal()
5227 out = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)); in si_clkctl_xtal()
5228 outen = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32)); in si_clkctl_xtal()
5249 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, in si_clkctl_xtal()
5251 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, in si_clkctl_xtal()
5259 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, in si_clkctl_xtal()
5268 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32), out); in si_clkctl_xtal()
5269 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32), in si_clkctl_xtal()
5275 return (-1); in si_clkctl_xtal()
5284 * set dynamic clk control mode (forceslow, forcefast, dynamic)
5290 si_clkctl_cc(si_t *sih, uint mode) in si_clkctl_cc() argument
5297 if (CCREV(sih->ccrev) < 6) in si_clkctl_cc()
5300 return _si_clkctl_cc(sii, mode); in si_clkctl_cc()
5305 _si_clkctl_cc(si_info_t *sii, uint mode) in _si_clkctl_cc() argument
5314 if (CCREV(sii->pub.ccrev) < 6) in _si_clkctl_cc()
5318 ASSERT(CCREV(sii->pub.ccrev) != 10); in _si_clkctl_cc()
5322 origidx = sii->curidx; in _si_clkctl_cc()
5323 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); in _si_clkctl_cc()
5328 if (!CCCTL_ENAB(&sii->pub) && (CCREV(sii->pub.ccrev) < 20)) in _si_clkctl_cc()
5331 switch (mode) { in _si_clkctl_cc()
5333 if (CCREV(sii->pub.ccrev) < 10) { in _si_clkctl_cc()
5335 si_clkctl_xtal(&sii->pub, XTAL, ON); in _si_clkctl_cc()
5336 SET_REG(sii->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP); in _si_clkctl_cc()
5337 } else if (CCREV(sii->pub.ccrev) < 20) { in _si_clkctl_cc()
5338 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR); in _si_clkctl_cc()
5340 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT); in _si_clkctl_cc()
5344 if (PMUCTL_ENAB(&sii->pub)) { in _si_clkctl_cc()
5346 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0), in _si_clkctl_cc()
5348 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); in _si_clkctl_cc()
5355 if (CCREV(sii->pub.ccrev) < 10) { in _si_clkctl_cc()
5356 scc = R_REG(sii->osh, &cc->slow_clk_ctl); in _si_clkctl_cc()
5360 W_REG(sii->osh, &cc->slow_clk_ctl, scc); in _si_clkctl_cc()
5364 si_clkctl_xtal(&sii->pub, XTAL, OFF); in _si_clkctl_cc()
5365 } else if (CCREV(sii->pub.ccrev) < 20) { in _si_clkctl_cc()
5367 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR); in _si_clkctl_cc()
5369 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); in _si_clkctl_cc()
5373 if (PMUCTL_ENAB(&sii->pub)) { in _si_clkctl_cc()
5375 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0), in _si_clkctl_cc()
5377 ASSERT(!(R_REG(sii->osh, &cc->clk_ctl_st) & htavail)); in _si_clkctl_cc()
5390 si_setcoreidx(&sii->pub, origidx); in _si_clkctl_cc()
5393 return (mode == CLK_FAST); in _si_clkctl_cc()
5406 return -1; in BCMNMIATTACHFN()
5408 switch (BUSTYPE(sih->bustype)) { in BCMNMIATTACHFN()
5413 ASSERT((SI_INFO(sih))->osh != NULL); in BCMNMIATTACHFN()
5415 OSL_PCI_BUS((SI_INFO(sih))->osh), in BCMNMIATTACHFN()
5416 OSL_PCI_SLOT((SI_INFO(sih))->osh)); in BCMNMIATTACHFN()
5425 slen = -1; in BCMNMIATTACHFN()
5432 return -1; in BCMNMIATTACHFN()
5445 return -1; in BCMNMIATTACHFN()
5447 ASSERT((SI_INFO(sih))->osh != NULL); in BCMNMIATTACHFN()
5449 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh), in BCMNMIATTACHFN()
5450 OSL_PCIE_BUS((SI_INFO(sih))->osh)); in BCMNMIATTACHFN()
5470 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5472 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh), in BCMATTACHFN()
5473 OSL_PCIE_BUS((SI_INFO(sih))->osh)); in BCMATTACHFN()
5482 if (devpath[len1 - 1] == '/') in BCMATTACHFN()
5483 len1--; in BCMATTACHFN()
5492 if (p[len2 - 1] == '/') in BCMATTACHFN()
5493 len2--; in BCMATTACHFN()
5525 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5554 if (BUSTYPE(sih->bustype) == PCI_BUS) { in BCMATTACHFN()
5585 if (strlen(name) + 1 > (uint)(len - path_len)) in BCMATTACHFN()
5588 strlcpy(var + path_len, name, len - path_len); in BCMATTACHFN()
5605 if (strlen(name) + 1 > (uint)(len - path_len)) in BCMATTACHFN()
5608 strlcpy(var + path_len, name, len - path_len); in BCMATTACHFN()
5626 reg_val = si_corereg(&sii->pub, SI_CC_IDX, offset, mask, val); in BCMPOSTTRAPFN()
5636 W_REG(si_osh(sih), &cc->sr_memrw_addr, offset); in sih_write_sraon()
5638 W_REG(si_osh(sih), &cc->sr_memrw_data, *data); in sih_write_sraon()
5640 len -= sizeof(uint32); in sih_write_sraon()
5654 pmu_var->pmu_control = si_ccreg(sih, PMU_CTL, 0, 0); in si_dump_pmu()
5655 pmu_var->pmu_capabilities = si_ccreg(sih, PMU_CAP, 0, 0); in si_dump_pmu()
5656 pmu_var->pmu_status = si_ccreg(sih, PMU_ST, 0, 0); in si_dump_pmu()
5657 pmu_var->res_state = si_ccreg(sih, PMU_RES_STATE, 0, 0); in si_dump_pmu()
5658 pmu_var->res_pending = si_ccreg(sih, PMU_RES_PENDING, 0, 0); in si_dump_pmu()
5659 pmu_var->pmu_timer1 = si_ccreg(sih, PMU_TIMER, 0, 0); in si_dump_pmu()
5660 pmu_var->min_res_mask = si_ccreg(sih, MINRESMASKREG, 0, 0); in si_dump_pmu()
5661 pmu_var->max_res_mask = si_ccreg(sih, MAXRESMASKREG, 0, 0); in si_dump_pmu()
5662 pmu_chip_ctl_reg = (pmu_var->pmu_capabilities & 0xf8000000); in si_dump_pmu()
5665 pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0); in si_dump_pmu()
5667 pmu_chip_reg_reg = (pmu_var->pmu_capabilities & 0x07c00000); in si_dump_pmu()
5670 pmu_var->pmu_regcontrol[i] = si_pmu_vreg_control(sih, i, 0, 0); in si_dump_pmu()
5672 pmu_chip_pll_reg = (pmu_var->pmu_capabilities & 0x003e0000); in si_dump_pmu()
5675 pmu_var->pmu_pllcontrol[i] = si_pmu_pllcontrol(sih, i, 0, 0); in si_dump_pmu()
5677 pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00); in si_dump_pmu()
5681 pmu_var->pmu_rsrc_up_down_timer[i] = si_corereg(sih, SI_CC_IDX, in si_dump_pmu()
5684 pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00); in si_dump_pmu()
5688 pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0); in si_dump_pmu()
5702 W_REG(sii->osh, &cc->res_table_sel, int_val); in si_pmu_keep_on()
5703 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on()
5707 max_res_mask = R_REG(sii->osh, &cc->max_res_mask); in si_pmu_keep_on()
5709 W_REG(sii->osh, &cc->max_res_mask, max_res_mask); in si_pmu_keep_on()
5711 W_REG(sii->osh, &cc->min_res_mask, min_res_mask); in si_pmu_keep_on()
5724 min_res_mask = R_REG(sii->osh, &cc->min_res_mask); in si_pmu_keep_on_get()
5727 W_REG(sii->osh, &cc->res_table_sel, i); in si_pmu_keep_on_get()
5728 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask); in si_pmu_keep_on_get()
5809 return pcicore_pciereg(sii->pch, offset, mask, val, type); in si_pciereg()
5822 return pcicore_pcieserdesreg(sii->pch, mdioslave, offset, mask, val); in si_pcieserdesreg()
5832 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) in BCMATTACHFN()
5835 cap_ptr = pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, NULL); in BCMATTACHFN()
5842 /* Wake-on-wireless-LAN (WOWL) support functions */
5847 pcicore_pmeen(SI_INFO(sih)->pch); in si_pci_pmeen()
5854 return pcicore_pmestat(SI_INFO(sih)->pch); in si_pci_pmestat()
5861 pcicore_pmeclr(SI_INFO(sih)->pch); in si_pci_pmeclr()
5867 pcicore_pmestatclr(SI_INFO(sih)->pch); in si_pci_pmestatclr()
5877 if (BUSCORETYPE(sih->buscoretype) == SDIOD_CORE_ID) { in si_sdio_init()
5883 idx = sii->curidx; in si_sdio_init()
5893 sih->buscorerev, idx, sii->curidx, OSL_OBFUSCATE_BUF(sdpregs))); in si_sdio_init()
5896 W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT); in si_sdio_init()
5897 W_REG(sii->osh, &sdpregs->sbintmask, (I_SB_SERR | I_SB_RESPERR | (1 << idx))); in si_sdio_init()
5904 bcmsdh_intr_enable(sii->sdh); in si_sdio_init()
5924 pcie_war_ovr_aspm_update(sii->pch, aspm); in si_pcie_war_ovr_update()
5935 pcie_power_save_enable(sii->pch, enable); in si_pcie_power_save_enable()
5946 pcie_set_maxpayload_size(sii->pch, size); in si_pcie_set_maxpayload_size()
5957 return pcie_get_maxpayload_size(sii->pch); in si_pcie_get_maxpayload_size()
5968 pcie_set_request_size(sii->pch, size); in si_pcie_set_request_size()
5979 return pcie_get_request_size(sii->pch); in BCMATTACHFN()
5990 return pcie_get_ssid(sii->pch); in si_pcie_get_ssid()
6001 return pcie_get_bar0(sii->pch); in si_pcie_get_bar0()
6012 return pcie_configspace_cache(sii->pch); in si_pcie_configspace_cache()
6023 return pcie_configspace_restore(sii->pch); in si_pcie_configspace_restore()
6032 return -1; in si_pcie_configspace_get()
6034 return pcie_configspace_get(sii->pch, buf, size); in si_pcie_configspace_get()
6042 /* SWWLAN-41753: WAR intermittent issue with D3Cold and L1.2 exit, in si_pcie_hw_L1SS_war()
6046 pcie_hw_L1SS_war(sii->pch); in si_pcie_hw_L1SS_war()
6055 if (BUSTYPE(sih->bustype) != PCI_BUS) in BCMINITFN()
6061 pcicore_up(sii->pch, SI_PCIUP); in BCMINITFN()
6065 /** Unconfigure and/or apply various WARs when system is going to sleep mode */
6072 pcicore_sleep(SI_INFO(sih)->pch); in BCMUNINITFN()
6083 if (BUSTYPE(sih->bustype) != PCI_BUS) in BCMINITFN()
6086 pcicore_down(sii->pch, SI_PCIDOWN); in BCMINITFN()
6101 if (BUSTYPE(sii->pub.bustype) != PCI_BUS) in BCMATTACHFN()
6105 ASSERT(sii->pub.buscoreidx != BADIDX); in BCMATTACHFN()
6109 idx = sii->curidx; in BCMATTACHFN()
6115 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx); in BCMATTACHFN()
6119 * Enable sb->pci interrupts. Assume in BCMATTACHFN()
6122 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { in BCMATTACHFN()
6124 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32)); in BCMATTACHFN()
6127 /* User mode operate with interrupt disabled */ in BCMATTACHFN()
6130 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w); in BCMATTACHFN()
6142 OR_REG(sii->osh, &pciregs->sbtopci2, (SBTOPCI_PREF | SBTOPCI_BURST)); in BCMATTACHFN()
6143 if (sii->pub.buscorerev >= 11) { in BCMATTACHFN()
6144 OR_REG(sii->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI); in BCMATTACHFN()
6148 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6149 W_REG(sii->osh, &pciregs->clkrun, (w | PCI_CLKRUN_DSBL)); in BCMATTACHFN()
6150 w = R_REG(sii->osh, &pciregs->clkrun); in BCMATTACHFN()
6158 /* In NIC mode is there any better way to find out what ARM core is there? */
6197 ASSERT(BUSTYPE(sih->bustype) == PCI_BUS); in BCMATTACHFN()
6198 ASSERT(BUSTYPE(sih->buscoretype) == PCIE2_CORE_ID); in BCMATTACHFN()
6200 /* ==== Enable sb->pci interrupts ==== */ in BCMATTACHFN()
6203 * re-route the main interrupt to pcie (from ARM) if necessary in BCMATTACHFN()
6206 HND_CORE_MAIN_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6209 * to the pcie core... re-route! in BCMATTACHFN()
6212 if (!GOODIDX(armcidx, sii->numcores)) { in BCMATTACHFN()
6222 HND_CORE_ALT_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6231 hnd_oobr_set_intr_src(sih, sih->buscoreidx, pciepidx, main_intr); in BCMATTACHFN()
6241 HND_CORE_MAIN_INTR, sih->buscoreidx, &pciepidx); in BCMATTACHFN()
6279 return pcie_clkreq(sii->pch, mask, val); in si_pcieclkreq()
6290 return pcie_lcreg(sii->pch, mask, val); in si_pcielcreg()
6301 return pcie_ltrenable(sii->pch, mask, val); in si_pcieltrenable()
6312 return pcie_obffenable(sii->pch, mask, val); in BCMATTACHFN()
6323 return pcie_ltr_reg(sii->pch, reg, mask, val); in si_pcieltr_reg()
6334 return pcieltrspacing_reg(sii->pch, mask, val); in si_pcieltrspacing_reg()
6345 return pcieltrhysteresiscnt_reg(sii->pch, mask, val); in si_pcieltrhysteresiscnt_reg()
6349 si_pcie_set_error_injection(const si_t *sih, uint32 mode) in si_pcie_set_error_injection() argument
6356 pcie_set_error_injection(sii->pch, mode); in si_pcie_set_error_injection()
6365 pcie_set_L1substate(sii->pch, substate); in si_pcie_set_L1substate()
6374 return pcie_get_L1substate(sii->pch); in si_pcie_get_L1substate()
6414 ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS); in si_pci_fixcfg()
6416 /* Fixup PI in SROM shadow area to enable the correct PCI core access */ in si_pci_fixcfg()
6417 origidx = si_coreidx(&sii->pub); in si_pci_fixcfg()
6420 if (BUSCORETYPE(sii->pub.buscoretype) == PCIE2_CORE_ID) { in si_pci_fixcfg()
6421 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE2_CORE_ID, 0); in si_pci_fixcfg()
6423 reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; in si_pci_fixcfg()
6424 } else if (BUSCORETYPE(sii->pub.buscoretype) == PCIE_CORE_ID) { in si_pci_fixcfg()
6425 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE_CORE_ID, 0); in si_pci_fixcfg()
6427 reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; in si_pci_fixcfg()
6428 } else if (BUSCORETYPE(sii->pub.buscoretype) == PCI_CORE_ID) { in si_pci_fixcfg()
6429 pciregs = (sbpciregs_t *)si_setcore(&sii->pub, PCI_CORE_ID, 0); in si_pci_fixcfg()
6431 reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; in si_pci_fixcfg()
6433 pciidx = si_coreidx(&sii->pub); in si_pci_fixcfg()
6435 if (!reg16) return -1; in si_pci_fixcfg()
6437 val16 = R_REG(sii->osh, reg16); in si_pci_fixcfg()
6441 W_REG(sii->osh, reg16, val16); in si_pci_fixcfg()
6445 si_setcoreidx(&sii->pub, origidx); in si_pci_fixcfg()
6447 pcicore_hwup(sii->pch); in si_pci_fixcfg()
6461 return pcicore_dump_pcieinfo(sii->pch, b); in si_dump_pcieinfo()
6471 bcm_bprintf(b, "===pmu(rev %d)===\n", sih->pmurev); in si_dump_pmuregs()
6472 if (!(sih->pmurev == 0x11 || (sih->pmurev >= 0x15 && sih->pmurev <= 0x19))) { in si_dump_pmuregs()
6530 return pcicore_dump_pcieregs(sii->pch, b); in si_dump_pcieregs()
6540 const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info; in si_dump()
6544 OSL_OBFUSCATE_BUF(sii), sih->chip, sih->chiprev, in si_dump()
6545 sih->boardtype, sih->boardvendor, sih->bustype); in si_dump()
6547 OSL_OBFUSCATE_BUF(sii->osh), OSL_OBFUSCATE_BUF(sii->curmap)); in si_dump()
6549 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_dump()
6550 bcm_bprintf(b, "sonicsrev %d ", sih->socirev); in si_dump()
6552 CCREV(sih->ccrev), sih->buscoretype, sih->buscorerev, sii->curidx); in si_dump()
6555 if ((BUSTYPE(sih->bustype) == PCI_BUS) && (sii->pch)) in si_dump()
6556 pcicore_dump(sii->pch, b); in si_dump()
6560 for (i = 0; i < sii->numcores; i++) in si_dump()
6561 bcm_bprintf(b, "0x%x ", cores_info->coreid[i]); in si_dump()
6575 if (CCREV(sih->ccrev) != 23) in si_ccreg_dump()
6578 origidx = sii->curidx; in si_ccreg_dump()
6585 bcm_bprintf(b, "\n===cc(rev %d) registers(offset val)===\n", CCREV(sih->ccrev)); in si_ccreg_dump()
6601 if (sih->cccaps & CC_CAP_PMU) { in si_ccreg_dump()
6621 if (!(sih->cccaps & CC_CAP_PWR_CTL)) in si_clkctl_dump()
6625 origidx = sii->curidx; in si_clkctl_dump()
6630 cc->pll_on_delay, cc->fref_sel_delay); in si_clkctl_dump()
6631 if ((CCREV(sih->ccrev) >= 6) && (CCREV(sih->ccrev) < 10)) in si_clkctl_dump()
6632 bcm_bprintf(b, "slow_clk_ctl 0x%x ", cc->slow_clk_ctl); in si_clkctl_dump()
6633 if (CCREV(sih->ccrev) >= 10) { in si_clkctl_dump()
6634 bcm_bprintf(b, "system_clk_ctl 0x%x ", cc->system_clk_ctl); in si_clkctl_dump()
6635 bcm_bprintf(b, "clkstatestretch 0x%x ", cc->clkstatestretch); in si_clkctl_dump()
6638 if (BUSTYPE(sih->bustype) == PCI_BUS) in si_clkctl_dump()
6640 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)), in si_clkctl_dump()
6641 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32))); in si_clkctl_dump()
6643 if (sih->cccaps & CC_CAP_PMU) { in si_clkctl_dump()
6670 bcm_bprintf(b, "gpioin 0x%x ", R_REG(sii->osh, &cc->gpioin)); in si_gpiodump()
6671 bcm_bprintf(b, "gpioout 0x%x ", R_REG(sii->osh, &cc->gpioout)); in si_gpiodump()
6672 bcm_bprintf(b, "gpioouten 0x%x ", R_REG(sii->osh, &cc->gpioouten)); in si_gpiodump()
6673 bcm_bprintf(b, "gpiocontrol 0x%x ", R_REG(sii->osh, &cc->gpiocontrol)); in si_gpiodump()
6674 bcm_bprintf(b, "gpiointpolarity 0x%x ", R_REG(sii->osh, &cc->gpiointpolarity)); in si_gpiodump()
6675 bcm_bprintf(b, "gpiointmask 0x%x ", R_REG(sii->osh, &cc->gpiointmask)); in si_gpiodump()
6701 * to some chip-specific purpose.
6714 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6736 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6758 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in BCMPOSTTRAPFN()
6775 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpioreserve()
6776 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpioreserve()
6780 if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) { in si_gpioreserve()
6781 ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1))); in si_gpioreserve()
6806 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpiorelease()
6807 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpiorelease()
6811 if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) { in si_gpiorelease()
6812 ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1))); in si_gpiorelease()
6843 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointpolarity()
6860 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointmask()
6875 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpioeventintmask()
6889 if (CCREV(sih->ccrev) < 20) in si_gpiopull()
6901 if (CCREV(sih->ccrev) < 11) in si_gpioevent()
6921 if (CCREV(sih->ccrev) < 11) in BCMATTACHFN()
6936 switch (CHIPID(sih->chip)) { in si_gci_shif_config_wake_pin()
7027 W_REG(sii->osh, ®s->bankidx, bankidx); in sysmem_banksize()
7028 bankinfo = R_REG(sii->osh, ®s->bankinfo); in sysmem_banksize()
7059 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_sysmem_size()
7089 W_REG(sii->osh, ®s->bankidx, bankidx); in socram_banksize()
7090 bankinfo = R_REG(sii->osh, ®s->bankinfo); in socram_banksize()
7117 W_REG(sii->osh, ®s->bankidx, bankidx); in si_socram_set_bankpda()
7118 W_REG(sii->osh, ®s->bankpda, bankpda); in si_socram_set_bankpda()
7156 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_socram_size()
7169 nb --; in si_socram_size()
7172 memsize += (1 << ((lss - 1) + SR_BSZ_BASE)); in si_socram_size()
7228 ret = R_REG(sii->osh, &cr4regs->corecapabilities) & CAP_MPU_MASK; in si_is_bus_mpu_present()
7231 ret = R_REG(sii->osh, &sysmemregs->mpucapabilities) & in si_is_bus_mpu_present()
7246 /** Return the TCM-RAM size of the ARMCR4 core. */
7282 corecap = R_REG(sii->osh, arm_cap_reg); in si_tcm_size()
7291 W_REG(sii->osh, arm_bidx, idx); in si_tcm_size()
7293 bxinfo = R_REG(sii->osh, arm_binfo); in si_tcm_size()
7356 coreinfo = R_REG(sii->osh, ®s->coreinfo); in si_socram_srmem_size()
7363 W_REG(sii->osh, ®s->bankidx, i); in si_socram_srmem_size()
7364 if (R_REG(sii->osh, ®s->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK) in si_socram_srmem_size()
7384 return (sih->cccaps_ext & CC_CAP_EXT_SECI_PUART_PRESENT); in BCMPOSTTRAPFN()
7437 W_REG(sii->osh, &cc->SECI_status, SECI_STAT_BI); in BCMPOSTTRAPFN()
7440 SPINWAIT(!(R_REG(sii->osh, &cc->SECI_status) & SECI_STAT_BI), 1000); in BCMPOSTTRAPFN()
7464 (void)si_pmu_wait_for_steady_state(sih, sii->osh, pmu); in BCMPOSTTRAPFN()
7490 *origidx = sii->curidx; in BCMPOSTTRAPFN()
7505 if (((R_REG(sii->osh, &cc->clk_ctl_st) & CCS_SECICLKREQ) != CCS_SECICLKREQ)) { in BCMPOSTTRAPFN()
7582 W_REG(sii->osh, &cc->seci_uart_data, (uint32)(val & 0xff)); in BCMPOSTTRAPFN()
7627 if (sih->ccrev < 35) in BCMINITFN()
7649 origidx = sii->curidx; in BCMINITFN()
7662 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7664 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7666 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7668 /* set force-low, and set EN_SECI for all non-legacy modes */ in BCMINITFN()
7675 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7679 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7681 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7684 /* hard-coded at 4MBaud for now */ in BCMINITFN()
7689 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMINITFN()
7690 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMINITFN()
7691 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMINITFN()
7692 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) { in BCMINITFN()
7703 else if (CCREV(sih->ccrev) >= 62) { in BCMINITFN()
7738 /* set the seci mode in seci conf register */ in BCMINITFN()
7739 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7742 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7744 /* Clear force-low bit */ in BCMINITFN()
7745 seci_conf = R_REG(sii->osh, &cc->SECI_config); in BCMINITFN()
7747 W_REG(sii->osh, &cc->SECI_config, seci_conf); in BCMINITFN()
7758 si_eci_notify_bt((sih), ECI_OUT_FM_DISABLE_MASK(CCREV(sih->ccrev)), \
7759 ((val) << ECI_OUT_FM_DISABLE_SHIFT(CCREV(sih->ccrev))), FALSE)
7793 return (!!(sih->cccaps & CC_CAP_ECI)); in si_eci()
7799 return (sih->cccaps_ext & CC_CAP_EXT_SECI_PRESENT); in BCMPOSTTRAPFN()
7805 return (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT); in si_gci()
7811 return (sih->cccaps_ext & CC_CAP_SR_AON_PRESENT); in si_sraon()
7825 if (!(sih->cccaps & CC_CAP_ECI)) in BCMINITFN()
7831 origidx = sii->curidx; in BCMINITFN()
7839 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7840 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskhi, 0x0); in BCMINITFN()
7841 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskmi, 0x0); in BCMINITFN()
7842 W_REG(sii->osh, &cc->eci.lt35.eci_intmasklo, 0x0); in BCMINITFN()
7844 W_REG(sii->osh, &cc->eci.ge35.eci_intmaskhi, 0x0); in BCMINITFN()
7845 W_REG(sii->osh, &cc->eci.ge35.eci_intmasklo, 0x0); in BCMINITFN()
7849 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7850 W_REG(sii->osh, &cc->eci.lt35.eci_control, ECI_MACCTRL_BITS); in BCMINITFN()
7852 W_REG(sii->osh, &cc->eci.ge35.eci_controllo, ECI_MACCTRLLO_BITS); in BCMINITFN()
7853 W_REG(sii->osh, &cc->eci.ge35.eci_controlhi, ECI_MACCTRLHI_BITS); in BCMINITFN()
7859 if (CCREV(sih->ccrev) < 35) { in BCMINITFN()
7860 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskhi, 0x0); in BCMINITFN()
7861 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskmi, 0x0); in BCMINITFN()
7862 W_REG(sii->osh, &cc->eci.lt35.eci_eventmasklo, 0x0); in BCMINITFN()
7864 W_REG(sii->osh, &cc->eci.ge35.eci_eventmaskhi, 0x0); in BCMINITFN()
7865 W_REG(sii->osh, &cc->eci.ge35.eci_eventmasklo, 0x0); in BCMINITFN()
7888 if ((sih->cccaps & CC_CAP_ECI) || in si_eci_notify_bt()
7891 /* ECI or SECI mode */ in si_eci_notify_bt()
7895 (CCREV(sih->ccrev) < 35 ? in si_eci_notify_bt()
7901 if (CCREV(sih->ccrev) >= 35) { in si_eci_notify_bt()
7920 (CCREV(sih->ccrev) < 35 ? in si_eci_notify_bt()
7925 } else if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT) { in si_eci_notify_bt()
7926 /* GCI Mode */ in si_eci_notify_bt()
7984 origidx = sii->curidx; in si_seci_upd()
7993 if ((CHIPID(sih->chip) == BCM4352_CHIP_ID) || (CHIPID(sih->chip) == BCM4360_CHIP_ID)) { in si_seci_upd()
7994 regval = R_REG(sii->osh, &cc->chipcontrol); in si_seci_upd()
8003 W_REG(sii->osh, &cc->chipcontrol, regval); in si_seci_upd()
8007 regval = R_REG(sii->osh, &cc->SECI_config); in si_seci_upd()
8009 W_REG(sii->osh, &cc->SECI_config, regval); in si_seci_upd()
8010 SPINWAIT((R_REG(sii->osh, &cc->SECI_config) & SECI_UPD_SECI), 1000); in si_seci_upd()
8012 W_REG(sii->osh, &cc->seci_uart_data, SECI_SLIP_ESC_CHAR); in si_seci_upd()
8013 W_REG(sii->osh, &cc->seci_uart_data, SECI_REFRESH_REQ); in si_seci_upd()
8032 if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT) in BCMINITFN()
8036 if (sih->boardflags4 & BFL4_BTCOEX_OVER_SECI) { in BCMINITFN()
8040 /* Set GCI Control bits 40 - 47 to be SW Controlled. These bits in BCMINITFN()
8047 hndgci_init(sih, sii->osh, HND_GCI_PLAIN_UART_MODE, in BCMINITFN()
8075 if (!(sih->cccaps & CC_CAP_UARTGPIO)) in si_btcgpiowar()
8078 /* si_corereg cannot be used as we have to guarantee 8-bit read/writes */ in si_btcgpiowar()
8086 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04); in si_btcgpiowar()
8105 W_REG(sii->osh, &cc->chipcontrol, val); in si_chipcontrl_restore()
8119 return -1; in si_chipcontrl_read()
8121 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_read()
8126 /** switch muxed pins, on: SROM, off: FEMCTRL. Called for a family of ac chips, not just 4360. */
8139 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_srom4360()
8148 W_REG(sii->osh, &cc->chipcontrol, val); in si_chipcontrl_srom4360()
8157 * The SROM clock is derived from the backplane clock. For chips having a fast
8158 * backplane clock that requires a higher-than-POR-default clock divisor ratio for the SROM clock.
8174 val = R_REG(sii->osh, &cc->clkdiv2); in si_srom_clk_set()
8177 W_REG(sii->osh, &cc->clkdiv2, ((val & ~CLKD2_SROM) | divisor)); in si_srom_clk_set()
8185 switch (CHIPID(sih->chip)) { in si_pmu_avb_clk_set()
8209 W_REG(sii->osh, &cc->chipcontrol, in si_btc_enable_chipcontrol()
8210 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK); in si_btc_enable_chipcontrol()
8220 sii->device_removed = status; in si_set_device_removed()
8230 if (sii->device_removed) { in si_deviceremoved()
8234 switch (BUSTYPE(sih->bustype)) { in si_deviceremoved()
8236 ASSERT(SI_INFO(sih)->osh != NULL); in si_deviceremoved()
8237 w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32)); in si_deviceremoved()
8257 if (CCREV(sih->ccrev) >= 31) { in si_is_sprom_available()
8263 if ((sih->cccaps & CC_CAP_SROM) == 0) in si_is_sprom_available()
8267 origidx = sii->curidx; in si_is_sprom_available()
8270 sromctrl = R_REG(sii->osh, &cc->sromcontrol); in si_is_sprom_available()
8275 switch (CHIPID(sih->chip)) { in si_is_sprom_available()
8277 if (CHIPREV(sih->chiprev) == 0) { in si_is_sprom_available()
8278 /* WAR for 4369a0: HW4369-1729. no sprom, default to otp always. */ in si_is_sprom_available()
8281 return (sih->chipst & CST4369_SPROM_PRESENT) != 0; in si_is_sprom_available()
8285 return (sih->chipst & CST43602_SPROM_PRESENT) != 0; in si_is_sprom_available()
8291 return (sih->chipst & CST4362_SPROM_PRESENT) != 0; in si_is_sprom_available()
8294 return (sih->chipst & CST4378_SPROM_PRESENT) != 0; in si_is_sprom_available()
8297 return (sih->chipst & CST4387_SPROM_PRESENT) != 0; in si_is_sprom_available()
8311 switch (CHIPID(sih->chip)) { in si_is_sflash_available()
8313 return (sih->chipst & CST4387_SFLASH_PRESENT) != 0; in si_is_sflash_available()
8323 switch (CHIPID(sih->chip)) { in si_is_otp_disabled()
8369 /* Most PCI chips use SROM format instead of CIS */ in si_cis_source()
8370 if (BUSTYPE(sih->bustype) == PCI_BUS) { in si_cis_source()
8374 switch (CHIPID(sih->chip)) { in si_cis_source()
8379 if ((sih->chipst & CST4360_OTP_ENABLED)) in si_cis_source()
8384 if (sih->chipst & CST43602_SPROM_PRESENT) { in si_cis_source()
8385 /* Don't support CIS formatted SROM, use 'real' SROM format instead */ in si_cis_source()
8394 if (CHIPREV(sih->chiprev) == 0) { in si_cis_source()
8395 /* WAR for 4369a0: HW4369-1729 */ in si_cis_source()
8397 } else if (sih->chipst & CST4369_SPROM_PRESENT) { in si_cis_source()
8402 return ((sih->chipst & CST4362_SPROM_PRESENT)? CIS_SROM : CIS_OTP); in si_cis_source()
8405 if (sih->chipst & CST4378_SPROM_PRESENT) in si_cis_source()
8410 if (sih->chipst & CST4387_SPROM_PRESENT) in si_cis_source()
8428 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
8464 sromctl = R_REG(osh, &cc->sromcontrol); in BCMATTACHFN()
8486 if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 && in BCMATTACHFN()
8487 (R_REG(osh, &cc->sromcontrol) & SRC_PRESENT)) { in BCMATTACHFN()
8488 W_REG(osh, &cc->sromcontrol, value); in BCMATTACHFN()
8534 si_pmu_res_minmax_update(sih, sii->osh); in si_pmu_sr_upd()
8548 switch (CHIPID(sih->chip)) { in si_update_masks()
8561 si_pmu_res_minmax_update(sih, sii->osh); in si_update_masks()
8581 switch (CHIPID(sih->chip)) { in si_force_islanding()
8634 switch (CHIPID(sih->chip)) { in si_pmu_rfldo()
8657 if (PCIECOREREV(sih->buscorerev) >= 23) in si_pcie_disable_oobselltr()
8670 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0)); in si_pcie_ltr_war()
8681 pcie_hw_LTR_war(sii->pch); in si_pcie_hw_LTR_war()
8692 pciedev_reg_pm_clk_period(sii->pch); in si_pciedev_reg_pm_clk_period()
8703 pciedev_crwlpciegen2(sii->pch); in si_pciedev_crwlpciegen2()
8714 pciedev_prep_D3(sii->pch, enter_D3); in si_pcie_prep_D3()
8774 /* Remove SFLASH clock request (which is default on for boot-from-flash support) */ in si_43012_lp_enable()
8783 if (!(sih->lpflags & LPFLAGS_SI_GCI_FORCE_REGCLK_DISABLE)) { in si_43012_lp_enable()
8789 if (!(sih->lpflags & LPFLAGS_SI_SFLASH_DISABLE)) { in si_43012_lp_enable()
8796 OR_REG(sii->osh, &gciregs->gpio_ctrl_iocfg_p_adr[count], in si_43012_lp_enable()
8801 if (!(sih->lpflags & LPFLAGS_SI_BTLDO3P3_DISABLE)) { in si_43012_lp_enable()
8818 if (BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8830 if (hosti != CHIP_HOSTIF_USBMODE && !BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8841 switch (CHIPID(sih->chip)) { in si_lowpwr_opt()
8865 /* Power down unused BBPLL ch-6(pcie_tl_clk) and ch-5(sample-sync-clk), */ in si_lowpwr_opt()
8866 /* valid in all modes, ch-5 needs to be reenabled for sample-capture */ in si_lowpwr_opt()
8868 /* a pcie driver. Enable the sample-sync-clk in the sample capture function */ in si_lowpwr_opt()
8869 if (BCM43602_CHIP(sih->chip)) { in si_lowpwr_opt()
8883 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_lowpwr_opt()
8884 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_lowpwr_opt()
8885 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_lowpwr_opt()
8887 if (sih->lpflags & LPFLAGS_SI_GLOBAL_DISABLE) { in si_lowpwr_opt()
8912 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
8913 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in BCMPOSTTRAPFN()
8923 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in BCMPOSTTRAPFN()
8924 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in BCMPOSTTRAPFN()
8937 if (CHIPTYPE(sih->socitype) != SOCI_AI) { in BCMATTACHFN()
8956 if ((CHIPTYPE(sih->socitype) != SOCI_AI) && in si_slave_wrapper_add()
8957 (CHIPTYPE(sih->socitype) != SOCI_DVTBUS)) { in si_slave_wrapper_add()
9038 switch (CHIPID(sih->chip)) { in si_pll_sr_reinit()
9042 /* check current pll mode */ in si_pll_sr_reinit()
9047 si_pmu_pll_init(sih, osh, sii->xtalfreq); in si_pll_sr_reinit()
9073 si_pmu_res_init(sih, sii->osh); in si_pll_sr_reinit()
9088 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9090 /* Don't apply those changes to FULL DONGLE mode since the in BCMATTACHFN()
9096 /* current mode is openloop (possible POR) */ in BCMATTACHFN()
9144 return sii->rfldo3p3_war; in si_get_nvram_rfldo3p3_war()
9152 if (sii->min_mask_valid == TRUE) { in si_nvram_res_masks()
9153 SI_MSG(("Applying rmin=%d to min_mask\n", sii->nvram_min_mask)); in si_nvram_res_masks()
9154 *min_mask = sii->nvram_min_mask; in si_nvram_res_masks()
9157 if (sii->max_mask_valid == TRUE) { in si_nvram_res_masks()
9158 SI_MSG(("Applying rmax=%d to max_mask\n", sii->nvram_max_mask)); in si_nvram_res_masks()
9159 *max_mask = sii->nvram_max_mask; in si_nvram_res_masks()
9167 return sii->spurmode; in si_getspurmode()
9174 return sii->xtalfreq; in si_xtalfreq()
9181 return sii->openloop_dco_code; in si_get_openloop_dco_code()
9188 sii->openloop_dco_code = _openloop_dco_code; in si_set_openloop_dco_code()
9209 armpllclkfreq = (sii->armpllclkfreq) ? sii->armpllclkfreq : armpllclk_max; in BCMPOSTTRAPFN()
9225 ccidiv = (sii->ccidiv) ? sii->ccidiv : CCIDIV_3_TO_1; in BCMPOSTTRAPFN()
9234 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMATTACHFN()
9242 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9252 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9263 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9273 if (CHIPTYPE(sih->socitype) == SOCI_AI) in BCMPOSTTRAPFN()
9283 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_get_axi_timeout_reg()
9304 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in BCMPOSTTRAPFN()
9306 r = (volatile uint32 *)((volatile char *)sii->curmap + in BCMPOSTTRAPFN()
9309 W_REG(sii->osh, r, val); in BCMPOSTTRAPFN()
9318 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in BCMPOSTTRAPFN()
9320 r = (volatile uint32 *)((volatile char *)sii->curmap + in BCMPOSTTRAPFN()
9323 return R_REG(sii->osh, r); in BCMPOSTTRAPFN()
9330 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in BCMPOSTTRAPFN()
9346 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9347 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9358 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9359 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9360 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9374 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9375 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9390 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in BCMPOSTTRAPFN()
9400 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9401 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9407 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9413 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9414 W_REG(sii->osh, fast_srpwr_addr, r); in BCMPOSTTRAPFN()
9415 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9443 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9444 r = R_REG(sii->osh, fast_srpwr_addr); in BCMPOSTTRAPFN()
9448 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & in BCMPOSTTRAPFN()
9461 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in BCMPOSTTRAPFN()
9476 if (BUSTYPE(sih->bustype) == SI_BUS) { in BCMPOSTTRAPFN()
9477 SPINWAIT(((R_REG(sii->osh, fast_srpwr_addr) & mask) != val), in BCMPOSTTRAPFN()
9479 r = R_REG(sii->osh, fast_srpwr_addr) & mask; in BCMPOSTTRAPFN()
9496 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_stat()
9498 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_stat()
9500 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_stat()
9514 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_domain()
9516 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_domain()
9522 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_domain()
9546 /* If domain ID is non-zero, chip supports power domain control */ in si_srpwr_cap()
9569 uint32 offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_bt_status()
9571 uint32 cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_bt_status()
9573 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_bt_status()
9600 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_raw_reg()
9605 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_raw_reg()
9613 addr = (volatile uint32*)(((volatile uint8*)sii->curmap) + in si_raw_reg()
9621 addr = (volatile uint32*)(((volatile uint8*)sii->curmap) + in si_raw_reg()
9626 prev_value = OSL_PCI_READ_CONFIG(sii->osh, cfg_reg, 4); in si_raw_reg()
9629 OSL_PCI_WRITE_CONFIG(sii->osh, cfg_reg, in si_raw_reg()
9637 W_REG(sii->osh, addr, val); in si_raw_reg()
9639 val = R_REG(sii->osh, addr); in si_raw_reg()
9644 OSL_PCI_WRITE_CONFIG(sii->osh, in si_raw_reg()
9656 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in BCMPOSTTRAPFN()
9667 return sii->lhl_ps_mode; in si_lhl_ps_mode()
9674 return sii->hib_ext_wakeup_enab; in si_hib_ext_wakeup_isenab()
9739 * GCI Chip Control reg 15 - Bits 29 & 30 (Global 509 & 510) in si_rffe_rfem_init()
9743 * GCI chip control reg 23 - Bits 29 & 30 (Global 765 & 766) in si_rffe_rfem_init()
9761 if (sih->ccrev == 68) { in si_rffe_rfem_init()
9770 if (sih->ccrev >= 71) { in si_rffe_rfem_init()
9791 sih->rffe_debug_mode = enable; in si_rffe_set_debug_mode()
9797 return sih->rffe_debug_mode; in si_rffe_get_debug_mode()
9803 return sih->rffe_elnabyp_mode; in si_rffe_get_elnabyp_mode()
9807 si_rffe_set_elnabyp_mode(si_t *sih, uint8 mode) in si_rffe_set_elnabyp_mode() argument
9813 if ((mode & ELNABYP_IOVAR_2G0_VALUE_MASK) && (mode & ELNABYP_IOVAR_2G0_ENABLE_MASK)) { in si_rffe_set_elnabyp_mode()
9815 } else if (mode & ELNABYP_IOVAR_2G0_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9818 if ((mode & ELNABYP_IOVAR_5G0_VALUE_MASK) && (mode & ELNABYP_IOVAR_5G0_ENABLE_MASK)) { in si_rffe_set_elnabyp_mode()
9820 } else if (mode & ELNABYP_IOVAR_5G0_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9823 if ((mode & ELNABYP_IOVAR_2G1_VALUE_MASK) && (mode & ELNABYP_IOVAR_2G1_ENABLE_MASK)) { in si_rffe_set_elnabyp_mode()
9825 } else if (mode & ELNABYP_IOVAR_2G1_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9828 if ((mode & ELNABYP_IOVAR_5G1_VALUE_MASK) && (mode & ELNABYP_IOVAR_5G1_ENABLE_MASK)) { in si_rffe_set_elnabyp_mode()
9830 } else if (mode & ELNABYP_IOVAR_5G1_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9834 if (mode & ELNABYP_IOVAR_2G0_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9837 if (mode & ELNABYP_IOVAR_5G0_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9840 if (mode & ELNABYP_IOVAR_2G1_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9843 if (mode & ELNABYP_IOVAR_5G1_ENABLE_MASK) { in si_rffe_set_elnabyp_mode()
9852 sih->rffe_elnabyp_mode = mode; in si_rffe_set_elnabyp_mode()
9924 uint8 repeat = (sih->ccrev == 69) ? 2 : 1; /* WAR for 4387c0 */ in BCMPOSTTRAPFN()
9952 while (repeat--) { in BCMPOSTTRAPFN()
9980 switch (CHIPID(sih->chip)) { in si_chipcap_sdio_ate_only()
9982 if (CST4369_CHIPMODE_SDIOD(sih->chipst) && in si_chipcap_sdio_ate_only()
9983 CST4369_CHIPMODE_PCIE(sih->chipst)) { in si_chipcap_sdio_ate_only()
9997 if (CST4362_CHIPMODE_SDIOD(sih->chipst) && in si_chipcap_sdio_ate_only()
9998 CST4362_CHIPMODE_PCIE(sih->chipst)) { in si_chipcap_sdio_ate_only()
10013 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_dump_APB_Bridge_registers()
10022 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_force_clocks()
10035 * 0 0000-0FFF 1000-1FFF
10036 * 1 4000-4FFF 5000-5FFF
10037 * 2 9000-9FFF A000-AFFF
10045 sii->slice = slice; in si_set_slice_id()
10053 return sii->slice; in si_get_slice_id()
10067 switch (CHIPID(sih->chip)) { in si_btc_bt_status_in_reset()
10161 if (CHIPID(sih->chip) == BCM4369_CHIP_ID || CHIPID(sih->chip) == BCM4377_CHIP_ID) { in si_configure_pwrthrottle_gpio()
10173 if (CHIPID(sih->chip) == BCM4369_CHIP_ID || CHIPID(sih->chip) == BCM4377_CHIP_ID) { in si_configure_onbody_gpio()
10189 switch (CHIPID(sih->chip)) { in si_jtag_udr_pwrsw_main_toggle()
10210 switch (CHIPID(sih->chip)) { in BCMATTACHFN()