Lines Matching +full:0 +full:x0080000
105 #define DEFAULT_SECI_UART_PINMUX 0x08090a0b
106 static bool force_seci_clk = 0;
128 #define GCI_FEM_CTRL_WAR 0x11111111
191 static uint32 si_gpioreservation = 0;
201 0x0000, 0x0001, 0x0010, 0x0011,
202 0x0100, 0x0101, 0x0110, 0x0111,
203 0x1000, 0x1001, 0x1010, 0x1011,
204 0x1100, 0x1101, 0x1110, 0x1111
209 int do_4360_pcie2_war = 0;
297 sii->varsz = varsz ? *varsz : 0; in BCMATTACHFN()
402 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", in BCMATTACHFN()
415 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); in BCMATTACHFN()
428 SI_MSG(("F0 REG0 rd = 0x%x\n", regdata)); in BCMATTACHFN()
448 uint origidx = 0; in si_get_pmu_reg_addr()
459 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in si_get_pmu_reg_addr()
487 sii->curidx = 0; in BCMATTACHFN()
512 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0); in BCMATTACHFN()
523 GCI_OFFSETOF(&sii->pub, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK; in BCMATTACHFN()
527 OFFSETOF(gciregs_t, lhl_core_capab_adr), 0, 0) & in BCMATTACHFN()
539 SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n", in BCMATTACHFN()
556 for (i = 0; i < sii->numcores; i++) { in BCMATTACHFN()
565 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x size:%x regs 0x%p\n", in BCMATTACHFN()
658 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype, in BCMATTACHFN()
682 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || in BCMATTACHFN()
683 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) in BCMATTACHFN()
684 si_core_disable(&sii->pub, 0); in BCMATTACHFN()
743 sii->pub.boardtype = (conf_vid >> 16) & 0xffff; in BCMATTACHFN()
757 uint w = 0; in BCMATTACHFN()
771 rstr_boardvendor)) == 0) { in BCMATTACHFN()
773 if ((w & 0xffff) == 0) in BCMATTACHFN()
777 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
779 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", in BCMATTACHFN()
780 sii->pub.boardvendor, w & 0xffff)); in BCMATTACHFN()
784 == 0) { in BCMATTACHFN()
785 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
786 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
788 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", in BCMATTACHFN()
789 sii->pub.boardtype, (w >> 16) & 0xffff)); in BCMATTACHFN()
818 if (pvars == NULL || ((sii->pub.boardtype = getintvar(pvars, rstr_prodid)) == 0)) in BCMATTACHFN()
819 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0) in BCMATTACHFN()
820 sii->pub.boardtype = 0xffff; in BCMATTACHFN()
825 sii->pub.boardvendor = w & 0xffff; in BCMATTACHFN()
826 sii->pub.boardtype = (w >> 16) & 0xffff; in BCMATTACHFN()
834 if (sii->pub.boardtype == 0) { in BCMATTACHFN()
845 & SISF_SDRENABLE) ? BFL2_SDR_EN:0): in BCMATTACHFN()
919 ASSERT(0); in BCMATTACHFN()
930 pmu_chipcontrol = si_pmu_chipcontrol(sih, 1, 0, 0); in BCMATTACHFN()
932 0, 0); in BCMATTACHFN()
948 * 0x10 : use GPIO0 as host wake up pin in BCMATTACHFN()
949 * 0x20 ~ 0xf0: Reserved in BCMATTACHFN()
952 uint8 hostwake = 0; in BCMATTACHFN()
956 sizeof(mux43012_hostwakeopt)/sizeof(mux43012_hostwakeopt[0]) - 1) { in BCMATTACHFN()
970 uint32 uart_rx = 0, uart_tx = 0; in BCMATTACHFN()
972 uint8 uartopt_size = sizeof(mux_uartopt)/sizeof(mux_uartopt[0]); in BCMATTACHFN()
978 uart_rx = 0; in BCMATTACHFN()
993 uint8 hostwake = 0; in BCMATTACHFN()
996 * 0x10 : use GPIO0 as host wake up pin in BCMATTACHFN()
1001 sizeof(mux_hostwakeopt[0]) - 1)) { in BCMATTACHFN()
1031 ASSERT(0); in BCMATTACHFN()
1036 si_pmu_chipcontrol(sih, 1, ~0, pmu_chipcontrol); in BCMATTACHFN()
1038 ~0, chipcontrol); in BCMATTACHFN()
1053 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, regidx); in si_gci_indirect()
1061 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_input[reg]), 0, 0); in si_gci_input()
1078 return (si_corereg(sih, SI_CC_IDX, offs, CI_ECI, (enable ? CI_ECI : 0))); in si_gci_int_enable()
1097 for (i = 0; i < 2; i++) { in si_gci_reset()
1098 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1109 for (i = 0; i < 10; i++) { in si_gci_reset()
1110 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1117 ((0 << GCI_CCTL_SECIRST_OFFSET) in si_gci_reset()
1118 |(0 << GCI_CCTL_RSTSL_OFFSET) in si_gci_reset()
1119 |(0 << GCI_CCTL_RSTOCC_OFFSET))); in si_gci_reset()
1122 for (i = 0; i < 2; i++) { in si_gci_reset()
1123 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_corectrl), 0, 0); in si_gci_reset()
1130 ((0 << GCI_CCTL_FREGCLK_OFFSET) in si_gci_reset()
1131 |(0 << GCI_CCTL_FSECICLK_OFFSET))); in si_gci_reset()
1134 for (i = 0; i < 32; i++) { in si_gci_reset()
1135 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_event[i]), ALLONES_32, 0x00); in si_gci_reset()
1148 uint32 ring_idx = 0, pos = 0; in BCMPOSTTRAPFN()
1151 SI_MSG(("si_gci_gpio_chipcontrol:rngidx is %d, pos is %d, opt is %d, mask is 0x%04x," in BCMPOSTTRAPFN()
1152 " value is 0x%04x\n", in BCMPOSTTRAPFN()
1155 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1164 uint32 ring_idx = 0, pos = 0; /**< FunctionSel register idx and bits to use */ in BCMPOSTTRAPFN()
1168 SI_MSG(("si_gci_gpio_reg:rngidx is %d, pos is %d, val is %d, mask is 0x%04x," in BCMPOSTTRAPFN()
1169 " value is 0x%04x\n", in BCMPOSTTRAPFN()
1171 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1178 val_32 = si_corereg(sih, GCI_CORE_IDX(sih), reg_offset, 0, 0); in BCMPOSTTRAPFN()
1180 value = (uint8)((val_32 >> pos) & 0xFF); in BCMPOSTTRAPFN()
1197 uint32 ring_idx = 0, pos = 0; in BCMPOSTTRAPFN()
1200 SI_MSG(("si_gci_enable_gpio:rngidx is %d, pos is %d, val is %d, mask is 0x%04x," in BCMPOSTTRAPFN()
1201 " value is 0x%04x\n", in BCMPOSTTRAPFN()
1204 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, ring_idx); in BCMPOSTTRAPFN()
1206 si_gpiocontrol(sih, mask, 0, GPIO_HI_PRIORITY); in BCMPOSTTRAPFN()
1229 if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiocontrol), 0, 0) & mask) { in si_gpio_enable()
1248 for (bit = 0; mask; bit++) { in si_gpio_enable()
1256 si_gpioouten(sih, mask, 0, GPIO_HI_PRIORITY); in si_gpio_enable()
1274 host_wake_gpio = host_wake_opt & 0xff; in BCMATTACHFN()
1294 state ? 1 << gpio : 0x00); in BCMPOSTTRAPFN()
1297 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMPOSTTRAPFN()
1313 state ? 1 << gpio : 0x00); in si_gci_time_sync_gpio_enable()
1316 SI_ERROR(("Time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_gci_time_sync_gpio_enable()
1343 time_sync_gpio = time_sync_opt & 0xff; in BCMATTACHFN()
1345 1 << time_sync_gpio, 0x00); in BCMATTACHFN()
1348 SI_ERROR(("time sync not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1383 GCI_INTSTATUS_GPIOINT, 0); in si_gci_enable_gpioint()
1411 uint8 chipcontrol = 0; in BCMPOSTTRAPFN()
1412 uint32 pmu_chipcontrol2 = 0; in BCMPOSTTRAPFN()
1430 pmu_chipcontrol2 = si_pmu_chipcontrol(sih, PMU_CHIPCTL2, 0, 0); in BCMPOSTTRAPFN()
1432 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, ~0, pmu_chipcontrol2); in BCMPOSTTRAPFN()
1444 uint8 chipcontrol = 0; in si_gci_free_wake_pin()
1450 wake_events = si_gci_gpio_intmask(sih, gpio_n, 0, 0); in si_gci_free_wake_pin()
1451 si_gci_gpio_intmask(sih, gpio_n, wake_events, 0); in si_gci_free_wake_pin()
1452 wake_events = si_gci_gpio_wakemask(sih, gpio_n, 0, 0); in si_gci_free_wake_pin()
1453 si_gci_gpio_wakemask(sih, gpio_n, wake_events, 0); in si_gci_free_wake_pin()
1473 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in BCMATTACHFN()
1538 si_gci_gpio_chipcontrol(sih, 0, in si_enable_device_wake()
1542 si_gci_indirect(sih, 0, in si_enable_device_wake()
1548 SI_ERROR(("0x%04x: don't know about device_wake_opt %d\n", in si_enable_device_wake()
1553 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip))); in si_enable_device_wake()
1655 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, 0); in si_gci_gpioint_handler_process()
1656 gpio_status[0] = si_corereg(sih, GCI_CORE_IDX(sih), in si_gci_gpioint_handler_process()
1657 GCI_OFFSETOF(sih, gci_gpiostatus), 0, 0); in si_gci_gpioint_handler_process()
1661 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_gpiostatus), ~0, gpio_status[0]); in si_gci_gpioint_handler_process()
1663 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, 1); in si_gci_gpioint_handler_process()
1665 GCI_OFFSETOF(sih, gci_gpiostatus), 0, 0); in si_gci_gpioint_handler_process()
1669 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_gpiostatus), ~0, gpio_status[1]); in si_gci_gpioint_handler_process()
1673 SI_MSG(("si_gci_gpioint_handler_process: status 0x%04x, 0x%04x\n", in si_gci_gpioint_handler_process()
1674 gpio_status[0], gpio_status[1])); in si_gci_gpioint_handler_process()
1678 status = ((gpio_status[0] >> (gci_i->gci_gpio * 4)) & 0x0F); in si_gci_gpioint_handler_process()
1680 status = ((gpio_status[1] >> ((gci_i->gci_gpio - 8) * 4)) & 0x0F); in si_gci_gpioint_handler_process()
1697 gci_intstatus = si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_intstat), 0, 0); in si_gci_handler_process()
1700 SI_MSG(("si_gci_handler_process: gci_intstatus is 0x%04x\n", gci_intstatus)); in si_gci_handler_process()
1735 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_chipctrl), ALLONES_32, 0x0080000); //0x200 in si_gci_seci_init()
1737 si_gci_indirect(sih, 1, GCI_OFFSETOF(sih, gci_gpioctl), ALLONES_32, 0x00010280); //0x044 in si_gci_seci_init()
1739 /* baudrate:4Mbps at 40MHz xtal, escseq:0xdb, high baudrate, enable seci_tx/rx */ in si_gci_seci_init()
1740 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secibauddiv), //0x1e0 in si_gci_seci_init()
1741 ALLONES_32, 0xF6); in si_gci_seci_init()
1742 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_baudadj), ALLONES_32, 0xFF); //0x1f8 in si_gci_seci_init()
1743 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secifcr), ALLONES_32, 0x00); //0x1e4 in si_gci_seci_init()
1744 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x08); //0x1ec in si_gci_seci_init()
1745 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0xA8); //0x1e8 in si_gci_seci_init()
1746 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartescval), //0x1d0 in si_gci_seci_init()
1747 ALLONES_32, 0xDB); in si_gci_seci_init()
1750 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_miscctl), ALLONES_32, 0xFFFF); //0xc54 in si_gci_seci_init()
1753 si_gci_indirect(sih, 0, in si_gci_seci_init()
1754 GCI_OFFSETOF(sih, gci_seciin_ctrl), ALLONES_32, 0x161); //0x218 in si_gci_seci_init()
1755 si_gci_indirect(sih, 0, in si_gci_seci_init()
1756 GCI_OFFSETOF(sih, gci_seciout_ctrl), ALLONES_32, 0x10051); //0x21c in si_gci_seci_init()
1758 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciout_txen_txbr), ALLONES_32, 0x01); //0x224 in si_gci_seci_init()
1762 si_gci_indirect(sih, 0, in si_gci_seci_init()
1763 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x13121110); //0x1bc in si_gci_seci_init()
1765 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x17161514); in si_gci_seci_init()
1767 GCI_OFFSETOF(sih, gci_secif0rx_offset), ALLONES_32, 0x1b1a1918); in si_gci_seci_init()
1769 /* first 12 nibbles configured for format-0 */ in si_gci_seci_init()
1771 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_seciusef0tx_reg), //0x1b4 in si_gci_seci_init()
1772 ALLONES_32, 0xFFF); // first 12 nibbles in si_gci_seci_init()
1774 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_secitx_datatag), in si_gci_seci_init()
1775 ALLONES_32, 0x0F0); // gci_secitx_datatag(nibbles 4 to 7 tagged) in si_gci_seci_init()
1776 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_secirx_datatag), in si_gci_seci_init()
1777 ALLONES_32, 0x0F0); // gci_secirx_datatag(nibbles 4 to 7 tagged) in si_gci_seci_init()
1780 si_gci_indirect(sih, 0, in si_gci_seci_init()
1781 GCI_OFFSETOF(sih, gci_secif0tx_offset), 0xFFFFFFFF, 0x76543210); //0x1b8 in si_gci_seci_init()
1783 GCI_OFFSETOF(sih, gci_secif0tx_offset), 0xFFFFFFFF, 0x0000ba98); in si_gci_seci_init()
1795 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_control_0), ALLONES_32, 0x00000000); in si_gci_seci_init()
1796 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_control_1), ALLONES_32, 0x00000000); in si_gci_seci_init()
1904 udata = si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartdata), 0, 0); in si_wci2_rxfifo_intr_handler_process()
1921 udata = si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartdata), 0, 0); in si_wci2_rxfifo_intr_handler_process()
1929 wci2_info->rx_idx = 0; in si_wci2_rxfifo_intr_handler_process()
1970 |(0 << GCI_CCTL_SECIEN_OFFSET) in si_ercx_init()
2009 si_config_gcigpio(sih, GCI_LTE_FRAMESYNC_POS, fsync_gcigpio, 0xFF, in si_ercx_init()
2013 si_config_gcigpio(sih, GCI_LTE_RX_POS, lterx_gcigpio, 0xFF, in si_ercx_init()
2017 si_config_gcigpio(sih, GCI_LTE_TX_POS, ltetx_gcigpio, 0xFF, in si_ercx_init()
2023 si_config_gcigpio(sih, GCI_WLAN_PRIO_POS, wlprio_gcigpio, 0xFF, in si_ercx_init()
2036 |(0 << GCI_BITOFFSET(GCI_LTE_RX_POS)) in si_ercx_init()
2037 |(0 << GCI_BITOFFSET(GCI_LTE_TX_POS)))); in si_ercx_init()
2078 |(0 << GCI_CCTL_BRKONSLP_OFFSET) in si_wci2_init()
2079 |(0 << GCI_CCTL_US_OFFSET) in si_wci2_init()
2081 |(0 << GCI_CCTL_FSL_OFFSET) in si_wci2_init()
2099 |(0 << GCI_BITOFFSET(GCI_LTE_RX_POS)) in si_wci2_init()
2100 |(0 << GCI_BITOFFSET(GCI_LTE_TX_POS)))); in si_wci2_init()
2119 (0xFF << (gcigpioin%4)*8), in si_wci2_init()
2132 (0xFF << (gcigpioout%4)*8), in si_wci2_init()
2162 0x0000); in si_wci2_init()
2164 /* baudrate: 1/2/3/4mbps, escseq:0xdb, high baudrate, enable seci_tx/rx */ in si_wci2_init()
2165 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secifcr), ALLONES_32, 0x00); in si_wci2_init()
2168 ALLONES_32, 0x00); in si_wci2_init()
2170 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0x00); in si_wci2_init()
2172 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_secilcr), ALLONES_32, 0x28); in si_wci2_init()
2174 si_gci_direct(sih, GCI_OFFSETOF(sih, gci_seciuartescval), ALLONES_32, 0xDB); in si_wci2_init()
2181 ALLONES_32, 0xFE); in si_wci2_init()
2184 ALLONES_32, 0xFE); in si_wci2_init()
2188 ALLONES_32, 0x80); in si_wci2_init()
2191 ALLONES_32, 0x80); in si_wci2_init()
2194 ALLONES_32, 0x81); in si_wci2_init()
2197 ALLONES_32, 0x23); in si_wci2_init()
2208 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xFF); in si_wci2_init()
2211 ALLONES_32, 0xFF); in si_wci2_init()
2215 GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x80); in si_wci2_init()
2218 ALLONES_32, 0x80); in si_wci2_init()
2221 ALLONES_32, 0x0); in si_wci2_init()
2226 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xFF); in si_wci2_init()
2229 ALLONES_32, 0xFF); in si_wci2_init()
2233 GCI_OFFSETOF(sih, gci_secimcr), ALLONES_32, 0x80); in si_wci2_init()
2236 ALLONES_32, 0x80); in si_wci2_init()
2239 ALLONES_32, 0x81); in si_wci2_init()
2242 ALLONES_32, 0x11); in si_wci2_init()
2250 ALLONES_32, 0xF7); in si_wci2_init()
2253 ALLONES_32, 0xF7); in si_wci2_init()
2257 ALLONES_32, 0x8); in si_wci2_init()
2260 ALLONES_32, 0x8); in si_wci2_init()
2263 ALLONES_32, 0x9); in si_wci2_init()
2266 ALLONES_32, 0x0); in si_wci2_init()
2277 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF6); in si_wci2_init()
2280 ALLONES_32, 0xF6); in si_wci2_init()
2285 * set bauddiv to 0xF4 to achieve 2.5M for Xtal/2 @ 29.9MHz in si_wci2_init()
2290 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF4); in si_wci2_init()
2293 ALLONES_32, 0xF4); in si_wci2_init()
2298 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF1); in si_wci2_init()
2301 ALLONES_32, 0xF1); in si_wci2_init()
2306 ALLONES_32, 0x8); in si_wci2_init()
2309 ALLONES_32, 0x8); in si_wci2_init()
2312 ALLONES_32, 0x9); in si_wci2_init()
2315 ALLONES_32, 0x0); in si_wci2_init()
2327 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF7); in si_wci2_init()
2330 ALLONES_32, 0xF7); in si_wci2_init()
2335 GCI_OFFSETOF(sih, gci_secibauddiv), ALLONES_32, 0xF4); in si_wci2_init()
2338 ALLONES_32, 0xF4); in si_wci2_init()
2343 ALLONES_32, 0x8); in si_wci2_init()
2346 ALLONES_32, 0x8); in si_wci2_init()
2349 ALLONES_32, 0x9); in si_wci2_init()
2352 ALLONES_32, 0x0); in si_wci2_init()
2372 si_gci_indirect(sih, 0, in si_wci2_init()
2373 GCI_OFFSETOF(sih, gci_gpioctl), 0x20000000, 0x20000010); in si_wci2_init()
2375 GCI_OFFSETOF(sih, gci_gpioctl), 0x20202020, 0x20202020); in si_wci2_init()
2377 * pat[0]-gpio4, pat[1]-gpio3 in si_wci2_init()
2379 si_gci_indirect(sih, 0x70010, in si_wci2_init()
2380 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000001, 0x00000001); in si_wci2_init()
2381 si_gci_indirect(sih, 0x60010, in si_wci2_init()
2382 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000002, 0x00000002); in si_wci2_init()
2383 si_gci_indirect(sih, 0x50010, in si_wci2_init()
2384 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000004, 0x00000004); in si_wci2_init()
2385 si_gci_indirect(sih, 0x40010, in si_wci2_init()
2386 GCI_OFFSETOF(sih, gci_gpiomask), 0x02000000, 0x00000008); in si_wci2_init()
2387 si_gci_indirect(sih, 0x30010, in si_wci2_init()
2388 GCI_OFFSETOF(sih, gci_gpiomask), 0x04000000, 0x04000010); in si_wci2_init()
2390 si_gci_indirect(sih, 0x50000, in si_wci2_init()
2391 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000010, 0x00000010); in si_wci2_init()
2392 si_gci_indirect(sih, 0x40000, in si_wci2_init()
2393 GCI_OFFSETOF(sih, gci_gpiomask), 0x00000020, 0x00000020); in si_wci2_init()
2396 GCI_OFFSETOF(sih, gci_control_0), 0x00000030, 0x00000000); in si_wci2_init()
2419 |(0 << GCI_CCTL_BRKONSLP_OFFSET) in si_btcx_wci2_init()
2420 |(0 << GCI_CCTL_US_OFFSET) in si_btcx_wci2_init()
2422 |(0 << GCI_CCTL_FSL_OFFSET) in si_btcx_wci2_init()
2437 hndgci_uart_config_rx_complete(-1, -1, 0, NULL, NULL); in si_gci_uart_init()
2476 return 0; in BCMPOSTTRAPFN()
2483 uint32 reg = 0, pos = 0; in BCMPOSTTRAPFN()
2495 uint32 reg = 0, pos = 0, temp; in si_gci_get_functionsel()
2510 for (i = 0; i <= CC_PIN_GPIO_LAST; i++) { in si_gci_clear_functionsel()
2520 /* because NFLASH and GCI clashes in 0xC00 */ in BCMPOSTTRAPFN()
2521 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2523 ASSERT(0); in BCMPOSTTRAPFN()
2527 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, reg); in BCMPOSTTRAPFN()
2535 /* because NFLASH and GCI clashes in 0xC00 */ in BCMPOSTTRAPFN()
2536 if ((CCREV(sih->ccrev) == 38) && ((sih->chipst & (1 << 4)) != 0)) { in BCMPOSTTRAPFN()
2538 ASSERT(0); in BCMPOSTTRAPFN()
2542 si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_indirect_addr), ~0, reg); in BCMPOSTTRAPFN()
2543 /* setting mask and value to '0' to use si_corereg for read only purpose */ in BCMPOSTTRAPFN()
2544 return si_corereg(sih, GCI_CORE_IDX(sih), GCI_OFFSETOF(sih, gci_chipsts), 0, 0); in BCMPOSTTRAPFN()
2562 ASSERT(sii->chipnew == 0); in BCMATTACHFN()
2596 return 0; in BCMPOSTTRAPFN()
2613 sih->err_info->count = 0; in si_reset_axi_errlog_info()
2711 uint err_at = 0; in BCMATTACHFN()
2715 savewin = 0; in BCMATTACHFN()
2723 sii->second_bar0win = ~0x0; in BCMATTACHFN()
2740 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) { in BCMATTACHFN()
2742 "devid:0x%x\n", devid)); in BCMATTACHFN()
2784 * We assume we can read chipid at offset 0 from the regs arg. in BCMATTACHFN()
2795 if ((w & 0xfffff) == 148277) w -= 65532; in BCMATTACHFN()
2831 if ((sii->numcores = nci_scan(sih)) == 0u) { in BCMATTACHFN()
2847 SI_MSG(("Found chip type SB (0x%08x)\n", w)); in BCMATTACHFN()
2854 SI_MSG(("Found chip type AI (0x%08x)\n", w)); in BCMATTACHFN()
2856 SI_MSG(("Found chip type NAI (0x%08x)\n", w)); in BCMATTACHFN()
2858 SI_MSG(("Found chip type DVT (0x%08x)\n", w)); in BCMATTACHFN()
2866 if (sii->axi_num_wrappers == 0) { in BCMATTACHFN()
2867 SI_ERROR(("FATAL: Wrapper count 0\n")); in BCMATTACHFN()
2873 SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip)); in BCMATTACHFN()
2877 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w)); in BCMATTACHFN()
2883 if (sii->numcores == 0) { in BCMATTACHFN()
2895 /* Set the clkdiv2 divisor bits (2:0) to 0x4 if srom is present */ in BCMATTACHFN()
2921 pcie_set_L1_entry_time(sii->pch, 0x40); in BCMATTACHFN()
3040 sii->nvram_min_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3047 sii->nvram_max_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3058 sii->armpllclkfreq = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
3059 ASSERT(sii->armpllclkfreq > 0); in BCMATTACHFN()
3061 sii->armpllclkfreq = 0; in BCMATTACHFN()
3075 hnd_tcam_bootloader_load(si_setcore(sih, ARMCR4_CORE_ID, 0), pvars); in BCMATTACHFN()
3077 hnd_tcam_bootloader_load(si_setcore(sih, SYSMEM_CORE_ID, 0), pvars); in BCMATTACHFN()
3079 hnd_tcam_bootloader_load(si_setcore(sih, SOCRAM_CORE_ID, 0), pvars); in BCMATTACHFN()
3086 uint32 gpiopullup = 0, gpiopulldown = 0; in BCMATTACHFN()
3087 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMATTACHFN()
3094 if (value != 0xFFFFFFFF) { /* non populated SROM fields are ffff */ in BCMATTACHFN()
3132 CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_MASK), 0u); in BCMATTACHFN()
3166 if (xtalfreq == 0) in BCMATTACHFN()
3174 if (xtalfreq == 0) in BCMATTACHFN()
3182 sii->spurmode = getintvar(pvars, rstr_spurconfig) & 0xf; in BCMATTACHFN()
3241 CHIPC_REG(sih, clk_ctl_st, CCS_SFLASH_CLKREQ, 0); in BCMATTACHFN()
3336 for (idx = 0; idx < SI_MAXCORES; idx++) { in BCMATTACHFN()
3444 ASSERT(0); in BCMPOSTTRAPFN()
3445 return 0; in BCMPOSTTRAPFN()
3463 ASSERT(0); in si_flag()
3464 return 0; in si_flag()
3478 ASSERT(0); in si_flag_alt()
3479 return 0; in si_flag_alt()
3497 ASSERT(0); in BCMATTACHFN()
3506 return 0; in si_oobr_baseaddr()
3514 ASSERT(0); in si_oobr_baseaddr()
3515 return 0; in si_oobr_baseaddr()
3569 coreunit = 0; in si_coreunit()
3577 for (i = 0; i < idx; i++) in si_coreunit()
3598 ASSERT(0); in BCMATTACHFN()
3599 return 0; in BCMATTACHFN()
3606 return ((sih->cccaps & CC_CAP_BKPLN64) != 0); in BCMINITFN()
3623 ASSERT(0); in BCMPOSTTRAPFN()
3624 return 0; in BCMPOSTTRAPFN()
3637 return 0; in si_corerev_minor()
3654 found = 0; in BCMPOSTTRAPFN()
3656 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3670 if (si_findcoreidx(sih, HWA_CORE_ID, 0) != BADIDX) { in BCMPOSTTRAPFN()
3679 if (si_findcoreidx(sih, SYSMEM_CORE_ID, 0) != BADIDX) { in BCMPOSTTRAPFN()
3707 uint found = 0; in BCMPOSTTRAPFN()
3713 for (i = 0; i < sii->numcores; i++) { in BCMPOSTTRAPFN()
3796 ASSERT(0); in BCMPOSTTRAPFN()
3815 ASSERT(0); in BCMPOSTTRAPFN()
3840 cc = si_setcore(sih, coreid, 0); in BCMPOSTTRAPFN()
3902 ASSERT(0); in BCMATTACHFN()
3903 return 0; in BCMATTACHFN()
3928 ASSERT(0); in si_addrspace()
3929 return 0; in si_addrspace()
3953 ASSERT(0); in BCMATTACHFN()
3954 return 0; in BCMATTACHFN()
3969 *size = 0; in si_coreaddrspaceX()
3986 ASSERT(0); in BCMPOSTTRAPFN()
3987 return 0; in BCMPOSTTRAPFN()
4005 ASSERT(0); in si_core_cflags_wo()
4022 ASSERT(0); in si_core_sflags()
4023 return 0; in si_core_sflags()
4041 ASSERT(0); in si_commit()
4059 ASSERT(0); in BCMPOSTTRAPFN()
4075 return 0; in BCMPOSTTRAPFN()
4078 * it uses secondary bar-0 window which lies at an offset of 16K from primary bar-0
4086 * [11 : 0] should be the "regoff"
4087 * for reading 4 bytes from reg 0x200 of d11 core use it like below
4088 * : si_backplane_access(sih, 0x18001000, 0x200, 4, 0, TRUE)
4096 if (addr & 0x1) { in si_backplane_addr_sane()
4102 if (addr & 0x3) { in si_backplane_addr_sane()
4114 sii->second_bar0win = ~0x0; in si_invalidate_second_bar0win()
4121 uint32 region = 0; in si_backplane_access()
4131 region = (addr & (0xFFFFF << 12)); in si_backplane_access()
4132 addr = addr & 0xFFF; in si_backplane_access()
4145 * sii->curmap : bar-0 virtual address in si_backplane_access()
4146 * PCI_SECOND_BAR0_OFFSET : secondar bar-0 offset in si_backplane_access()
4194 uint32 region = 0; in si_backplane_access_64()
4204 region = (addr & (0xFFFFF << 12)); in si_backplane_access_64()
4205 addr = addr & 0xFFF; in si_backplane_access_64()
4220 * sii->curmap : bar-0 virtual address in si_backplane_access_64()
4221 * PCI_SECOND_BAR0_OFFSET : secondar bar-0 offset in si_backplane_access_64()
4259 ASSERT(0); in BCMPOSTTRAPFN()
4260 return 0; in BCMPOSTTRAPFN()
4296 if (mask != 0 && PMUREV(sih->pmurev) >= 22 && in BCMPOSTTRAPFN()
4301 while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING) in BCMPOSTTRAPFN()
4329 return 0; in BCMPOSTTRAPFN()
4368 int result = 0; in si_corebist()
4371 cflags = si_core_cflags(sih, 0, 0); in si_corebist()
4374 si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC)); in si_corebist()
4377 SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000); in si_corebist()
4379 if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR) in si_corebist()
4383 si_core_cflags(sih, 0xffff, cflags); in si_corebist()
4391 uint idx = si_findcoreidx(sih, coreid, 0); in si_num_slaveports()
4392 uint num = 0; in si_num_slaveports()
4411 uint32 addr = 0x0; in si_get_slaveport_addr()
4435 uint32 addr = 0x0; in si_get_d11_slaveport_addr()
4463 default: return 0; in BCMINITFN()
4474 return div ? clock / div : 0; in divide_clock()
4506 ASSERT(0); in BCMINITFN()
4514 if (clock == 0) in BCMINITFN()
4515 return 0; in BCMINITFN()
4539 default: return (0); in BCMINITFN()
4551 if ((mc & CC_T2MC_M1BYP) == 0) in BCMINITFN()
4553 if ((mc & CC_T2MC_M2BYP) == 0) in BCMINITFN()
4555 if ((mc & CC_T2MC_M3BYP) == 0) in BCMINITFN()
4569 uint hosti = 0; in si_chip_hostif()
4582 /* chippkg bit-0 == 0 is PCIE only pkgs in si_chip_hostif()
4583 * chippkg bit-0 == 1 has both PCIE and USB cores enabled in si_chip_hostif()
4585 if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB)) in si_chip_hostif()
4639 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMINITFN()
4700 maxt = 0xffffffff; in si_watchdog()
4713 PMU_REG_NEW(sih, min_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
4714 PMU_REG_NEW(sih, watchdog_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
4716 PMU_REG_NEW(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, 0); in si_watchdog()
4717 SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO), in si_watchdog()
4721 pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks); in si_watchdog()
4732 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, in si_watchdog()
4736 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks); in si_watchdog()
4768 ASSERT(0); in si_taclear()
4788 return 0xffff; in BCMATTACHFN()
4792 if ((device = (uint16)si_getdevpathintvar(sih, rstr_devid)) != 0) in BCMATTACHFN()
4795 else if ((device = (uint16)getintvar(sii->vars, rstr_devid)) != 0) in BCMATTACHFN()
4798 else if ((device = (uint16)getintvar(sii->vars, rstr_wl0id)) != 0) in BCMATTACHFN()
4804 device = 0xffff; in BCMATTACHFN()
4814 uint16 vendor = 0xffff, device = 0xffff; in BCMATTACHFN()
4815 uint8 class, subclass, progif = 0; in BCMATTACHFN()
4880 progif = 0x10; /* OHCI */ in BCMATTACHFN()
4887 progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI value defined in spec */ in BCMATTACHFN()
4899 progif = 0x30; /* XHCI */ in BCMATTACHFN()
4940 class = subclass = progif = 0xff; in BCMATTACHFN()
4952 return 0; in BCMATTACHFN()
4978 ASSERT(0); in si_dumpregs()
5001 ASSERT(0); in si_view()
5022 for (i = 0; i < sii->numcores; i++) { in si_viewall()
5083 ASSERT(0); in si_slowclk_freq()
5090 return (0); in si_slowclk_freq()
5125 uint origidx = 0; in BCMINITFN()
5136 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
5162 uint origidx = 0; in BCMINITFN()
5177 return 0; in BCMINITFN()
5180 fpdelay = 0; in BCMINITFN()
5184 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
5193 if (slowminfreq > 0) in BCMINITFN()
5236 return (0); in si_clkctl_xtal()
5272 return 0; in si_clkctl_xtal()
5278 return (0); in si_clkctl_xtal()
5307 uint origidx = 0; in _si_clkctl_cc()
5323 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); in _si_clkctl_cc()
5346 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0), in _si_clkctl_cc()
5375 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0), in _si_clkctl_cc()
5385 ASSERT(0); in _si_clkctl_cc()
5405 if (!path || size <= 0) in BCMNMIATTACHFN()
5420 SI_ERROR(("si_devpath: device 0 assumed\n")); in BCMNMIATTACHFN()
5426 ASSERT(0); in BCMNMIATTACHFN()
5430 if (slen < 0 || slen >= size) { in BCMNMIATTACHFN()
5431 path[0] = '\0'; in BCMNMIATTACHFN()
5435 return 0; in BCMNMIATTACHFN()
5444 if (!path || size <= 0) in BCMNMIATTACHFN()
5452 return 0; in BCMNMIATTACHFN()
5465 int len3 = 0; in BCMATTACHFN()
5478 if (si_devpath(sih, devpath, SI_DEVPATH_BUFSZ) == 0) { in BCMATTACHFN()
5485 for (idx = 0; idx < SI_MAXCORES; idx++) { in BCMATTACHFN()
5497 if ((len1 == len2) && (memcmp(p, devpath, len1) == 0)) { in BCMATTACHFN()
5503 if (len3 && (len3 == len2) && (memcmp(p, devpath_pcie, len3) == 0)) { in BCMATTACHFN()
5551 if ((val = getintvar(NULL, varname)) != 0) in BCMATTACHFN()
5556 if ((val = getintvar(NULL, varname)) != 0) in BCMATTACHFN()
5562 return 0; in BCMATTACHFN()
5571 * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
5572 * On overflow, the first char will be set to '\0'.
5579 if (!var || len <= 0) in BCMATTACHFN()
5582 if (si_devpath(sih, var, len) == 0) { in BCMATTACHFN()
5586 var[0] = '\0'; in BCMATTACHFN()
5599 if (!var || len <= 0) in BCMATTACHFN()
5602 if (si_devpath_pcie(sih, var, len) == 0) { in BCMATTACHFN()
5606 var[0] = '\0'; in BCMATTACHFN()
5618 uint32 reg_val = 0; in BCMPOSTTRAPFN()
5624 return 0; in BCMPOSTTRAPFN()
5635 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in sih_write_sraon()
5637 while (len > 0) { in sih_write_sraon()
5654 pmu_var->pmu_control = si_ccreg(sih, PMU_CTL, 0, 0); in si_dump_pmu()
5655 pmu_var->pmu_capabilities = si_ccreg(sih, PMU_CAP, 0, 0); in si_dump_pmu()
5656 pmu_var->pmu_status = si_ccreg(sih, PMU_ST, 0, 0); in si_dump_pmu()
5657 pmu_var->res_state = si_ccreg(sih, PMU_RES_STATE, 0, 0); in si_dump_pmu()
5658 pmu_var->res_pending = si_ccreg(sih, PMU_RES_PENDING, 0, 0); in si_dump_pmu()
5659 pmu_var->pmu_timer1 = si_ccreg(sih, PMU_TIMER, 0, 0); in si_dump_pmu()
5660 pmu_var->min_res_mask = si_ccreg(sih, MINRESMASKREG, 0, 0); in si_dump_pmu()
5661 pmu_var->max_res_mask = si_ccreg(sih, MAXRESMASKREG, 0, 0); in si_dump_pmu()
5662 pmu_chip_ctl_reg = (pmu_var->pmu_capabilities & 0xf8000000); in si_dump_pmu()
5664 for (i = 0; i < pmu_chip_ctl_reg; i++) { in si_dump_pmu()
5665 pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0); in si_dump_pmu()
5667 pmu_chip_reg_reg = (pmu_var->pmu_capabilities & 0x07c00000); in si_dump_pmu()
5669 for (i = 0; i < pmu_chip_reg_reg; i++) { in si_dump_pmu()
5670 pmu_var->pmu_regcontrol[i] = si_pmu_vreg_control(sih, i, 0, 0); in si_dump_pmu()
5672 pmu_chip_pll_reg = (pmu_var->pmu_capabilities & 0x003e0000); in si_dump_pmu()
5674 for (i = 0; i < pmu_chip_pll_reg; i++) { in si_dump_pmu()
5675 pmu_var->pmu_pllcontrol[i] = si_pmu_pllcontrol(sih, i, 0, 0); in si_dump_pmu()
5677 pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00); in si_dump_pmu()
5679 for (i = 0; i < pmu_chip_res_reg; i++) { in si_dump_pmu()
5680 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmu()
5682 RSRCUPDWNTIME, 0, 0); in si_dump_pmu()
5684 pmu_chip_res_reg = (pmu_var->pmu_capabilities & 0x00001f00); in si_dump_pmu()
5686 for (i = 0; i < pmu_chip_res_reg; i++) { in si_dump_pmu()
5687 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmu()
5688 pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0); in si_dump_pmu()
5696 chipcregs_t *cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_pmu_keep_on()
5719 chipcregs_t *cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_pmu_keep_on_get()
5726 for (i = 0; i < PMU_RES; i++) { in si_pmu_keep_on_get()
5735 return 0; in si_pmu_keep_on_get()
5741 uint32 i = 0x0; in si_power_island_set()
5744 int cnt = 0; in si_power_island_set()
5745 for (k = 0; k < ARRAYSIZE(si_power_island_test_array); k++) { in si_power_island_set()
5750 if (cnt > 0) { in si_power_island_set()
5752 i = i | 0x1; in si_power_island_set()
5755 i = i | 0x2; in si_power_island_set()
5758 i = i | 0x4; in si_power_island_set()
5761 i = i | 0x8; in si_power_island_set()
5763 j = (i << 18) & 0x003c0000; in si_power_island_set()
5764 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x003c0000, j); in si_power_island_set()
5766 return 0; in si_power_island_set()
5775 uint32 sc_on = 0x0; in si_power_island_get()
5776 uint32 phy_on = 0x0; in si_power_island_get()
5777 uint32 vddm_on = 0x0; in si_power_island_get()
5778 uint32 memlpldo_on = 0x0; in si_power_island_get()
5781 reg_val = si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0, 0); in si_power_island_get()
5806 return 0; in si_pciereg()
5819 return 0; in si_pcieserdesreg()
5884 ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0)); in si_sdio_init()
5888 sdpregs = (sdpcmd_regs_t *)si_setcore(sih, SDIOD_CORE_ID, 0); in si_sdio_init()
5955 return (0); in si_pcie_get_maxpayload_size()
5977 return (0); in BCMATTACHFN()
5988 return (0); in si_pcie_get_ssid()
5999 return (0); in si_pcie_get_bar0()
6070 do_4360_pcie2_war = 0; in BCMUNINITFN()
6098 uint32 siflag = 0, w; in BCMATTACHFN()
6099 uint idx = 0; in BCMATTACHFN()
6165 if (si_setcore(sih, ARMCR4_CORE_ID, 0) != NULL || in BCMATTACHFN()
6166 si_setcore(sih, ARMCA7_CORE_ID, 0) != NULL) { in BCMATTACHFN()
6193 if ((oobrregs = si_setcore(sih, HND_OOBR_CORE_ID, 0)) == NULL) { in BCMATTACHFN()
6207 if (main_intr < 0) { in BCMATTACHFN()
6223 if ((ret = main_intr) < 0 || (ret = alt_intr) < 0) { in BCMATTACHFN()
6242 ASSERT(main_intr >= 0); in BCMATTACHFN()
6277 return 0; in si_pcieclkreq()
6288 return 0; in si_pcielcreg()
6299 return 0; in si_pcieltrenable()
6310 return 0; in BCMATTACHFN()
6321 return 0; in si_pcieltr_reg()
6332 return 0; in si_pcieltrspacing_reg()
6343 return 0; in si_pcieltrhysteresiscnt_reg()
6376 return 0; in si_pcie_get_L1substate()
6421 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE2_CORE_ID, 0); in si_pci_fixcfg()
6425 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE_CORE_ID, 0); in si_pci_fixcfg()
6429 pciregs = (sbpciregs_t *)si_setcore(&sii->pub, PCI_CORE_ID, 0); in si_pci_fixcfg()
6449 return 0; in si_pci_fixcfg()
6472 if (!(sih->pmurev == 0x11 || (sih->pmurev >= 0x15 && sih->pmurev <= 0x19))) { in si_dump_pmuregs()
6476 pmu_cap = si_ccreg(sih, PMU_CAP, 0, 0); in si_dump_pmuregs()
6477 bcm_bprintf(b, "pmu_control 0x%x\n", si_ccreg(sih, PMU_CTL, 0, 0)); in si_dump_pmuregs()
6478 bcm_bprintf(b, "pmu_capabilities 0x%x\n", pmu_cap); in si_dump_pmuregs()
6479 bcm_bprintf(b, "pmu_status 0x%x\n", si_ccreg(sih, PMU_ST, 0, 0)); in si_dump_pmuregs()
6480 bcm_bprintf(b, "res_state 0x%x\n", si_ccreg(sih, PMU_RES_STATE, 0, 0)); in si_dump_pmuregs()
6481 bcm_bprintf(b, "res_pending 0x%x\n", si_ccreg(sih, PMU_RES_PENDING, 0, 0)); in si_dump_pmuregs()
6482 bcm_bprintf(b, "pmu_timer1 %d\n", si_ccreg(sih, PMU_TIMER, 0, 0)); in si_dump_pmuregs()
6483 bcm_bprintf(b, "min_res_mask 0x%x\n", si_ccreg(sih, MINRESMASKREG, 0, 0)); in si_dump_pmuregs()
6484 bcm_bprintf(b, "max_res_mask 0x%x\n", si_ccreg(sih, MAXRESMASKREG, 0, 0)); in si_dump_pmuregs()
6486 pmu_chip_reg = (pmu_cap & 0xf8000000); in si_dump_pmuregs()
6489 for (i = 0; i < pmu_chip_reg; i++) { in si_dump_pmuregs()
6490 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_chipcontrol(sih, i, 0, 0)); in si_dump_pmuregs()
6493 pmu_chip_reg = (pmu_cap & 0x07c00000); in si_dump_pmuregs()
6496 for (i = 0; i < pmu_chip_reg; i++) { in si_dump_pmuregs()
6497 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_vreg_control(sih, i, 0, 0)); in si_dump_pmuregs()
6499 pmu_chip_reg = (pmu_cap & 0x003e0000); in si_dump_pmuregs()
6502 for (i = 0; i < pmu_chip_reg; i++) { in si_dump_pmuregs()
6503 bcm_bprintf(b, "[%d]=0x%x ", i, si_pmu_pllcontrol(sih, i, 0, 0)); in si_dump_pmuregs()
6505 pmu_chip_reg = (pmu_cap & 0x0001e000); in si_dump_pmuregs()
6508 for (i = 0; i < pmu_chip_reg; i++) { in si_dump_pmuregs()
6509 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmuregs()
6510 bcm_bprintf(b, "[%d]=0x%x ", i, si_corereg(sih, SI_CC_IDX, RSRCUPDWNTIME, 0, 0)); in si_dump_pmuregs()
6512 pmu_chip_reg = (pmu_cap & 0x00001f00); in si_dump_pmuregs()
6515 for (i = 0; i < pmu_chip_reg; i++) { in si_dump_pmuregs()
6516 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i); in si_dump_pmuregs()
6517 bcm_bprintf(b, "[%d]=0x%x ", i, si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0)); in si_dump_pmuregs()
6543 bcm_bprintf(b, "si %p chip 0x%x chiprev 0x%x boardtype 0x%x boardvendor 0x%x bus %d\n", in si_dump()
6551 bcm_bprintf(b, "ccrev %d buscoretype 0x%x buscorerev %d curidx %d\n", in si_dump()
6560 for (i = 0; i < sii->numcores; i++) in si_dump()
6561 bcm_bprintf(b, "0x%x ", cores_info->coreid[i]); in si_dump()
6582 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_ccreg_dump()
6586 for (i = 0; i <= 0xc4; i += 4) { in si_ccreg_dump()
6587 if (i == 0x4c) { in si_ccreg_dump()
6591 bcm_bprintf(b, "0x%x\t0x%x\n", i, *(uint32 *)((uintptr)cc + i)); in si_ccreg_dump()
6596 for (i = 0x1e0; i <= 0x1e4; i += 4) { in si_ccreg_dump()
6597 bcm_bprintf(b, "0x%x\t0x%x\n", i, *(uint32 *)((uintptr)cc + i)); in si_ccreg_dump()
6602 for (i = 0x600; i <= 0x660; i += 4) { in si_ccreg_dump()
6603 bcm_bprintf(b, "0x%x\t0x%x\n", i, *(uint32 *)((uintptr)cc + i)); in si_ccreg_dump()
6626 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in si_clkctl_dump()
6629 bcm_bprintf(b, "pll_on_delay 0x%x fref_sel_delay 0x%x ", in si_clkctl_dump()
6632 bcm_bprintf(b, "slow_clk_ctl 0x%x ", cc->slow_clk_ctl); in si_clkctl_dump()
6634 bcm_bprintf(b, "system_clk_ctl 0x%x ", cc->system_clk_ctl); in si_clkctl_dump()
6635 bcm_bprintf(b, "clkstatestretch 0x%x ", cc->clkstatestretch); in si_clkctl_dump()
6639 bcm_bprintf(b, "gpioout 0x%x gpioouten 0x%x ", in si_clkctl_dump()
6665 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_gpiodump()
6670 bcm_bprintf(b, "gpioin 0x%x ", R_REG(sii->osh, &cc->gpioin)); in si_gpiodump()
6671 bcm_bprintf(b, "gpioout 0x%x ", R_REG(sii->osh, &cc->gpioout)); in si_gpiodump()
6672 bcm_bprintf(b, "gpioouten 0x%x ", R_REG(sii->osh, &cc->gpioouten)); in si_gpiodump()
6673 bcm_bprintf(b, "gpiocontrol 0x%x ", R_REG(sii->osh, &cc->gpiocontrol)); in si_gpiodump()
6674 bcm_bprintf(b, "gpiointpolarity 0x%x ", R_REG(sii->osh, &cc->gpiointpolarity)); in si_gpiodump()
6675 bcm_bprintf(b, "gpiointmask 0x%x ", R_REG(sii->osh, &cc->gpiointmask)); in si_gpiodump()
6683 return 0; in si_gpiodump()
6699 * If a gpiocontrol bit is set to 0, chipcommon controls the corresponding GPIO pin.
6708 regoff = 0; in BCMPOSTTRAPFN()
6730 regoff = 0; in BCMPOSTTRAPFN()
6752 regoff = 0; in BCMPOSTTRAPFN()
6777 return 0xffffffff; in si_gpioreserve()
6782 return 0xffffffff; in si_gpioreserve()
6787 return 0xffffffff; in si_gpioreserve()
6808 return 0xffffffff; in si_gpiorelease()
6813 return 0xffffffff; in si_gpiorelease()
6818 return 0xffffffff; in si_gpiorelease()
6833 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0)); in si_gpioin()
6890 return 0xffffffff; in si_gpiopull()
6902 return 0xffffffff; in si_gpioevent()
6911 return 0xffffffff; in si_gpioevent()
6922 return 0xffffffff; in BCMATTACHFN()
6925 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0))); in BCMATTACHFN()
6933 uint8 chipcontrol = 0; in si_gci_shif_config_wake_pin()
6963 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_intmask), in si_gci_shif_config_wake_pin()
6966 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_wakemask), in si_gci_shif_config_wake_pin()
6996 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_intmask), in si_gci_shif_config_wake_pin()
6999 si_gci_indirect(sih, 0, GCI_OFFSETOF(sih, gci_wakemask), in si_gci_shif_config_wake_pin()
7014 si_gci_gpio_intmask(sih, gpio_n, wake_events, 0); in si_shif_int_enable()
7015 si_gci_gpio_wakemask(sih, gpio_n, wake_events, 0); in si_shif_int_enable()
7044 uint memsize = 0; in si_sysmem_size()
7053 if (!(regs = si_setcore(sih, SYSMEM_CORE_ID, 0))) in si_sysmem_size()
7058 si_core_reset(sih, 0, 0); in si_sysmem_size()
7069 for (i = 0; i < nb; i++) in si_sysmem_size()
7109 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_set_bankpda()
7113 si_core_reset(sih, 0, 0); in si_socram_set_bankpda()
7123 si_core_disable(sih, 0); in si_socram_set_bankpda()
7142 uint memsize = 0; in si_socram_size()
7149 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_size()
7154 si_core_reset(sih, 0, 0); in si_socram_size()
7159 if (corerev == 0) in si_socram_size()
7168 if (lss != 0) in si_socram_size()
7171 if (lss != 0) in si_socram_size()
7182 for (i = 0; i < nb; i++) in si_socram_size()
7188 si_core_disable(sih, 0); in si_socram_size()
7205 uint ret = 0; in si_is_bus_mpu_present()
7210 cr4regs = si_setcore(sih, ARMCR4_CORE_ID, 0); in si_is_bus_mpu_present()
7215 sysmemregs = si_setcore(sih, SYSMEM_CORE_ID, 0); in si_is_bus_mpu_present()
7224 si_core_reset(sih, 0, 0); in si_is_bus_mpu_present()
7235 si_core_disable(sih, 0); in si_is_bus_mpu_present()
7256 uint memsize = 0; in si_tcm_size()
7257 uint banku_size = 0; in si_tcm_size()
7258 uint32 nab = 0; in si_tcm_size()
7259 uint32 nbb = 0; in si_tcm_size()
7260 uint32 totb = 0; in si_tcm_size()
7261 uint32 bxinfo = 0; in si_tcm_size()
7262 uint32 idx = 0; in si_tcm_size()
7272 if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0))) in si_tcm_size()
7290 for (idx = 0; idx < totb; idx++) { in si_tcm_size()
7304 si_core_disable(sih, 0); in si_tcm_size()
7320 if (si_setcore(sih, ARMCR4_CORE_ID, 0)) { in si_has_flops()
7342 uint memsize = 0; in si_socram_srmem_size()
7349 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_srmem_size()
7354 si_core_reset(sih, 0, 0); in si_socram_srmem_size()
7362 for (i = 0; i < nb; i++) { in si_socram_srmem_size()
7371 si_core_disable(sih, 0); in si_socram_srmem_size()
7395 uint32 origidx = 0; in BCMPOSTTRAPFN()
7405 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7421 val = 0; in BCMPOSTTRAPFN()
7445 /* Setting/clearing bit 4 along with bit 8 of 0x1e0 block. the core requests that in BCMPOSTTRAPFN()
7459 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
7468 SPINWAIT(!(si_corereg(sih, 0, offset, 0, 0) & CLKCTL_STS_SECI_CLK_AVAIL), in BCMPOSTTRAPFN()
7471 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0); in BCMPOSTTRAPFN()
7475 ASSERT(0); in BCMPOSTTRAPFN()
7491 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in BCMPOSTTRAPFN()
7493 *origidx = 0; in BCMPOSTTRAPFN()
7526 return 0; in BCMPOSTTRAPFN()
7539 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7548 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7567 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7573 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0) & 0xff; in BCMPOSTTRAPFN()
7577 retval = si_corereg(sih, SI_CC_IDX, offset, 0, 0); in BCMPOSTTRAPFN()
7582 W_REG(sii->osh, &cc->seci_uart_data, (uint32)(val & 0xff)); in BCMPOSTTRAPFN()
7583 retval = 0; in BCMPOSTTRAPFN()
7586 ASSERT(0); in BCMPOSTTRAPFN()
7619 uint32 origidx = 0; in BCMINITFN()
7650 if ((ptr = si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
7688 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFF); /* 4MBaud */ in BCMINITFN()
7695 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFE); in BCMINITFN()
7697 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44); in BCMINITFN()
7700 0xFF, SECI_UART_MCR_BAUD_ADJ_EN); /* 0x81 */ in BCMINITFN()
7706 si_corereg(sih, SI_CC_IDX, offset, 0xff, 0x01); in BCMINITFN()
7715 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x22); in BCMINITFN()
7718 0xFF, SECI_UART_MCR_BAUD_ADJ_EN); /* 0x80 */ in BCMINITFN()
7723 si_corereg(sih, SI_CC_IDX, offset, 0xFF, in BCMINITFN()
7724 (SECI_UART_LCR_RX_EN | SECI_UART_LCR_TXO_EN)); /* 0x28 */ in BCMINITFN()
7727 SECI_UART_MCR_TX_EN, SECI_UART_MCR_TX_EN); /* 0x01 */ in BCMINITFN()
7734 si_corereg(sih, SI_CC_IDX, offset, 0xFFFF, ECI_MACCTRLHI_BITS); in BCMINITFN()
7766 uint bitoff = 0; in BCMINITFN()
7769 uint32 min_res_mask = 0; in BCMINITFN()
7818 uint32 origidx = 0; in BCMINITFN()
7832 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in BCMINITFN()
7840 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskhi, 0x0); in BCMINITFN()
7841 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskmi, 0x0); in BCMINITFN()
7842 W_REG(sii->osh, &cc->eci.lt35.eci_intmasklo, 0x0); in BCMINITFN()
7844 W_REG(sii->osh, &cc->eci.ge35.eci_intmaskhi, 0x0); in BCMINITFN()
7845 W_REG(sii->osh, &cc->eci.ge35.eci_intmasklo, 0x0); in BCMINITFN()
7860 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskhi, 0x0); in BCMINITFN()
7861 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskmi, 0x0); in BCMINITFN()
7862 W_REG(sii->osh, &cc->eci.lt35.eci_eventmasklo, 0x0); in BCMINITFN()
7864 W_REG(sii->osh, &cc->eci.ge35.eci_eventmaskhi, 0x0); in BCMINITFN()
7865 W_REG(sii->osh, &cc->eci.ge35.eci_eventmasklo, 0x0); in BCMINITFN()
7879 return 0; in BCMINITFN()
7898 (1 << 30), 0); in si_eci_notify_bt()
7902 if ((mask & 0xFFFF0000) == ECI48_OUT_MASKMAGIC_HIWORD) { in si_eci_notify_bt()
7904 mask = mask & ~0xFFFF0000; in si_eci_notify_bt()
7927 if ((mask & 0xFFFF0000) == ECI48_OUT_MASKMAGIC_HIWORD) { in si_eci_notify_bt()
7928 mask = mask & ~0xFFFF0000; in si_eci_notify_bt()
7955 if (!(si_corereg(sih, 0, offset, 0, 0) & CLKCTL_STS_SECI_CLK_REQ)) in BCMPOSTTRAPFN()
7971 uint32 origidx = 0; in si_seci_upd()
7985 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in si_seci_upd()
8083 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_btcgpiowar()
8086 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04); in si_btcgpiowar()
8101 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_restore()
8117 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_read()
8135 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_srom4360()
8169 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_srom_clk_set()
8175 ASSERT(0); in si_srom_clk_set()
8203 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_btc_enable_chipcontrol()
8238 if ((w & 0xFFFF) != VENDOR_BROADCOM) in si_deviceremoved()
8263 if ((sih->cccaps & CC_CAP_SROM) == 0) in si_is_sprom_available()
8277 if (CHIPREV(sih->chiprev) == 0) { in si_is_sprom_available()
8279 return 0; in si_is_sprom_available()
8281 return (sih->chipst & CST4369_SPROM_PRESENT) != 0; in si_is_sprom_available()
8285 return (sih->chipst & CST43602_SPROM_PRESENT) != 0; in si_is_sprom_available()
8291 return (sih->chipst & CST4362_SPROM_PRESENT) != 0; in si_is_sprom_available()
8294 return (sih->chipst & CST4378_SPROM_PRESENT) != 0; in si_is_sprom_available()
8297 return (sih->chipst & CST4387_SPROM_PRESENT) != 0; in si_is_sprom_available()
8313 return (sih->chipst & CST4387_SFLASH_PRESENT) != 0; in si_is_sflash_available()
8394 if (CHIPREV(sih->chiprev) == 0) { in si_cis_source()
8426 uint16 fabid = 0; in BCMATTACHFN()
8442 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, fabid), 0, 0); in BCMATTACHFN()
8443 fabid = data & 0xf; in BCMATTACHFN()
8486 if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 && in BCMATTACHFN()
8568 PMU_REG(sih, mac_res_req_timer, ~0x0, PMU43012_MAC_RES_REQ_TIMER); in si_update_masks()
8569 PMU_REG(sih, mac_res_req_mask, ~0x0, PMU43012_MAC_RES_REQ_MASK); in si_update_masks()
8573 ASSERT(0); in si_update_masks()
8587 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x00000053, 0x0); in si_force_islanding()
8590 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000003, 0x000003); in si_force_islanding()
8594 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050); in si_force_islanding()
8598 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x000050, 0x000050); in si_force_islanding()
8604 ASSERT(0); in si_force_islanding()
8624 pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0); in si_pmu_res_req_timer_clr()
8626 return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0); in si_pmu_res_req_timer_clr()
8640 on ? 0 : RCTRL4360_RFLDO_PWR_DOWN); in si_pmu_rfldo()
8644 ASSERT(0); in si_pmu_rfldo()
8658 si_wrapperreg(sih, AI_OOBSELIND74, ~0, 0); in si_pcie_disable_oobselltr()
8660 si_wrapperreg(sih, AI_OOBSELIND30, ~0, 0); in si_pcie_disable_oobselltr()
8670 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0)); in si_pcie_ltr_war()
8728 regs = si_setcore(sih, core_id, 0); in BCMPOSTTRAPFN()
8738 ret_val = 0; in BCMPOSTTRAPFN()
8778 if (!(gciregs = si_setcore(sih, GCI_CORE_ID, 0))) { in si_43012_lp_enable()
8785 GCI_CORECTRL_FORCEREGCLK_MASK, 0); in si_43012_lp_enable()
8795 for (count = 0; count < GPIO_CTRL_REG_COUNT; count++) { in si_43012_lp_enable()
8823 regs = si_setcore(sih, CC_CORE_ID, 0); in si_lowpwr_opt()
8831 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << USBAPP_CLK_BIT), 0); in si_lowpwr_opt()
8835 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << PCIE_CLK_BIT), 0); in si_lowpwr_opt()
8844 PMU43602_CC3_ARMCR4_DBG_CLK, 0); in si_lowpwr_opt()
8850 OFFSETOF(chipcregs_t, jtagctrl), 0, 0) in si_lowpwr_opt()
8856 tapsel?(1 << ARMCR4_DBG_CLK_BIT):0); in si_lowpwr_opt()
8861 (1 << ARMCR4_DBG_CLK_BIT), 0); in si_lowpwr_opt()
8873 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL4, ~0, val); in si_lowpwr_opt()
8895 mask = (0x1 << MEM_CLK_GATE_BIT); in si_lowpwr_opt()
8896 val = (0x1 << MEM_CLK_GATE_BIT); in si_lowpwr_opt()
8928 return 0; in BCMPOSTTRAPFN()
8953 uint32 axi_to = 0; in si_slave_wrapper_add()
8964 ai_update_backplane_timeouts(sih, TRUE, axi_to, 0); in si_slave_wrapper_add()
8967 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE_CORE_ID); in si_slave_wrapper_add()
8968 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE2_CORE_ID); in si_slave_wrapper_add()
8978 /* #define SI_BPIND_1BYTE 0x1 */
8979 /* #define SI_BPIND_2BYTE 0x3 */
8980 /* #define SI_BPIND_4BYTE 0xF */
8986 uint32 status = 0; in BCMPOSTTRAPFN()
8991 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_addrlow), ~0, addr_low); in BCMPOSTTRAPFN()
8992 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_addrhigh), ~0, addr_high); in BCMPOSTTRAPFN()
8996 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), ~0, in BCMPOSTTRAPFN()
9000 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_data), ~0, *data); in BCMPOSTTRAPFN()
9001 si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), ~0, in BCMPOSTTRAPFN()
9008 SPINWAIT(((status = si_ccreg(sih, OFFSETOF(chipcregs_t, bp_indaccess), 0, 0)) & in BCMPOSTTRAPFN()
9013 SI_ERROR(("Action Failed for address 0x%08x:0x%08x \t status: 0x%x\n", in BCMPOSTTRAPFN()
9022 *data = si_ccreg(sih, OFFSETOF(chipcregs_t, bp_data), 0, 0); in BCMPOSTTRAPFN()
9041 data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0); in si_pll_sr_reinit()
9043 if ((data & PMU1_PLLCTL8_OPENLOOP_MASK) == 0) { in si_pll_sr_reinit()
9048 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, PMU1_PLLCTL8_OPENLOOP_MASK, 0); in si_pll_sr_reinit()
9095 data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0); in BCMATTACHFN()
9097 if ((data & PMU1_PLLCTL8_OPENLOOP_MASK) != 0) { in BCMATTACHFN()
9099 PMU1_PLLCTL8_OPENLOOP_MASK, 0); in BCMATTACHFN()
9221 uint8 ccidiv = 0xFF; in BCMPOSTTRAPFN()
9236 return 0; in BCMATTACHFN()
9244 return 0; in BCMPOSTTRAPFN()
9254 return 0; in BCMPOSTTRAPFN()
9265 return 0; in BCMPOSTTRAPFN()
9287 return 0; in si_get_axi_timeout_reg()
9338 return 0; in BCMPOSTTRAPFN()
9389 uint32 r, offset = OFFSETOF(chipcregs_t, powerctl); /* Same 0x1e8 per core */ in BCMPOSTTRAPFN()
9403 r = si_corereg(sih, cidx, offset, 0, 0); in BCMPOSTTRAPFN()
9417 r = si_corereg(sih, cidx, offset, ~0, r); in BCMPOSTTRAPFN()
9432 if (ucode_awake == 0) { in BCMPOSTTRAPFN()
9446 r = si_corereg(sih, cidx, offset, 0, 0); in BCMPOSTTRAPFN()
9449 (mask2 << SRPWR_REQON_SHIFT)) != 0), in BCMPOSTTRAPFN()
9467 return 0; in BCMPOSTTRAPFN()
9501 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_stat()
9519 return 0; in si_srpwr_domain()
9523 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_domain()
9547 return si_srpwr_domain(sih) != 0 ? TRUE : FALSE; in si_srpwr_cap()
9574 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_bt_status()
9590 uint32 address_space = reg & ~0xFFF; in si_raw_reg()
9592 uint32 prev_value = 0; in si_raw_reg()
9593 uint32 cfg_reg = 0; in si_raw_reg()
9596 return 0; in si_raw_reg()
9614 PCI_SEC_BAR0_WIN_OFFSET + (reg & 0xfff)); in si_raw_reg()
9622 PCI_BAR0_WIN2_OFFSET + (reg & 0xfff)); in si_raw_reg()
9632 prev_value = 0; in si_raw_reg()
9686 regs = si_setcore(sih, AXI2AHB_BRIDGE_ID, 0); in BCMATTACHFN()
9690 si_wrapperreg(sih, AI_OOBSELINA30, 0xF00, 0x300); in BCMATTACHFN()
9697 #define RF_SW_CTRL_ELNABYP_ANT_MASK 0x000CC330
9700 #define RF_SW_CTRL_ELNABYP_2G0_MASK 0x00000010
9701 #define RF_SW_CTRL_ELNABYP_5G0_MASK 0x00000020
9702 #define RF_SW_CTRL_ELNABYP_2G1_MASK 0x00004000
9703 #define RF_SW_CTRL_ELNABYP_5G1_MASK 0x00008000
9708 #define RF_SW_CTRL_ELNABYP_2G0_MASK_FB 0x00000100
9709 #define RF_SW_CTRL_ELNABYP_5G0_MASK_FB 0x00000200
9710 #define RF_SW_CTRL_ELNABYP_2G1_MASK_FB 0x00040000
9711 #define RF_SW_CTRL_ELNABYP_5G1_MASK_FB 0x00080000
9714 #define ELNABYP_IOVAR_2G0_VALUE_MASK 0x01
9715 #define ELNABYP_IOVAR_5G0_VALUE_MASK 0x02
9716 #define ELNABYP_IOVAR_2G1_VALUE_MASK 0x04
9717 #define ELNABYP_IOVAR_5G1_VALUE_MASK 0x08
9720 * The values are 'don't care' if the corresponding enables are 0
9722 #define ELNABYP_IOVAR_2G0_ENABLE_MASK 0x10
9723 #define ELNABYP_IOVAR_5G0_ENABLE_MASK 0x20
9724 #define ELNABYP_IOVAR_2G1_ENABLE_MASK 0x40
9725 #define ELNABYP_IOVAR_5G1_ENABLE_MASK 0x80
9727 #define ANTENNA_0_ENABLE 0x00000044
9728 #define ANTENNA_1_ENABLE 0x20000000
9729 #define RFFE_CTRL_START 0x80000000
9730 #define RFFE_CTRL_READ 0x40000000
9731 #define RFFE_CTRL_RFEM_SEL 0x08000000
9732 #define RFFE_MISC_EN_PHYCYCLES 0x00000002
9741 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_15, ALLONES_32, 0x60000000); in si_rffe_rfem_init()
9745 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_23, 0x3 << 29, 0x3 << 29); in si_rffe_rfem_init()
9747 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_clk_ctrl), ALLONES_32, 0x101); in si_rffe_rfem_init()
9750 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlmc), ALLONES_32, 0); in si_rffe_rfem_init()
9751 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlac), ALLONES_32, 0); in si_rffe_rfem_init()
9752 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_wlsc), ALLONES_32, 0); in si_rffe_rfem_init()
9753 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_btmc), ALLONES_32, 0); in si_rffe_rfem_init()
9754 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_change_detect_ovr_btsc), ALLONES_32, 0); in si_rffe_rfem_init()
9756 /* reg address = 0x16, deviceID of rffe dev1 = 0xE, deviceID of dev0 = 0xC, in si_rffe_rfem_init()
9757 * last_mux_ctrl = 0, disable_preemption = 0 (1 for 4387b0), tssi_mask = 3, tssi_en = 0, in si_rffe_rfem_init()
9758 * rffe_disable_line1 = 0, enable rffe_en_phyaccess = 1, in si_rffe_rfem_init()
9759 * disable BRCM proprietary reg0 wr = 0 in si_rffe_rfem_init()
9762 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_misc_ctrl), ALLONES_32, 0x0016EC72); in si_rffe_rfem_init()
9764 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_misc_ctrl), ALLONES_32, 0x0016EC32); in si_rffe_rfem_init()
9767 /* Enable Dual RFFE Master: rffe_single_master = 0 in si_rffe_rfem_init()
9783 uint32 misc_ctrl_set = 0; in si_rffe_set_debug_mode()
9810 uint32 elnabyp_ovr_val = 0; in si_rffe_set_elnabyp_mode()
9811 uint32 elnabyp_ovr_en = 0; in si_rffe_set_elnabyp_mode()
9863 uint32 gci_rffe_ctrl = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0); in BCMPOSTTRAPFN()
9864 uint32 gci_chipcontrol_03 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, 0, 0); in BCMPOSTTRAPFN()
9865 uint32 gci_chipcontrol_02 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, 0, 0); in BCMPOSTTRAPFN()
9867 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, 0); in BCMPOSTTRAPFN()
9873 antenna_1_enable = 0; in BCMPOSTTRAPFN()
9877 antenna_0_enable = 0; in BCMPOSTTRAPFN()
9894 SPINWAIT(si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9896 if (si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9901 *val = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_rfem_data0), 0, 0); in BCMPOSTTRAPFN()
9904 RFFE_CTRL_READ | RFFE_CTRL_RFEM_SEL, 0); in BCMPOSTTRAPFN()
9921 uint32 gci_rffe_ctrl = si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0); in BCMPOSTTRAPFN()
9922 uint32 gci_chipcontrol_03 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_03, 0, 0); in BCMPOSTTRAPFN()
9923 uint32 gci_chipcontrol_02 = si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_02, 0, 0); in BCMPOSTTRAPFN()
9926 si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), ALLONES_32, 0); in BCMPOSTTRAPFN()
9931 antenna_1_enable = 0; in BCMPOSTTRAPFN()
9934 antenna_0_enable = 0; in BCMPOSTTRAPFN()
9957 SPINWAIT(si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
9959 if (si_gci_direct(sih, OFFSETOF(gciregs_t, gci_rffe_ctrl), 0, 0) & in BCMPOSTTRAPFN()
10035 * 0 0000-0FFF 1000-1FFF
10066 uint32 chipst = 0; in si_btc_bt_status_in_reset()
10070 OFFSETOF(chipcregs_t, chipstatus), 0, 0); in si_btc_bt_status_in_reset()
10071 /* 1 =bt in reset 0 = bt out of reset */ in si_btc_bt_status_in_reset()
10075 ASSERT(0); in si_btc_bt_status_in_reset()
10085 BT_IN_PDS_BIT_SHIFT) & 0x1); in si_btc_bt_status_in_pds()
10103 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, PMU_CC0_4387_BT_PU_WAKE_MASK, 0); in si_btc_bt_pds_wakeup_force()
10129 coretype = (si_core_sflags(sih, 0, 0) & SISF_CORE_BITS_SCAN) != 0 ? in BCMATTACHFN()
10150 allowed = ((si_core_sflags(sih, 0, 0) & SISF_CORE_BITS_SCAN) == 0 || in BCMATTACHFN()
10151 (si_gci_chipstatus(sih, GCI_CHIPSTATUS_09) & GCI_CST9_SCAN_DIS) == 0); in BCMATTACHFN()
10160 uint32 board_gpio = 0; in si_configure_pwrthrottle_gpio()
10165 si_gpiocontrol(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_pwrthrottle_gpio()
10166 si_gpioouten(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_pwrthrottle_gpio()
10172 uint32 board_gpio = 0; in si_configure_onbody_gpio()
10177 si_gpiocontrol(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_onbody_gpio()
10178 si_gpioouten(sih, board_gpio, 0, GPIO_DRV_PRIORITY); in si_configure_onbody_gpio()
10187 int val = on ? 0 : 1; in si_jtag_udr_pwrsw_main_toggle()
10207 uint32 sssr_dmp_src = 0; in BCMATTACHFN()
10208 *sssr_size = 0; in BCMATTACHFN()
10212 if (unit == 0) { in BCMATTACHFN()
10236 hib_time = LHL_REG(sih, lhl_hibtim_adr, 0, 0); in si_cur_hib_time()
10243 if (hib_time != LHL_REG(sih, lhl_hibtim_adr, 0, 0)) { in si_cur_hib_time()
10244 hib_time = LHL_REG(sih, lhl_hibtim_adr, 0, 0); in si_cur_hib_time()