42 static uint _sb_coreidx(const si_info_t *sii, uint32 sba);
43 static uint _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus, uint32 sbba,
45 static uint32 _sb_coresba(const si_info_t *sii);
46 static volatile void *_sb_setcoreidx(const si_info_t *sii, uint coreidx);
47 #define	SET_SBREG(sii, r, mask, val)	\  argument
48 		W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
58 #define	R_SBREG(sii, sbr)	sb_read_sbreg((sii), (sbr))  argument
59 #define	W_SBREG(sii, sbr, v)	sb_write_sbreg((sii), (sbr), (v))  argument
60 #define	AND_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))  argument
61 #define	OR_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))  argument
64 sb_read_sbreg(const si_info_t *sii, volatile uint32 *sbr)  in sb_read_sbreg()  argument
66 	return R_REG(sii->osh, sbr);  in sb_read_sbreg()
70 sb_write_sbreg(const si_info_t *sii, volatile uint32 *sbr, uint32 v)  in sb_write_sbreg()  argument
72 	W_REG(sii->osh, sbr, v);  in sb_write_sbreg()
78 	const si_info_t *sii = SI_INFO(sih);  in sb_coreid()  local
79 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_coreid()
81 	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);  in sb_coreid()
87 	const si_info_t *sii = SI_INFO(sih);  in sb_intflag()  local
93 	INTR_OFF(sii, &intr_val);  in sb_intflag()
98 	intflag = R_SBREG(sii, &sb->sbflagst);  in sb_intflag()
100 	INTR_RESTORE(sii, &intr_val);  in sb_intflag()
108 	const si_info_t *sii = SI_INFO(sih);  in sb_flag()  local
109 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_flag()
111 	return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;  in sb_flag()
117 	const si_info_t *sii = SI_INFO(sih);  in sb_setint()  local
118 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_setint()
125 	W_SBREG(sii, &sb->sbintvec, vec);  in sb_setint()
130 BCMATTACHFN(_sb_coreidx)(const si_info_t *sii, uint32 sba)  in BCMATTACHFN()
133 	const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;  in BCMATTACHFN()
135 	for (i = 0; i < sii->numcores; i ++)  in BCMATTACHFN()
143 BCMATTACHFN(_sb_coresba)(const si_info_t *sii)  in BCMATTACHFN()
147 	switch (BUSTYPE(sii->pub.bustype)) {  in BCMATTACHFN()
149 		sbconfig_t *sb = REGS2SB(sii->curmap);  in BCMATTACHFN()
150 		sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));  in BCMATTACHFN()
155 		sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));  in BCMATTACHFN()
161 		sbaddr = (uint32)(uintptr)sii->curmap;  in BCMATTACHFN()
176 	const si_info_t *sii;  in sb_corevendor()  local
179 	sii = SI_INFO(sih);  in sb_corevendor()
180 	sb = REGS2SB(sii->curmap);  in sb_corevendor()
182 	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);  in sb_corevendor()
188 	const si_info_t *sii;  in sb_corerev()  local
192 	sii = SI_INFO(sih);  in sb_corerev()
193 	sb = REGS2SB(sii->curmap);  in sb_corerev()
194 	sbidh = R_SBREG(sii, &sb->sbidhigh);  in sb_corerev()
203 	const si_info_t *sii = SI_INFO(sih);  in sb_core_cflags_wo()  local
204 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_core_cflags_wo()
210 	w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |  in sb_core_cflags_wo()
212 	W_SBREG(sii, &sb->sbtmstatelow, w);  in sb_core_cflags_wo()
219 	const si_info_t *sii = SI_INFO(sih);  in sb_core_cflags()  local
220 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_core_cflags()
227 		w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |  in sb_core_cflags()
229 		W_SBREG(sii, &sb->sbtmstatelow, w);  in sb_core_cflags()
235 	return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);  in sb_core_cflags()
242 	const si_info_t *sii = SI_INFO(sih);  in sb_core_sflags()  local
243 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_core_sflags()
251 		w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |  in sb_core_sflags()
253 		W_SBREG(sii, &sb->sbtmstatehigh, w);  in sb_core_sflags()
257 	return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);  in sb_core_sflags()
263 	const si_info_t *sii = SI_INFO(sih);  in sb_iscoreup()  local
264 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_iscoreup()
266 	return ((R_SBREG(sii, &sb->sbtmstatelow) &  in sb_iscoreup()
288 	si_info_t *sii = SI_INFO(sih);  in sb_corereg()  local
289 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in sb_corereg()
291 	ASSERT(GOODIDX(coreidx, sii->numcores));  in sb_corereg()
298 	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {  in sb_corereg()
308 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {  in sb_corereg()
311 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in sb_corereg()
315 			r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
317 		} else if (sii->pub.buscoreidx == coreidx) {  in sb_corereg()
322 			if (SI_FAST(sii))  in sb_corereg()
323 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
326 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
334 		INTR_OFF(sii, &intr_val);  in sb_corereg()
337 		origidx = si_coreidx(&sii->pub);  in sb_corereg()
340 		r = (volatile uint32*) ((volatile uchar*)sb_setcoreidx(&sii->pub, coreidx) +  in sb_corereg()
348 			w = (R_SBREG(sii, r) & ~mask) | val;  in sb_corereg()
349 			W_SBREG(sii, r, w);  in sb_corereg()
351 			w = (R_REG(sii->osh, r) & ~mask) | val;  in sb_corereg()
352 			W_REG(sii->osh, r, w);  in sb_corereg()
358 		w = R_SBREG(sii, r);  in sb_corereg()
360 		w = R_REG(sii->osh, r);  in sb_corereg()
366 			sb_setcoreidx(&sii->pub, origidx);  in sb_corereg()
368 		INTR_RESTORE(sii, &intr_val);  in sb_corereg()
388 	const si_info_t *sii = SI_INFO(sih);  in sb_corereg_addr()  local
389 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in sb_corereg_addr()
391 	ASSERT(GOODIDX(coreidx, sii->numcores));  in sb_corereg_addr()
397 	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {  in sb_corereg_addr()
407 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {  in sb_corereg_addr()
410 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in sb_corereg_addr()
414 			r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
416 		} else if (sii->pub.buscoreidx == coreidx) {  in sb_corereg_addr()
421 			if (SI_FAST(sii))  in sb_corereg_addr()
422 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
425 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
447 BCMATTACHFN(_sb_scan)(si_info_t *sii, uint32 sba, volatile void *regs, uint bus,  in BCMATTACHFN()
453 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in BCMATTACHFN()
465 	for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {  in BCMATTACHFN()
469 		if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (cores_info->coresba[next] == sba)) {  in BCMATTACHFN()
475 		sii->curmap = _sb_setcoreidx(sii, next);  in BCMATTACHFN()
476 		sii->curidx = next;  in BCMATTACHFN()
478 		cores_info->coreid[next] = sb_coreid(&sii->pub);  in BCMATTACHFN()
483 			chipcregs_t *cc = (chipcregs_t *)sii->curmap;  in BCMATTACHFN()
487 			numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;  in BCMATTACHFN()
489 				sii->pub.issim ? "QT" : ""));  in BCMATTACHFN()
493 			sbconfig_t *sb = REGS2SB(sii->curmap);  in BCMATTACHFN()
494 			uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);  in BCMATTACHFN()
497 			sii->numcores = next + 1;  in BCMATTACHFN()
502 			if (_sb_coreidx(sii, nsbba) != BADIDX)  in BCMATTACHFN()
505 			nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;  in BCMATTACHFN()
506 			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc, devid);  in BCMATTACHFN()
515 	sii->numcores = i + ncc;  in BCMATTACHFN()
516 	return sii->numcores;  in BCMATTACHFN()
525 	si_info_t *sii = SI_INFO(sih);  in BCMATTACHFN()  local
528 	sb = REGS2SB(sii->curmap);  in BCMATTACHFN()
530 	sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;  in BCMATTACHFN()
535 	origsba = _sb_coresba(sii);  in BCMATTACHFN()
538 	sii->numcores = _sb_scan(sii, origsba, regs, 0, si_enum_base(devid), 1, devid);  in BCMATTACHFN()
549 	si_info_t *sii = SI_INFO(sih);  in sb_setcoreidx()  local
551 	if (coreidx >= sii->numcores)  in sb_setcoreidx()
558 	ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));  in sb_setcoreidx()
560 	sii->curmap = _sb_setcoreidx(sii, coreidx);  in sb_setcoreidx()
561 	sii->curidx = coreidx;  in sb_setcoreidx()
563 	return (sii->curmap);  in sb_setcoreidx()
570 _sb_setcoreidx(const si_info_t *sii, uint coreidx)  in _sb_setcoreidx()  argument
572 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in _sb_setcoreidx()
576 	switch (BUSTYPE(sii->pub.bustype)) {  in _sb_setcoreidx()
588 		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);  in _sb_setcoreidx()
589 		regs = sii->curmap;  in _sb_setcoreidx()
615 sb_admatch(const si_info_t *sii, uint asidx)  in sb_admatch()  argument
620 	sb = REGS2SB(sii->curmap);  in sb_admatch()
651 	const si_info_t *sii = SI_INFO(sih);  in sb_numaddrspaces()  local
652 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_numaddrspaces()
655 	return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;  in sb_numaddrspaces()
662 	const si_info_t *sii = SI_INFO(sih);  in sb_addrspace()  local
664 	return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));  in sb_addrspace()
671 	const si_info_t *sii = SI_INFO(sih);  in sb_addrspacesize()  local
673 	return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));  in sb_addrspacesize()
680 sb_serr_clear(si_info_t *sii)  in sb_serr_clear()  argument
688 	INTR_OFF(sii, &intr_val);  in sb_serr_clear()
689 	origidx = si_coreidx(&sii->pub);  in sb_serr_clear()
691 	for (i = 0; i < sii->numcores; i++) {  in sb_serr_clear()
692 		corereg = sb_setcoreidx(&sii->pub, i);  in sb_serr_clear()
695 			if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) {  in sb_serr_clear()
696 				AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR);  in sb_serr_clear()
698 				          sb_coreid(&sii->pub)));  in sb_serr_clear()
703 	sb_setcoreidx(&sii->pub, origidx);  in sb_serr_clear()
704 	INTR_RESTORE(sii, &intr_val);  in sb_serr_clear()
714 	si_info_t *sii = SI_INFO(sih);  in sb_taclear()  local
719 	BCM_REFERENCE(sii);  in sb_taclear()
721 	if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {  in sb_taclear()
725 		stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32));  in sb_taclear()
734 			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32), stcmd);  in sb_taclear()
738 		stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32));  in sb_taclear()
747 			sb_serr_clear(sii);  in sb_taclear()
748 			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32), stcmd);  in sb_taclear()
752 		imstate = sb_corereg(sih, sii->pub.buscoreidx,  in sb_taclear()
755 			sb_corereg(sih, sii->pub.buscoreidx,  in sb_taclear()
772 			if (sii->pub.socirev == SONICS_2_2)  in sb_taclear()
776 				imerrlog = sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, 0, 0);  in sb_taclear()
778 					imerrloga = sb_corereg(sih, sii->pub.buscoreidx,  in sb_taclear()
782 					sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, ~0, 0);  in sb_taclear()
790 	else if ((BUSTYPE(sii->pub.bustype) == SDIO_BUS) ||  in sb_taclear()
791 	         (BUSTYPE(sii->pub.bustype) == SPI_BUS)) {  in sb_taclear()
798 		INTR_OFF(sii, &intr_val);  in sb_taclear()
805 			imstate = R_SBREG(sii, &sb->sbimstate);  in sb_taclear()
807 				AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));  in sb_taclear()
811 			tmstate = R_SBREG(sii, &sb->sbtmstatehigh);  in sb_taclear()
813 				sb_serr_clear(sii);  in sb_taclear()
815 				OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK);  in sb_taclear()
816 				AND_SBREG(sii, &sb->sbtmstatelow, ~SBTML_INT_ACK);  in sb_taclear()
821 		INTR_RESTORE(sii, &intr_val);  in sb_taclear()
839 	const si_info_t *sii = SI_INFO(sih);  in sb_commit()  local
843 	origidx = sii->curidx;  in sb_commit()
844 	ASSERT(GOODIDX(origidx, sii->numcores));  in sb_commit()
846 	INTR_OFF(sii, &intr_val);  in sb_commit()
849 	if (sii->pub.ccrev != NOREV) {  in sb_commit()
854 		W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);  in sb_commit()
855 		W_REG(sii->osh, &ccregs->broadcastdata, 0x0);  in sb_commit()
857 	} else if (PCI(sii)) {  in sb_commit()
862 		W_REG(sii->osh, &pciregs->bcastaddr, SB_COMMIT);  in sb_commit()
863 		W_REG(sii->osh, &pciregs->bcastdata, 0x0);  in sb_commit()
870 	INTR_RESTORE(sii, &intr_val);  in sb_commit()
876 	const si_info_t *sii = SI_INFO(sih);  in sb_core_disable()  local
880 	ASSERT(GOODREGS(sii->curmap));  in sb_core_disable()
881 	sb = REGS2SB(sii->curmap);  in sb_core_disable()
884 	if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)  in sb_core_disable()
888 	if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)  in sb_core_disable()
892 	OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);  in sb_core_disable()
893 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_disable()
896 	SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);  in sb_core_disable()
897 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)  in sb_core_disable()
905 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {  in sb_core_disable()
906 		OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);  in sb_core_disable()
907 		dummy = R_SBREG(sii, &sb->sbimstate);  in sb_core_disable()
910 		SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);  in sb_core_disable()
914 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_disable()
917 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_disable()
922 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)  in sb_core_disable()
923 		AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);  in sb_core_disable()
927 	W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));  in sb_core_disable()
939 	const si_info_t *sii = SI_INFO(sih);  in sb_core_reset()  local
943 	ASSERT(GOODREGS(sii->curmap));  in sb_core_reset()
944 	sb = REGS2SB(sii->curmap);  in sb_core_reset()
956 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_reset()
959 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
964 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {  in sb_core_reset()
965 		W_SBREG(sii, &sb->sbtmstatehigh, 0);  in sb_core_reset()
967 	if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {  in sb_core_reset()
968 		AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));  in sb_core_reset()
972 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_reset()
974 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
979 	W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));  in sb_core_reset()
980 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
1041 	const si_info_t *sii = SI_INFO(sih);  in sb_dumpregs()  local
1042 	const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;  in sb_dumpregs()
1044 	origidx = sii->curidx;  in sb_dumpregs()
1046 	INTR_OFF(sii, &intr_val);  in sb_dumpregs()
1048 	for (i = 0; i < sii->numcores; i++) {  in sb_dumpregs()
1053 		if (sii->pub.socirev > SONICS_2_2)  in sb_dumpregs()
1055 			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),  in sb_dumpregs()
1056 			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));  in sb_dumpregs()
1060 		            R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),  in sb_dumpregs()
1061 		            R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),  in sb_dumpregs()
1062 		            R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));  in sb_dumpregs()
1066 	INTR_RESTORE(sii, &intr_val);  in sb_dumpregs()
1074 	const si_info_t *sii = SI_INFO(sih);  in sb_view()  local
1075 	sbconfig_t *sb = REGS2SB(sii->curmap);  in sb_view()
1077 	SI_ERROR(("\nCore ID: 0x%x\n", sb_coreid(&sii->pub)));  in sb_view()
1079 	if (sii->pub.socirev > SONICS_2_2)  in sb_view()
1081 		         sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),  in sb_view()
1082 		         sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0)));  in sb_view()
1086 	          R_SBREG(sii, &sb->sbtmerrloga), R_SBREG(sii, &sb->sbtmerrlog)));  in sb_view()
1088 	          R_SBREG(sii, &sb->sbimstate),  in sb_view()
1089 	          R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh)));  in sb_view()
1091 	          R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbtmconfiglow),  in sb_view()
1092 	          R_SBREG(sii, &sb->sbtmconfighigh), R_SBREG(sii, &sb->sbidhigh)));  in sb_view()
1097 		          R_SBREG(sii, &sb->sbipsflag), R_SBREG(sii, &sb->sbtpsflag)));  in sb_view()
1099 		          R_SBREG(sii, &sb->sbadmatch3), R_SBREG(sii, &sb->sbadmatch2),  in sb_view()
1100 		          R_SBREG(sii, &sb->sbadmatch1), R_SBREG(sii, &sb->sbadmatch0)));  in sb_view()
1102 		          R_SBREG(sii, &sb->sbintvec), R_SBREG(sii, &sb->sbbwa0),  in sb_view()
1103 		          R_SBREG(sii, &sb->sbimconfighigh)));  in sb_view()
1105 		          R_SBREG(sii, &sb->sbbconfig), R_SBREG(sii, &sb->sbbstate)));  in sb_view()
1107 		          R_SBREG(sii, &sb->sbactcnfg), R_SBREG(sii, &sb->sbflagst),  in sb_view()
1108 		          R_SBREG(sii, &sb->sbidlow)));  in sb_view()