bcmdhd/include/sdioh.h

118 #define CAP_TO_CLKFREQ_M	BITFIELD_MASK(6)
120 #define CAP_TO_CLKUNIT_M	BITFIELD_MASK(1)
125 #define CAP_BASECLK_M		BITFIELD_MASK(8)
127 #define CAP_MAXBLOCK_M		BITFIELD_MASK(2)
129 #define CAP_ADMA2_M		BITFIELD_MASK(1)
131 #define CAP_ADMA1_M		BITFIELD_MASK(1)
133 #define CAP_HIGHSPEED_M		BITFIELD_MASK(1)
135 #define CAP_DMA_M		BITFIELD_MASK(1)
137 #define CAP_SUSPEND_M		BITFIELD_MASK(1)
139 #define CAP_VOLT_3_3_M		BITFIELD_MASK(1)
141 #define CAP_VOLT_3_0_M		BITFIELD_MASK(1)
143 #define CAP_VOLT_1_8_M		BITFIELD_MASK(1)
145 #define CAP_64BIT_HOST_M	BITFIELD_MASK(1)
150 #define CAP_ASYNCINT_SUP_M	BITFIELD_MASK(1)
153 #define CAP_SLOTTYPE_M		BITFIELD_MASK(2)
161 #define CAP3_SDR50_SUP_M		BITFIELD_MASK(1)
164 #define CAP3_SDR104_SUP_M	BITFIELD_MASK(1)
167 #define CAP3_DDR50_SUP_M	BITFIELD_MASK(1)
171 #define CAP3_30CLKCAP_M		BITFIELD_MASK(3)
174 #define CAP3_DRIVTYPE_A_M	BITFIELD_MASK(1)
177 #define CAP3_DRIVTYPE_C_M	BITFIELD_MASK(1)
180 #define CAP3_DRIVTYPE_D_M	BITFIELD_MASK(1)
183 #define CAP3_RETUNING_TC_M	BITFIELD_MASK(4)
186 #define CAP3_TUNING_SDR50_M	BITFIELD_MASK(1)
189 #define CAP3_RETUNING_MODES_M	BITFIELD_MASK(2)
196 #define CAP3_CLK_MULT_M		BITFIELD_MASK(8)
199 #define PRESET_DRIVR_SELECT_M	BITFIELD_MASK(2)
202 #define PRESET_CLK_DIV_M	BITFIELD_MASK(10)
206 #define CAP_CURR_3_3_M		BITFIELD_MASK(8)
208 #define CAP_CURR_3_0_M		BITFIELD_MASK(8)
210 #define CAP_CURR_1_8_M		BITFIELD_MASK(8)
216 #define BLKSZ_BLKSZ_M		BITFIELD_MASK(12)
218 #define BLKSZ_BNDRY_M		BITFIELD_MASK(3)
225 #define XFER_DMA_ENABLE_M	BITFIELD_MASK(1)
227 #define XFER_BLK_COUNT_EN_M	BITFIELD_MASK(1)
229 #define XFER_CMD_12_EN_M	BITFIELD_MASK(1)
231 #define XFER_DATA_DIRECTION_M	BITFIELD_MASK(1)
233 #define XFER_MULTI_BLOCK_M	BITFIELD_MASK(1)
248 #define CMD_RESP_TYPE_M		BITFIELD_MASK(2)	/* Bits [0-1]	- Response type */
250 #define CMD_CRC_EN_M		BITFIELD_MASK(1)	/* Bit 3	- CRC enable */
252 #define CMD_INDEX_EN_M		BITFIELD_MASK(1)	/* Bit 4	- Enable index checking */
254 #define CMD_DATA_EN_M		BITFIELD_MASK(1)	/* Bit 5	- Using DAT line */
256 #define CMD_TYPE_M		BITFIELD_MASK(2)	/* Bit [6-7]	- Normal, abort, resume, etc
259 #define CMD_INDEX_M		BITFIELD_MASK(6)	/* Bits [8-13]	- Command number */
265 #define PRES_CMD_INHIBIT_M	BITFIELD_MASK(1)	/* Bit 0	May use CMD */
267 #define PRES_DAT_INHIBIT_M	BITFIELD_MASK(1)	/* Bit 1	May use DAT */
269 #define PRES_DAT_BUSY_M		BITFIELD_MASK(1)	/* Bit 2	DAT is busy */
271 #define PRES_PRESENT_RSVD_M	BITFIELD_MASK(5)	/* Bit [3-7]	rsvd */
273 #define PRES_WRITE_ACTIVE_M	BITFIELD_MASK(1)	/* Bit 8	Write is active */
275 #define PRES_READ_ACTIVE_M	BITFIELD_MASK(1)	/* Bit 9	Read is active */
277 #define PRES_WRITE_DATA_RDY_M	BITFIELD_MASK(1)	/* Bit 10	Write buf is avail */
279 #define PRES_READ_DATA_RDY_M	BITFIELD_MASK(1)	/* Bit 11	Read buf data avail */
281 #define PRES_CARD_PRESENT_M	BITFIELD_MASK(1)	/* Bit 16	Card present - debounced */
283 #define PRES_CARD_STABLE_M	BITFIELD_MASK(1)	/* Bit 17	Debugging */
285 #define PRES_CARD_PRESENT_RAW_M	BITFIELD_MASK(1)	/* Bit 18	Not debounced */
287 #define PRES_WRITE_ENABLED_M	BITFIELD_MASK(1)	/* Bit 19	Write protected? */
289 #define PRES_DAT_SIGNAL_M	BITFIELD_MASK(4)	/* Bit [20-23]	Debugging */
291 #define PRES_CMD_SIGNAL_M	BITFIELD_MASK(1)	/* Bit 24	Debugging */
295 #define HOST_LED_M		BITFIELD_MASK(1)	/* Bit 0	LED On/Off */
297 #define HOST_DATA_WIDTH_M	BITFIELD_MASK(1)	/* Bit 1	4 bit enable */
299 #define HOST_HI_SPEED_EN_M	BITFIELD_MASK(1)	/* Bit 2	High speed vs low speed */
301 #define HOST_DMA_SEL_M		BITFIELD_MASK(2)	/* Bit 4:3	DMA Select */
305 #define HOSTCtrl2_PRESVAL_EN_M	BITFIELD_MASK(1)	/* 1 bit */
308 #define HOSTCtrl2_ASYINT_EN_M	BITFIELD_MASK(1)	/* 1 bit */
311 #define HOSTCtrl2_SAMPCLK_SEL_M	BITFIELD_MASK(1)	/* 1 bit */
314 #define HOSTCtrl2_EXEC_TUNING_M	BITFIELD_MASK(1)	/* 1 bit */
317 #define HOSTCtrl2_DRIVSTRENGTH_SEL_M	BITFIELD_MASK(2)	/* 2 bit */
320 #define HOSTCtrl2_1_8SIG_EN_M	BITFIELD_MASK(1)	/* 1 bit */
323 #define HOSTCtrl2_UHSMODE_SEL_M	BITFIELD_MASK(3)	/* 3 bit */
335 #define PWR_BUS_EN_M		BITFIELD_MASK(1)	/* Bit 0	Power the bus */
337 #define PWR_VOLTS_M		BITFIELD_MASK(3)	/* Bit [1-3]	Voltage Select */
341 #define SW_RESET_ALL_M		BITFIELD_MASK(1)	/* Bit 0	Reset All */
343 #define SW_RESET_CMD_M		BITFIELD_MASK(1)	/* Bit 1	CMD Line Reset */
345 #define SW_RESET_DAT_M		BITFIELD_MASK(1)	/* Bit 2	DAT Line Reset */
350 #define INTSTAT_CMD_COMPLETE_M		BITFIELD_MASK(1)	/* Bit 0 */
352 #define INTSTAT_XFER_COMPLETE_M		BITFIELD_MASK(1)
354 #define INTSTAT_BLOCK_GAP_EVENT_M	BITFIELD_MASK(1)
356 #define INTSTAT_DMA_INT_M		BITFIELD_MASK(1)
358 #define INTSTAT_BUF_WRITE_READY_M	BITFIELD_MASK(1)
360 #define INTSTAT_BUF_READ_READY_M	BITFIELD_MASK(1)
362 #define INTSTAT_CARD_INSERTION_M	BITFIELD_MASK(1)
364 #define INTSTAT_CARD_REMOVAL_M		BITFIELD_MASK(1)
366 #define INTSTAT_CARD_INT_M		BITFIELD_MASK(1)
368 #define INTSTAT_RETUNING_INT_M		BITFIELD_MASK(1)	/* Bit 12 */
370 #define INTSTAT_ERROR_INT_M		BITFIELD_MASK(1)	/* Bit 15 */
375 #define ERRINT_CMD_TIMEOUT_M		BITFIELD_MASK(1)
377 #define ERRINT_CMD_CRC_M		BITFIELD_MASK(1)
379 #define ERRINT_CMD_ENDBIT_M		BITFIELD_MASK(1)
381 #define ERRINT_CMD_INDEX_M		BITFIELD_MASK(1)
383 #define ERRINT_DATA_TIMEOUT_M		BITFIELD_MASK(1)
385 #define ERRINT_DATA_CRC_M		BITFIELD_MASK(1)
387 #define ERRINT_DATA_ENDBIT_M		BITFIELD_MASK(1)
389 #define ERRINT_CURRENT_LIMIT_M		BITFIELD_MASK(1)
391 #define ERRINT_AUTO_CMD12_M		BITFIELD_MASK(1)
393 #define ERRINT_VENDOR_M			BITFIELD_MASK(4)
395 #define ERRINT_ADMA_M			BITFIELD_MASK(1)