Lines Matching full:receive
30 * basic DMA register set is per channel(transmit or receive)
149 /* receive channel control */
150 #define RC_RE ((uint32)1 << 0) /**< receive enable */
151 #define RC_RO_MASK 0xfe /**< receive frame offset */
153 #define RC_FM ((uint32)1 << 8) /**< direct fifo receive (pio) mode */
167 /* receive descriptor table pointer */
170 /* receive channel status */
172 #define RS_RS_MASK 0xf000 /**< receive state */
178 #define RS_RE_MASK 0xf0000 /**< receive errors */
194 #define FA_SEL_RDD 0x40000 /**< receive dma data */
195 #define FA_SEL_RDP 0x50000 /**< receive dma pointers */
198 #define FA_SEL_RFD 0xc0000 /**< receive fifo data */
199 #define FA_SEL_RFP 0xd0000 /**< receive fifo pointers */
200 #define FA_SEL_RSD 0xe0000 /**< receive frame status data */
201 #define FA_SEL_RSP 0xf0000 /**< receive frame status pointers */
332 /* receive channel control */
333 #define D64_RC_RE 0x00000001 /**< receive enable */
334 #define D64_RC_RO_MASK 0x000000fe /**< receive frame offset */
336 #define D64_RC_FM 0x00000100 /**< direct fifo receive (pio) mode */
355 #define D64_RC_ROEXT_MASK 0x08000000 /**< receive frame offset extension bit */
360 /* receive control values */
387 #define DMA_CTRL_ROEXT (1u << 11u) /* receive frame offset extension support */
400 /* receive descriptor table pointer */
403 /* receive channel status */
405 #define D64_RS0_RS_MASK 0xf0000000 /**< receive state */
414 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
429 #define D64_FA_SEL_RDD 0x40000 /**< receive dma data */
430 #define D64_FA_SEL_RDP 0x50000 /**< receive dma pointers */
433 #define D64_FA_SEL_RFD 0xc0000 /**< receive fifo data */
434 #define D64_FA_SEL_RFP 0xd0000 /**< receive fifo pointers */
435 #define D64_FA_SEL_RSD 0xe0000 /**< receive frame status data */
436 #define D64_FA_SEL_RSP 0xf0000 /**< receive frame status pointers */
441 /**< bzero operation for receive channels or a compare-to-zero operation for transmit engines */
475 /** receive frame status */