bcmdhd/include/sbhndarm.h

33 #define	ARM7_CORECTL		0
36 #define	ACC_FORCED_RST		0x1
37 #define	ACC_SERRINT		0x2
38 #define	ACC_WFICLKSTOP		0x4
46 #define ACC_FORCECLOCKRATIO		(0x1u << 8)
48 #define ACC_CLOCKRATIO_MASK		(0xFu << ACC_CLOCKRATIO_SHIFT)
50 #define ACC_CLOCKRATIO_1_TO_1		(0u)
56 #define ACC_FASTCLOCKCHANNEL_MASK	(0x3u << ACC_FASTCLOCKCHANNEL_SHIFT)
58 #define ACC_NUM_FASTCLOCKS_MASK		(0x3u << ACC_NUM_FASTCLOCKS_SHIFT)
61 #define ACC_NOTSLEEPINGCLKREQ_MASK	(0x3u << ACC_NOT_SLEEPING_CLKREQ_SHIFT)
62 #define ACC_NOTSLEEPING_ALP		(0u)
71 #define ACC_CLOCKRATIO_MASK	(0xFu << ACC_CLOCKRATIO_SHIFT)
78 #define ACC_CLOCKRATIO_1_TO_1	(0u)
83 #define ACC_CLOCKMODE_SAME	(0)	/**< BP and CPU clock are the same */
91 #define ACC_MPU_MASK		(0x1u << ACC_MPU_SHIFT)
93 #define ACC_MPU_REGION_CNT_MASK		0x7u
97 #define ACC_MPU_SECURE_MASK	(0x1u << ACC_MPU_SECURE_SHIFT)
99 #define ACC_MPU_READ_MASK	(0x1u << ACC_MPU_READ_SHIFT)
101 #define ACC_MPU_WRITE_MASK	(0x1u << ACC_MPU_WRITE_SHIFT)
103 #define ACC_MPU_VALID_MASK	(0x1u << ACC_MPU_VALID_SHIFT)
106 #define SBRESETLOG		0x1
107 #define SERRORLOG		0x2
110 #define	SICF_REMAP_MSK		0x001c
111 #define	SICF_REMAP_NONE		0
112 #define	SICF_REMAP_ROM		0x0004
113 #define	SIFC_REMAP_FLASH	0x0008
123 #define ARMCM3_CYCLECNT		0x90		/**< Cortex-M3 core registers offsets */
124 #define ARMCM3_INTTIMER		0x94
125 #define ARMCM3_INTMASK		0x98
126 #define ARMCM3_INTSTATUS	0x9c
130 #define ARMCM3_SHARED_INT	0		/**< Interrupt shared by multiple cores */
133 #define ARMCM3_INTMASK_TIMER	0x1
134 #define ARMCM3_INTMASK_SYSRESET	0x4
135 #define ARMCM3_INTMASK_LOCKUP	0x8
140 #define ARMCM3_OVL_VALID_SHIFT		0
143 #define ARMCM3_OVL_SZ_MASK		0x0000000e
144 #define ARMCM3_OVL_SZ_512B		0	/* 512B */
153 #define ARMCM3_OVL_ADDR_MASK		0x003FFE00
161 #define SI_ARM_SRAM2		0x0	/**< In the cr4 the RAM is just not available
166 #define ARMCR4_CORECTL		0
170 #define ARMCR4_FIQRSTATUS	0x10
171 #define ARMCR4_FIQMASK		0x14
172 #define ARMCR4_IRQMASK		0x18
174 #define ARMCR4_INTSTATUS	0x20
175 #define ARMCR4_INTMASK		0x24
176 #define ARMCR4_CYCLECNT		0x28
177 #define ARMCR4_INTTIMER		0x2c
179 #define ARMCR4_GPIOSEL		0x30
180 #define ARMCR4_GPIOEN		0x34
182 #define ARMCR4_BANKIDX		0x40
183 #define ARMCR4_BANKINFO		0x44
184 #define ARMCR4_BANKSTBY		0x48
185 #define ARMCR4_BANKPDA		0x4c
187 #define ARMCR4_TCAMPATCHCTRL		0x68
188 #define ARMCR4_TCAMPATCHTBLBASEADDR	0x6C
189 #define ARMCR4_TCAMCMDREG		0x70
190 #define ARMCR4_TCAMDATAREG		0x74
191 #define ARMCR4_TCAMBANKXMASKREG		0x78
193 #define	ARMCR4_ROMNB_MASK	0xf00
195 #define	ARMCR4_MSB_ROMNB_MASK	0x1E00000
198 #define	ARMCR4_TCBBNB_MASK	0xf0
200 #define	ARMCR4_TCBANB_MASK	0xf
201 #define	ARMCR4_TCBANB_SHIFT	0
203 #define	ARMCR4_MT_MASK		0x300
205 #define	ARMCR4_MT_ROM		0x100
206 #define	ARMCR4_MT_RAM		0
208 #define	ARMCR4_BSZ_MASK		0x7f
209 #define	ARMCR4_BUNITSZ_MASK	0x200
213 #define	ARMCR4_STBY_SUPPORTED		0x400
214 #define	ARMCR4_STBY_TIMER_PRESENT	0x800
216 #define ARMCR4_TIMER_VAL_MASK		0xfffff
223 #define ARMCR4_TCAM_PATCHCNT_MASK	0xfu
229 #define ARMCR4_TCAM_ADDR_MASK	0xffff
230 #define ARMCR4_TCAM_NONE	(0 << ARMCR4_TCAM_OPCODE_SHIFT)
236 #define ARMCR4_DATA_MASK	(~0x7)
237 #define ARMCR4_DATA_VALID	(1u << 0)
240 #define ARMCR4_INTMASK_TIMER		(0x1)
241 #define ARMCR4_INTMASK_CLOCKSTABLE	(0x20000000)
249 #define ROM_STBY_TIMER_4378	0xb0
250 #define RAM_STBY_TIMER_4378	0x64
252 #define ROM_STBY_TIMER_4387	0x10
253 #define RAM_STBY_TIMER_4387	0x100
258 #define	ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_SHIFT	(0u)
259 #define ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_MASK	(0xF << \
262 #define	ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_MASK	(0x3F << \
265 #define	ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_MASK	(0x1 << \
302 	uint32	corecontrol;	/* 0x0 */
303 	uint32	corestatus;	/* 0x4 */
305 	uint32	biststatus;	/* 0xc */
306 	uint32	nmiisrst;	/* 0x10 */
307 	uint32	nmimask;	/* 0x14 */
308 	uint32	isrmask;	/* 0x18 */
310 	uint32	resetlog;	/* 0x20 */
311 	uint32	gpioselect;	/* 0x24 */
312 	uint32	gpioenable;	/* 0x28 */
314 	uint32	bpaddrlo;	/* 0x30 */
315 	uint32	bpaddrhi;	/* 0x34 */
316 	uint32	bpdata;		/* 0x38 */
317 	uint32	bpindaccess;	/* 0x3c */
318 	uint32	ovlidx;		/* 0x40 */
319 	uint32	ovlmatch;	/* 0x44 */
320 	uint32	ovladdr;	/* 0x48 */
322 	uint32	bwalloc;	/* 0x80 */
324 	uint32	cyclecnt;	/* 0x90 */
325 	uint32	inttimer;	/* 0x94 */
326 	uint32	intmask;	/* 0x98 */
327 	uint32	intstatus;	/* 0x9c */
329 	uint32	clk_ctl_st;	/* 0x1e0 */
331 	uint32  powerctl;	/* 0x1e8 */
337 	uint32	corecontrol;		/* 0x0 */
338 	uint32	corecapabilities;	/* 0x4 */
339 	uint32	corestatus;		/* 0x8 */
340 	uint32	biststatus;		/* 0xc */
341 	uint32	nmiisrst;		/* 0x10 */
342 	uint32	nmimask;		/* 0x14 */
343 	uint32	isrmask;		/* 0x18 */
344 	uint32	swintreg;		/* 0x1C */
345 	uint32	intstatus;		/* 0x20 */
346 	uint32	intmask;		/* 0x24 */
347 	uint32	cyclecnt;		/* 0x28 */
348 	uint32	inttimer;		/* 0x2c */
349 	uint32	gpioselect;		/* 0x30 */
350 	uint32	gpioenable;		/* 0x34 */
352 	uint32	bankidx;		/* 0x40 */
353 	uint32	bankinfo;		/* 0x44 */
354 	uint32	bankstbyctl;		/* 0x48 */
355 	uint32	bankpda;		/* 0x4c */
356 	uint32	dyn_stby_control;	/* 0x50 */
358 	uint32	tcampatchctrl;		/* 0x68 */
359 	uint32	tcampatchtblbaseaddr;	/* 0x6c */
360 	uint32	tcamcmdreg;		/* 0x70 */
361 	uint32	tcamdatareg;		/* 0x74 */
362 	uint32	tcambankxmaskreg;	/* 0x78 */
364 	uint32  mpucontrol;		/* 0x90 */
365 	uint32  mpucapabilities;	/* 0x94 */
366 	uint32	rom_reloc_addr;		/* 0x98 */
368 	uint32  region_n_regs[16];	/* 0xa0 - 0xdc */
370 	uint32  initiat_n_masks[16];	/* 0x120 - 0x15c */
372 	uint32	clk_ctl_st;		/* 0x1e0 */
373 	uint32	hw_war;			/* 0x1e4 */
374 	uint32	powerctl;		/* 0x1e8 */
375 	uint32  powerctl2;		/* 0x1ec */
379 #define SBRESETLOG_CR4		0x4
383 	uint32	corecontrol;		/* 0x0 */
384 	uint32	corecapabilities;	/* 0x4 */
385 	uint32	corestatus;		/* 0x8 */
386 	uint32	tracecontrol;		/* 0xc */
387 	uint32	gpioselect;		/* 0x10 */
388 	uint32	gpioenable;		/* 0x14 */
390 	uint32	clk_ctl_st;		/* 0x1e0 */
391 	uint32	workaround;		/* 0x1e4 */
392 	uint32  powerctl;		/* 0x1e8 */
393 	uint32  powerctl2;		/* 0x1ec */