Lines Matching refs:BCM_MASK32
40 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb))) macro
2305 #define PMU_CC6_RX4_CLK_SEQ_SELECT_MASK BCM_MASK32(1u, 0u)
3092 #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(23u, 20u)
3094 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28)
3107 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
3110 #define PMU_4369_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9)
3112 #define PMU_4369_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10)
3114 #define PMU_4369_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11)
3120 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
3122 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15)
3124 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18)
3126 #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21)
3134 #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28)
3146 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
3149 #define PMU_4362_VREG8_ASR_OVADJ_PFM_MASK BCM_MASK32(9, 5)
3152 #define PMU_4362_VREG8_ASR_OVADJ_PWM_MASK BCM_MASK32(14, 10)
3155 #define PMU_4362_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9)
3157 #define PMU_4362_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10)
3159 #define PMU_4362_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11)
3165 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
3167 #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15)
3169 #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18)
3171 #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21)