Lines Matching +full:btcm +full:- +full:enable
25 * <<Broadcom-WL-IPTag/Dual:>>
40 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
50 * be assigned their respective chipc-specific address space and connected to the Always On
133 uint32 PAD[3]; /* 0x754-0x75C */
136 uint32 PAD[2]; /* 0x768-0x76C */
137 uint32 extwakereqmask[2]; /* 0x770-0x774 */
138 uint32 PAD[2]; /* 0x778-0x77C */
254 /* gpio - cleared only by power-on-reset */
482 uint32 PAD[2]; /* 0x768-0x76C */
483 uint32 extwakereqmask[2]; /* 0x770-0x774 */
484 uint32 PAD[2]; /* 0x778-0x77C */
486 uint32 PAD[3]; /* 0x784 - 0x78c */
488 uint32 PAD[PADSZ(0x794u, 0x7b0u)]; /* 0x794 - 0x7b0 */
499 uint32 PAD[PADSZ(0x7dcu, 0x7e4u)]; /* 0x7dc - 0x7e4 */
501 uint32 PAD[PADSZ(0x7ecu, 0x7fcu)]; /* 0x7ec - 0x7fc */
842 #define CC_CAP_MIPSEB 0x00000004u /**< MIPS is in big-endian mode */
858 #define CC_CAP_BKPLN64 0x08000000u /**< 64-bit backplane */
899 * Debug register - gate off all the SPM ring oscillator clock outputs
906 * 00 - Use ILP clock as reference clock
907 * 01 - Use divided ALP clock
908 * 10 - Use divided jtag TCK
910 * 0 - SPM disabled
911 * 1 - SPM enabled
912 * Program all the SPM controls before enabling spm. For one-shot operation,
913 * SpmIdle indicates when the one-shot run has completed. After one-shot
941 * 0 - no divide
942 * 1 - divide by 2
943 * 2 - divide by 4
944 * 3 - divide by 8
945 * 4 - divide by 16
946 * 5 - divide by 32
948 * 0 - no divide
949 * 1 to 15 - divide by (prediv2+1)
963 * 00 - selects ring oscillator clock;
964 * 10 - selects functional clock;
965 * 11 - selects DFT clocks;
969 * Interrupt hi enable (MonEn should be 1)
971 * Interrupt hi enable (MonEn should be 1)
975 * Enable monitor, interrupt and watermark functions
1033 #define DVFS_CORE_SYSMEM ((PMUREV((sih)->pmurev) < 43u) ? \
1112 * 00 - LDV
1113 * 01 - NDV
1129 * Bits 0 Enable DVFS
1130 * This bit will enable DVFS operation. When cleared, the complete DVFS
1158 * This 2-bit field is the DVFS voltage status mapped as
1159 * 00 - LDV
1160 * 01 - NDV
1161 * 10 - HDV
1163 * This 2-bit field is used to request DVFS voltage mapped as shown above
1175 * 0 - 160MHz
1176 * 1 - 80Mhz - BT can force CB backplane clock to 80Mhz when wl is down
1184 /* WL Channel Info to BT via GCI - bits 40 - 47 */
1186 /* WL indication of MCHAN enabled/disabled to BT - bit 36 */
1190 /* WL indication of SWDIV enabled/disabled to BT - bit 33 */
1201 /* WL inidcation of Aux Core 2G hibernate status - bit 50 */
1210 /* bits [51:48] - reserved for wlan TX pwr index */
1217 /* bit [40] - to indicate RC2CX mode to BT */
1233 /* ALP clock on pre-PMU chips */
1263 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */
1265 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */
1437 #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */
1438 #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */
1444 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */
1447 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */
1464 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */
1465 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */
1472 #define JCTRL_EXT_EN 2 /**< Enable external targets */
1473 #define JCTRL_EN 1 /**< Enable Jtag master */
1477 #define SWDCTRL_INT_EN 8 /**< Enable internal targets */
1479 #define SWDCTRL_OVJTAG 2 /**< Enable shared SWD/JTAG pins */
1480 #define SWDCTRL_EN 1 /**< Enable Jtag master */
1542 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */
1543 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */
1551 /* WL sub-system reset */
1553 /* BT sub-system reset */
1556 /* Both WL and BT sub-system reset */
1575 #define CF_EN 0x00000001 /**< enable */
1588 #define CF_CE 0x00000100 /**< clock enable */
1732 #define CC_F6_3 0x03 /**< 6-bit fields like */
1738 #define CC_F5_BIAS 5 /**< 5-bit fields get this added */
1774 #define CC_CFG_EN 0x0001 /**< Enable */
1782 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */
1814 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */
1822 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */
1825 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */
1830 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */
1840 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */
1895 ((((val) & MUXENAB_DEF_ ## name ## _MASK) >> MUXENAB_DEF_ ## name ## _SHIFT) - 1)
1906 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */
1918 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */
1920 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */
1921 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */
1927 #define UART_FCR_FIFO_ENABLE 1 /**< FIFO control register bit controlling FIFO enable/disable */
1939 /* Interrupt Enable Register (IER) bits */
1940 #define UART_IER_PTIME 128 /**< Programmable THRE Interrupt Mode Enable */
1941 #define UART_IER_EDSSI 8 /**< enable modem status interrupt */
1942 #define UART_IER_ELSI 4 /**< enable receiver line status interrupt */
1943 #define UART_IER_ETBEI 2 /**< enable transmitter holding register empty interrupt */
1944 #define UART_IER_ERBFI 1 /**< enable data available interrupt */
1994 #define PMU_ST_EN_SHIFT (8) /* stat timer enable */
1998 #define PMU_ST_INT_EN_SHIFT (9) /* stat timer enable */
2032 /* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */
2037 * bit 18 of the PMU interrupt vector - S/R self test fails
2353 #define PMU_CC12_DISABLE_LQ_CLK_ON (1u << 31u) /* HW4387-254 */
2374 /* HW4368-331 */
2419 /* Enable wl booker to force a P channel sleep handshake upon assertion of wl_SSReset */
2905 #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */
3015 #define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */
3075 /* 43012 resources - End */
3605 * https://drive.google.com/file/d/1JjvNhp-RIXJBtw99M4w5ww4MmDsBJbpD
3663 /* backplane address, use last 16k of BTCM for s/r */
3666 /* backplane address, use last 32k of BTCM for s/r */
4166 * the memory space allows 192KB (0x1850_0000 - 0x1852_FFFF)
4171 /* 43012 PMU resources based on pmu_params.xls - Start */
4223 /* 43012 - offset at 5K */
4611 /* GCI GPIO for function sel GCI-0/GCI-1 */
4860 #define MUXENAB43012_GETIX(val, name) (val - 1)
4880 /* Fields in eci_inputlo register - [0:31] */
4881 #define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */
4883 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
4885 #define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */
4887 #define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */
4889 #define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */
4891 #define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */
4893 #define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */
4898 * - BT packet type information bits [7:0]
4900 /* [3:0] - Task (link) type */
4918 /* [8] - Master / Slave */
4921 /* [11:9] - multi-level priority */
4924 /* [19:12] - BT transmit power */
4925 /* [27:20] - BT RSSI */
4926 /* [28] - VAD silence */
4927 /* [31:29] - Undefined */
4928 /* Register eci_inputmi values - [32:63] - none defined */
4929 /* [63:32] - Undefined */
4932 /* Fields in eci_output register - [0:31] */
4951 * 0 - TxConf (ucode)
4952 * 38 - FM disable (wl)
4953 * 39 - Allow sim rx (ucode)
4954 * 40 - Num antennas (wl)
4955 * 43:41 - WLAN channel exclusion BW (wl)
4956 * 47:44 - WLAN channel (wl)
4959 * 15:0 - wl
4960 * 16 -
4961 * 18 - FM disable
4962 * 30 - wl interrupt
4963 * 31 - ucode interrupt
4964 * others - unassigned (presumed to be with dot11mac/ucode)
4972 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
5040 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
5042 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
5109 /* WLAN channel numbers - used from wifi.h */
5121 /* WLAN - number of antenna */
5130 #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */
5143 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
5223 /* RFC - RNG FIFO COUNT */