Lines Matching full:u
40 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
763 #define GC_BT_CTRL_UARTPADS_OVRD_EN (1u << 1)
878 #define CC_CAP_EXT1_CORE_CNT_SHIFT (7u)
918 #define SPMCTRL_ALPDIV_SHIFT 16u
921 #define SPMCTRL_RSTSPM_SHIFT 2u
924 #define SPMCTRL_USEDIVALP_SHIFT 1u
927 #define SPMCTRL_SPMEN_SHIFT 0u
952 #define SPMCLKCTRL_SAMPLETIME_SHIFT 24u
955 #define SPMCLKCTRL_ONESHOT_SHIFT 31u
977 #define MONCTRLN_TARGETRO_PMU_ALP_CLK 0u
978 #define MONCTRLN_TARGETRO_PCIE_ALP_CLK 1u
979 #define MONCTRLN_TARGETRO_CB_BP_CLK 2u
980 #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387B0 3u
981 #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387C0 20u
982 #define MONCTRLN_TARGETRO_SHIFT 8u
984 #define MONCTRLN_TARGETROMAX 64u
985 #define MONCTRLN_TARGETROHI 32u
989 #define MONCTRLN_TARGETROEXT_SHIFT 6u
992 #define MONCTRLN_MONEN_SHIFT 0u
1007 #define CTRLN_REQUEST_OVERRIDE_SHIFT 10u
1009 #define CTRLN_REQUEST_VAL_SHIFT 8u
1011 #define CTRLN_RSRC_TRIG_SHIFT 0u
1024 #define DVFS_CORE_CHIPC 0u
1025 #define DVFS_CORE_PCIE 1u
1026 #define DVFS_CORE_ARM 2u
1027 #define DVFS_CORE_D11_MAIN 3u
1028 #define DVFS_CORE_D11_AUX 4u
1029 #define DVFS_CORE_D11_SCAN 5u
1030 #define DVFS_CORE_BT_MAIN 6u
1031 #define DVFS_CORE_BT_SCAN 7u
1032 #define DVFS_CORE_HWA 8u
1033 #define DVFS_CORE_SYSMEM ((PMUREV((sih)->pmurev) < 43u) ? \
1034 9u : 8u)
1051 #define DVFS_VOLTAGE_RAMP_DOWN_STEP 1u
1052 #define DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT 28u
1054 #define DVFS_VOLTAGE_RAMP_UP_STEP 1u
1055 #define DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT 24u
1057 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL 1u
1058 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT 16u
1060 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL 1u
1061 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT 8u
1063 #define DVFS_CLOCK_STABLE_TIME 3u
1075 #define DVFS_VOLTAGE_XDV 0u /* Reserved */
1080 #define DVFS_VOLTAGE_HDV 72u /* 0.72V */
1081 #define DVFS_VOLTAGE_HDV_MAX 80u /* 0.80V */
1083 #define DVFS_VOLTAGE_HDV_PWR_OPT 68u /* 0.68V */
1084 #define DVFS_VOLTAGE_HDV_SHIFT 16u
1091 #define DVFS_VOLTAGE_NDV 72u /* 0.72V */
1092 #define DVFS_VOLTAGE_NDV_NON_LVM 76u /* 0.76V */
1093 #define DVFS_VOLTAGE_NDV_MAX 80u /* 0.80V */
1095 #define DVFS_VOLTAGE_NDV_PWR_OPT 68u /* 0.68V */
1096 #define DVFS_VOLTAGE_NDV_SHIFT 8u
1101 #define DVFS_VOLTAGE_LDV 65u /* 0.65V */
1103 #define DVFS_VOLTAGE_LDV_PWR_OPT 65u /* 0.65V */
1104 #define DVFS_VOLTAGE_LDV_SHIFT 0u
1117 #define DVFS_RAW_CORE_REQ_SHIFT 26u
1119 #define DVFS_ACT_CORE_REQ_SHIFT 24u
1121 #define DVFS_CORE_STATUS_SHIFT 11u
1123 #define DVFS_CLK_SEL_SHIFT 8u
1125 #define DVFS_VOLTAGE_SHIFT 0u
1134 #define DVFS_DISABLE_DVFS 0u
1135 #define DVFS_ENABLE_DVFS 1u
1136 #define DVFS_ENABLE_DVFS_SHIFT 0u
1137 #define DVFS_ENABLE_DVFS_MASK (1u << DVFS_ENABLE_DVFS_SHIFT)
1139 #define DVFS_LPO_DELAY 40u /* usec (1 LPO clock + margin) */
1140 #define DVFS_FASTLPO_DELAY 2u /* usec (1 FAST_LPO clock + margin) */
1141 #define DVFS_NDV_LPO_DELAY 1500u
1142 #define DVFS_NDV_FASTLPO_DELAY 50u
1152 #define DVFS_LDV 0u
1153 #define DVFS_NDV 1u
1154 #define DVFS_HDV 2u
1168 #define DVFS_REQ_SHIFT 0u
1170 #define DVFS_STATUS_SHIFT 16u
1178 #define GCI_CC16_CB_CLOCK_SEL_160 0u
1179 #define GCI_CC16_CB_CLOCK_SEL_80 1u
1180 #define GCI_CC16_CB_CLOCK_SEL_SHIFT 0u
1199 #define GCI_WL2BT_2G_AWAKE_MASK (1u << 28u)
1885 #define MUXENAB_DEF_HOSTWAKE_SHIFT 4u
1889 #define MUXENAB_GCI_UART_SHIFT 8u
1891 #define MUXENAB_GCI_UART_FNSEL_SHIFT 12u
1984 #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT (20u) /* # of MAC rsrc req timers */
1985 #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_MASK (7u << PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT)
1986 #define PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT (23u) /* pmu int rcvr cnt */
1987 #define PCAP_EXT_PMU_INTR_RCVR_CNT_MASK (7u << PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT)
2029 #define PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT (8u)
2030 #define PMU_INT_STAT_RSRC_EVENT_INT0_MASK (1u << PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT)
2033 #define PMU_INT_STAT_TIMER_INT_SHIFT (16u)
2034 #define PMU_INT_STAT_TIMER_INT_MASK (1u << PMU_INT_STAT_TIMER_INT_SHIFT)
2039 #define PMU_INT_STAT_SR_ERR_SHIFT (18u)
2040 #define PMU_INT_STAT_SR_ERR_MASK (1u << PMU_INT_STAT_SR_ERR_SHIFT)
2043 #define PMURES_BIT(bit) (1u << (bit))
2062 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20u << 0u)
2064 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3Fu << 0u)
2065 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1Au << 6u)
2066 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3Fu << 6u)
2067 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_VAL (0x00u << 12u)
2068 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_MASK (0x07u << 12u)
2069 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_VAL (0x02u << 15u)
2070 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_MASK (0x07u << 15u)
2089 #define PMU_CC0_4387_BT_PU_WAKE_MASK (0x3u << 30u)
2130 #define PMU_CC2_CB2WL_INTR_PWRREQ_EN (1u << 13u)
2131 #define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1u << 15u)
2134 #define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1u << 16u)
2135 #define PMU_CHIPCTL2 2u
2136 #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1u << 18u)
2137 #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1u << 19u)
2138 #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1u << 20u)
2139 #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1u << 21u)
2140 #define PMU_CC2_MASK_WL_DEV_WAKE (1u << 22u)
2141 #define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1u << 25u)
2142 #define PMU_CC2_GCI2_WAKE (1u << 31u)
2144 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2145 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2146 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2147 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2149 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2150 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2151 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2152 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2154 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2155 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2156 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2157 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2159 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2160 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2161 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2162 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2165 #define PMU_CHIPCTL3 3u
2166 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19u
2167 #define PMU_CC3_ENABLE_RF_SHIFT 22u
2168 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23u
2170 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u)
2171 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u)
2172 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u)
2173 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u)
2174 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u)
2175 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u)
2178 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2u << 12u)
2179 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7u << 12u)
2180 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x2u << 27u)
2181 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7u << 27u)
2183 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u)
2184 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u)
2185 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u)
2186 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u)
2187 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u)
2188 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u)
2189 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21u)
2190 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21u)
2191 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_VAL (0x02u << 12u)
2192 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_MASK (0x07u << 12u)
2194 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_VAL (0x02u << 27u)
2195 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_MASK (0x07u << 27u)
2239 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDB_ON (1u << 15u)
2240 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u)
2241 #define PMU_CC4_4369_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u)
2242 #define PMU_CC4_4369_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u)
2244 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDB_ON (1u << 21u)
2245 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDRET_ON (1u << 22u)
2246 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u)
2247 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u)
2249 #define PMU_CC4_4362_PD_CBUCK2VDDB_ON (1u << 15u)
2250 #define PMU_CC4_4362_PD_CBUCK2VDDRET_ON (1u << 16u)
2251 #define PMU_CC4_4362_PD_MEMLPLDO2VDDB_ON (1u << 17u)
2252 #define PMU_CC4_4362_PD_MEMLPDLO2VDDRET_ON (1u << 18u)
2254 #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDB_ON (1u << 15u)
2255 #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u)
2256 #define PMU_CC4_4378_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u)
2257 #define PMU_CC4_4378_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u)
2259 #define PMU_CC4_4378_AUX_PD_CBUCK2VDDB_ON (1u << 21u)
2260 #define PMU_CC4_4378_AUX_PD_CBUCK2VDDRET_ON (1u << 22u)
2261 #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u)
2262 #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u)
2264 #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDB_ON (1u << 15u)
2265 #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u)
2266 #define PMU_CC4_4387_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u)
2267 #define PMU_CC4_4387_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u)
2269 #define PMU_CC4_4387_AUX_PD_CBUCK2VDDB_ON (1u << 21u)
2270 #define PMU_CC4_4387_AUX_PD_CBUCK2VDDRET_ON (1u << 22u)
2271 #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u)
2272 #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u)
2277 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDB_ON (1u << 9u)
2278 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDRET_ON (1u << 10u)
2279 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u)
2280 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u)
2282 #define PMU_CC5_4362_SUBCORE_CBUCK2VDDB_ON (1u << 9u)
2283 #define PMU_CC5_4362_SUBCORE_CBUCK2VDDRET_ON (1u << 10u)
2284 #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u)
2285 #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u)
2287 #define PMU_CC5_4378_SUBCORE_CBUCK2VDDB_ON (1u << 9u)
2288 #define PMU_CC5_4378_SUBCORE_CBUCK2VDDRET_ON (1u << 10u)
2289 #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u)
2290 #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u)
2292 #define PMU_CC5_4387_SUBCORE_CBUCK2VDDB_ON (1u << 9u)
2293 #define PMU_CC5_4387_SUBCORE_CBUCK2VDDRET_ON (1u << 10u)
2294 #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u)
2295 #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u)
2297 #define PMU_CC5_4388_SUBCORE_SDTCCLK0_ON (1u << 3u)
2298 #define PMU_CC5_4388_SUBCORE_SDTCCLK1_ON (1u << 4u)
2300 #define PMU_CC5_4389_SUBCORE_SDTCCLK0_ON (1u << 3u)
2301 #define PMU_CC5_4389_SUBCORE_SDTCCLK1_ON (1u << 4u)
2305 #define PMU_CC6_RX4_CLK_SEQ_SELECT_MASK BCM_MASK32(1u, 0u)
2346 #define PMU_CC10_PCIE_RESET0_CNT_SLOW_MASK (0xFu << 4u)
2347 #define PMU_CC10_PCIE_RESET1_CNT_SLOW_MASK (0xFu << 12u)
2353 #define PMU_CC12_DISABLE_LQ_CLK_ON (1u << 31u) /* HW4387-254 */
2358 #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u)
2359 #define PMU_CC13_SUBCORE_CBUCK2VDDRET_OFF (1u << 1u)
2360 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDB_OFF (1u << 2u)
2361 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDRET_OFF (1u << 3u)
2363 #define PMU_CC13_MAIN_CBUCK2VDDB_OFF (1u << 4u)
2364 #define PMU_CC13_MAIN_CBUCK2VDDRET_OFF (1u << 5u)
2365 #define PMU_CC13_MAIN_MEMLPLDO2VDDB_OFF (1u << 6u)
2366 #define PMU_CC13_MAIN_MEMLPLDO2VDDRET_OFF (1u << 7u)
2368 #define PMU_CC13_AUX_CBUCK2VDDB_OFF (1u << 8u)
2369 #define PMU_CC13_AUX_MEMLPLDO2VDDB_OFF (1u << 10u)
2370 #define PMU_CC13_AUX_MEMLPLDO2VDDRET_OFF (1u << 11u)
2371 #define PMU_CC13_AUX_CBUCK2VDDRET_OFF (1u << 12u)
2372 #define PMU_CC13_CMN_MEMLPLDO2VDDRET_ON (1u << 18u)
2375 #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF0 (1u << 13u)
2376 #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF1 (1u << 14u)
2377 #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF0 (1u << 15u)
2378 #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF1 (1u << 19u)
2380 #define PMU_CC13_LHL_TIMER_SELECT (1u << 23u)
2382 #define PMU_CC13_4369_LHL_TIMER_SELECT (1u << 23u)
2383 #define PMU_CC13_4378_LHL_TIMER_SELECT (1u << 23u)
2385 #define PMU_CC13_4387_ENAB_RADIO_REG_CLK (1u << 9u)
2386 #define PMU_CC13_4387_LHL_TIMER_SELECT (1u << 23u)
2395 #define PMU_CHIPCTL17 17u
2397 #define PMU_CC17_SCAN_DIG_SR_CLK_SHIFT (2u)
2398 #define PMU_CC17_SCAN_DIG_SR_CLK_MASK (3u << 2u)
2399 #define PMU_CC17_SCAN_CBUCK2VDDB_OFF (1u << 8u)
2400 #define PMU_CC17_SCAN_MEMLPLDO2VDDB_OFF (1u << 10u)
2401 #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_OFF (1u << 11u)
2402 #define PMU_CC17_SCAN_CBUCK2VDDB_ON (1u << 24u)
2403 #define PMU_CC17_SCAN_MEMLPLDO2VDDB_ON (1u << 26u)
2404 #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_ON (1u << 27u)
2407 #define SCAN_DIG_SR_CLK_53P35_MHZ (1u) /* 53.35 MHz */
2408 #define SCAN_DIG_SR_CLK_40_MHZ (2u) /* 40 MHz */
2411 #define PMU_CHIPCTL18 18u
2414 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_OFF (1u << 1u)
2415 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_MASK (7u << 1u)
2417 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_8ms 7u /* (2^(7+1))*32us = 8ms */
2420 #define PMU_CC18_WL_BOOKER_FORCEPWRDWN_EN (1u << 4u)
2423 #define PMU_CHIPCTL19 19u
2425 #define PMU_CC19_ASYNC_ATRESETMN (1u << 9u)
2428 #define PMU_CC23_MACPHYCLK_MASK (1u << 31u)
2430 #define PMU_CC23_AT_CLK0_ON (1u << 14u)
2431 #define PMU_CC23_AT_CLK1_ON (1u << 15u)
2442 #define PMU_CC15_PCIE_VDDB_CURRENT_LIMIT_DELAY_MASK (0xFu << 4u)
2443 #define PMU_CC15_PCIE_VDDB_FORCE_RPS_PWROK_DELAY_MASK (0xFu << 8u)
2846 #define PMU4388_ARMPLL_I_NDIV_INT_SHIFT 15u
2853 #define PMU4389_ARMPLL_I_NDIV_INT_SHIFT 15u
3032 #define CC_FNSEL_HWDEF (0u)
3033 #define CC_FNSEL_SAMEASPIN (1u)
3034 #define CC_FNSEL_GPIO0 (2u)
3035 #define CC_FNSEL_GPIO1 (3u)
3036 #define CC_FNSEL_GCI0 (4u)
3037 #define CC_FNSEL_GCI1 (5u)
3038 #define CC_FNSEL_UART (6u)
3039 #define CC_FNSEL_SFLASH (7u)
3040 #define CC_FNSEL_SPROM (8u)
3041 #define CC_FNSEL_MISC0 (9u)
3042 #define CC_FNSEL_MISC1 (10u)
3043 #define CC_FNSEL_MISC2 (11u)
3044 #define CC_FNSEL_IND (12u)
3045 #define CC_FNSEL_PDN (13u)
3046 #define CC_FNSEL_PUP (14u)
3047 #define CC_FNSEL_TRI (15u)
3050 #define CC4387_FNSEL_FUART (3u)
3051 #define CC4387_FNSEL_DBG_UART (6u)
3052 #define CC4387_FNSEL_SPI (7u)
3055 #define PMU_VREG_0 (0u)
3056 #define PMU_VREG_1 (1u)
3057 #define PMU_VREG_2 (2u)
3058 #define PMU_VREG_3 (3u)
3059 #define PMU_VREG_4 (4u)
3060 #define PMU_VREG_5 (5u)
3061 #define PMU_VREG_6 (6u)
3062 #define PMU_VREG_7 (7u)
3063 #define PMU_VREG_8 (8u)
3064 #define PMU_VREG_9 (9u)
3065 #define PMU_VREG_10 (10u)
3066 #define PMU_VREG_11 (11u)
3067 #define PMU_VREG_12 (12u)
3068 #define PMU_VREG_13 (13u)
3069 #define PMU_VREG_14 (14u)
3070 #define PMU_VREG_15 (15u)
3071 #define PMU_VREG_16 (16u)
3088 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u)
3089 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_SHIFT 11u
3090 #define PMU_4369_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u)
3091 #define PMU_4369_VREG_5_LPLDO_POWER_UP_SHIFT 27u
3092 #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(23u, 20u)
3093 #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_SHIFT 20u
3095 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT 28u
3097 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u)
3098 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT 3u
3100 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u)
3101 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_SHIFT 27u
3102 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u)
3103 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_SHIFT 28u
3104 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u)
3105 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_SHIFT 29u
3108 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u
3111 #define PMU_4369_VREG13_RSRC_EN0_ASR_SHIFT 9u
3113 #define PMU_4369_VREG13_RSRC_EN1_ASR_SHIFT 10u
3115 #define PMU_4369_VREG13_RSRC_EN2_ASR_SHIFT 11u
3117 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u)
3118 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT 23u
3121 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u
3123 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT 15u
3125 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT 18u
3127 #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u
3130 #define PMU_4362_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u)
3131 #define PMU_4362_VREG_5_MISCLDO_POWER_UP_SHIFT (11u)
3132 #define PMU_4362_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u)
3133 #define PMU_4362_VREG_5_LPLDO_POWER_UP_SHIFT (27u)
3135 #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT (28u)
3136 #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u)
3137 #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_SHIFT (3u)
3139 #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u)
3140 #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_SHIFT (27u)
3141 #define PMU_4362_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u)
3142 #define PMU_4362_VREG_7_WL_PMU_LP_MODE_SHIFT (28u)
3143 #define PMU_4362_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u)
3144 #define PMU_4362_VREG_7_WL_PMU_LV_MODE_SHIFT (29u)
3147 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT (0u)
3150 #define PMU_4362_VREG8_ASR_OVADJ_PFM_SHIFT (5u)
3153 #define PMU_4362_VREG8_ASR_OVADJ_PWM_SHIFT (10u)
3156 #define PMU_4362_VREG13_RSRC_EN0_ASR_SHIFT 9u
3158 #define PMU_4362_VREG13_RSRC_EN1_ASR_SHIFT 10u
3160 #define PMU_4362_VREG13_RSRC_EN2_ASR_SHIFT 11u
3162 #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u)
3163 #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_SHIFT (23u)
3166 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_SHIFT (0u)
3168 #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_SHIFT (15u)
3170 #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_SHIFT (18u)
3172 #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u
3175 #define VREG0_4378_CSR_VOLT_ADJ_PWM_SHIFT 8u
3177 #define VREG0_4378_CSR_VOLT_ADJ_PFM_SHIFT 13u
3179 #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_SHIFT 18u
3181 #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_SHIFT 23u
3183 #define PMU_4387_VREG1_CSR_OVERI_DIS_MASK (1u << 22u)
3186 #define PMU_4387_VREG8_ASR_OVERI_DIS_MASK (1u << 7u)
3188 #define PMU_4388_VREG6_WL_PMU_LV_MODE_SHIFT (1u)
3189 #define PMU_4388_VREG6_WL_PMU_LV_MODE_MASK (1u << PMU_4388_VREG6_WL_PMU_LV_MODE_SHIFT)
3190 #define PMU_4388_VREG6_MEMLDO_PU_SHIFT (3u)
3191 #define PMU_4388_VREG6_MEMLDO_PU_MASK (1u << PMU_4388_VREG6_MEMLDO_PU_SHIFT)
3193 #define PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT (1u)
3194 #define PMU_4389_VREG6_WL_PMU_LV_MODE_MASK (1u << PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT)
3195 #define PMU_4389_VREG6_MEMLDO_PU_SHIFT (3u)
3196 #define PMU_4389_VREG6_MEMLDO_PU_MASK (1u << PMU_4389_VREG6_MEMLDO_PU_SHIFT)
3199 #define PMU_VREG13_ASR_OVADJ_PWM_SHIFT (16u)
3201 #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_MASK (1u << 18u)
3202 #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_SHIFT (18u)
3358 #define RES4388_DUMMY 0u
3359 #define RES4388_FAST_LPO_AVAIL 1u
3360 #define RES4388_PMU_LP 2u
3361 #define RES4388_MISC_LDO 3u
3362 #define RES4388_SERDES_AFE_RET 4u
3363 #define RES4388_XTAL_HQ 5u
3364 #define RES4388_XTAL_PU 6u
3365 #define RES4388_XTAL_STABLE 7u
3366 #define RES4388_PWRSW_DIG 8u
3367 #define RES4388_BTMC_TOP_RDY 9u
3368 #define RES4388_BTSC_TOP_RDY 10u
3369 #define RES4388_PWRSW_AUX 11u
3370 #define RES4388_PWRSW_SCAN 12u
3371 #define RES4388_CORE_RDY_SCAN 13u
3372 #define RES4388_PWRSW_MAIN 14u
3373 #define RES4388_RESERVED_15 15u
3374 #define RES4388_RESERVED_16 16u
3375 #define RES4388_CORE_RDY_DIG 17u
3376 #define RES4388_CORE_RDY_AUX 18u
3377 #define RES4388_ALP_AVAIL 19u
3378 #define RES4388_RADIO_PU_AUX 20u
3379 #define RES4388_RADIO_PU_SCAN 21u
3380 #define RES4388_CORE_RDY_MAIN 22u
3381 #define RES4388_RADIO_PU_MAIN 23u
3382 #define RES4388_MACPHY_CLK_SCAN 24u
3383 #define RES4388_CORE_RDY_CB 25u
3384 #define RES4388_PWRSW_CB 26u
3385 #define RES4388_ARMCLKAVAIL 27u
3386 #define RES4388_HT_AVAIL 28u
3387 #define RES4388_MACPHY_CLK_AUX 29u
3388 #define RES4388_MACPHY_CLK_MAIN 30u
3389 #define RES4388_RESERVED_31 31u
3392 #define RES4389_DUMMY 0u
3393 #define RES4389_FAST_LPO_AVAIL 1u
3394 #define RES4389_PMU_LP 2u
3395 #define RES4389_MISC_LDO 3u
3396 #define RES4389_SERDES_AFE_RET 4u
3397 #define RES4389_XTAL_HQ 5u
3398 #define RES4389_XTAL_PU 6u
3399 #define RES4389_XTAL_STABLE 7u
3400 #define RES4389_PWRSW_DIG 8u
3401 #define RES4389_BTMC_TOP_RDY 9u
3402 #define RES4389_BTSC_TOP_RDY 10u
3403 #define RES4389_PWRSW_AUX 11u
3404 #define RES4389_PWRSW_SCAN 12u
3405 #define RES4389_CORE_RDY_SCAN 13u
3406 #define RES4389_PWRSW_MAIN 14u
3407 #define RES4389_RESERVED_15 15u
3408 #define RES4389_RESERVED_16 16u
3409 #define RES4389_CORE_RDY_DIG 17u
3410 #define RES4389_CORE_RDY_AUX 18u
3411 #define RES4389_ALP_AVAIL 19u
3412 #define RES4389_RADIO_PU_AUX 20u
3413 #define RES4389_RADIO_PU_SCAN 21u
3414 #define RES4389_CORE_RDY_MAIN 22u
3415 #define RES4389_RADIO_PU_MAIN 23u
3416 #define RES4389_MACPHY_CLK_SCAN 24u
3417 #define RES4389_CORE_RDY_CB 25u
3418 #define RES4389_PWRSW_CB 26u
3419 #define RES4389_ARMCLKAVAIL 27u
3420 #define RES4389_HT_AVAIL 28u
3421 #define RES4389_MACPHY_CLK_AUX 29u
3422 #define RES4389_MACPHY_CLK_MAIN 30u
3423 #define RES4389_RESERVED_31 31u
3426 #define RES4397_DUMMY 0u
3427 #define RES4397_FAST_LPO_AVAIL 1u
3428 #define RES4397_PMU_LP 2u
3429 #define RES4397_MISC_LDO 3u
3430 #define RES4397_SERDES_AFE_RET 4u
3431 #define RES4397_XTAL_HQ 5u
3432 #define RES4397_XTAL_PU 6u
3433 #define RES4397_XTAL_STABLE 7u
3434 #define RES4397_PWRSW_DIG 8u
3435 #define RES4397_BTMC_TOP_RDY 9u
3436 #define RES4397_BTSC_TOP_RDY 10u
3437 #define RES4397_PWRSW_AUX 11u
3438 #define RES4397_PWRSW_SCAN 12u
3439 #define RES4397_CORE_RDY_SCAN 13u
3440 #define RES4397_PWRSW_MAIN 14u
3441 #define RES4397_XTAL_PM_CLK 15u
3442 #define RES4397_PWRSW_DRR2 16u
3443 #define RES4397_CORE_RDY_DIG 17u
3444 #define RES4397_CORE_RDY_AUX 18u
3445 #define RES4397_ALP_AVAIL 19u
3446 #define RES4397_RADIO_PU_AUX 20u
3447 #define RES4397_RADIO_PU_SCAN 21u
3448 #define RES4397_CORE_RDY_MAIN 22u
3449 #define RES4397_RADIO_PU_MAIN 23u
3450 #define RES4397_MACPHY_CLK_SCAN 24u
3451 #define RES4397_CORE_RDY_CB 25u
3452 #define RES4397_PWRSW_CB 26u
3453 #define RES4397_ARMCLKAVAIL 27u
3454 #define RES4397_HT_AVAIL 28u
3455 #define RES4397_MACPHY_CLK_AUX 29u
3456 #define RES4397_MACPHY_CLK_MAIN 30u
3457 #define RES4397_RESERVED_31 31u
3474 #define GCI_CS_4387_FLL1MHZ_DAC_OUT_SHIFT (16u)
3476 #define GCI_CS_4389_FLL1MHZ_DAC_OUT_SHIFT (16u)
3490 #define CC2_4362_SDIO_AOS_WAKEUP_MASK (1u << 24u)
3491 #define CC2_4362_SDIO_AOS_WAKEUP_SHIFT 24u
3493 #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u)
3494 #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12u
3495 #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u)
3496 #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13u
3497 #define CC2_4378_MAIN_VDDRET_ON_MASK (1u << 15u)
3498 #define CC2_4378_MAIN_VDDRET_ON_SHIFT 15u
3499 #define CC2_4378_AUX_VDDRET_ON_MASK (1u << 16u)
3500 #define CC2_4378_AUX_VDDRET_ON_SHIFT 16u
3501 #define CC2_4378_GCI2WAKE_MASK (1u << 31u)
3502 #define CC2_4378_GCI2WAKE_SHIFT 31u
3503 #define CC2_4378_SDIO_AOS_WAKEUP_MASK (1u << 24u)
3504 #define CC2_4378_SDIO_AOS_WAKEUP_SHIFT 24u
3505 #define CC4_4378_LHL_TIMER_SELECT (1u << 0u)
3506 #define CC6_4378_PWROK_WDT_EN_IN_MASK (1u << 6u)
3507 #define CC6_4378_PWROK_WDT_EN_IN_SHIFT 6u
3508 #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u)
3509 #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_SHIFT 24u
3511 #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u)
3512 #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15u
3513 #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u)
3514 #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_SHIFT 16u
3516 #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u)
3517 #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12u
3518 #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u)
3519 #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13u
3520 #define CC2_4387_MAIN_VDDRET_ON_MASK (1u << 15u)
3521 #define CC2_4387_MAIN_VDDRET_ON_SHIFT 15u
3522 #define CC2_4387_AUX_VDDRET_ON_MASK (1u << 16u)
3523 #define CC2_4387_AUX_VDDRET_ON_SHIFT 16u
3524 #define CC2_4387_GCI2WAKE_MASK (1u << 31u)
3525 #define CC2_4387_GCI2WAKE_SHIFT 31u
3526 #define CC2_4387_SDIO_AOS_WAKEUP_MASK (1u << 24u)
3527 #define CC2_4387_SDIO_AOS_WAKEUP_SHIFT 24u
3528 #define CC4_4387_LHL_TIMER_SELECT (1u << 0u)
3529 #define CC6_4387_PWROK_WDT_EN_IN_MASK (1u << 6u)
3530 #define CC6_4387_PWROK_WDT_EN_IN_SHIFT 6u
3531 #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u)
3532 #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_SHIFT 24u
3534 #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u)
3535 #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15u
3536 #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u)
3537 #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_SHIFT 16u
3539 #define CC2_4388_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u)
3540 #define CC2_4388_MAIN_MEMLPLDO_VDDB_OFF_SHIFT (12u)
3541 #define CC2_4388_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u)
3542 #define CC2_4388_AUX_MEMLPLDO_VDDB_OFF_SHIFT (13u)
3543 #define CC2_4388_MAIN_VDDRET_ON_MASK (1u << 15u)
3544 #define CC2_4388_MAIN_VDDRET_ON_SHIFT (15u)
3545 #define CC2_4388_AUX_VDDRET_ON_MASK (1u << 16u)
3546 #define CC2_4388_AUX_VDDRET_ON_SHIFT (16u)
3547 #define CC2_4388_GCI2WAKE_MASK (1u << 31u)
3548 #define CC2_4388_GCI2WAKE_SHIFT (31u)
3549 #define CC2_4388_SDIO_AOS_WAKEUP_MASK (1u << 24u)
3550 #define CC2_4388_SDIO_AOS_WAKEUP_SHIFT (24u)
3551 #define CC4_4388_LHL_TIMER_SELECT (1u << 0u)
3552 #define CC6_4388_PWROK_WDT_EN_IN_MASK (1u << 6u)
3553 #define CC6_4388_PWROK_WDT_EN_IN_SHIFT (6u)
3554 #define CC6_4388_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u)
3555 #define CC6_4388_SDIO_AOS_CHIP_WAKEUP_SHIFT (24u)
3557 #define CC2_4388_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u)
3558 #define CC2_4388_USE_WLAN_BP_CLK_ON_REQ_SHIFT (15u)
3559 #define CC2_4388_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u)
3560 #define CC2_4388_USE_CMN_BP_CLK_ON_REQ_SHIFT (16u)
3562 #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u)
3563 #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_SHIFT (12u)
3564 #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u)
3565 #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_SHIFT (13u)
3566 #define CC2_4389_MAIN_VDDRET_ON_MASK (1u << 15u)
3567 #define CC2_4389_MAIN_VDDRET_ON_SHIFT (15u)
3568 #define CC2_4389_AUX_VDDRET_ON_MASK (1u << 16u)
3569 #define CC2_4389_AUX_VDDRET_ON_SHIFT (16u)
3570 #define CC2_4389_GCI2WAKE_MASK (1u << 31u)
3571 #define CC2_4389_GCI2WAKE_SHIFT (31u)
3572 #define CC2_4389_SDIO_AOS_WAKEUP_MASK (1u << 24u)
3573 #define CC2_4389_SDIO_AOS_WAKEUP_SHIFT (24u)
3574 #define CC4_4389_LHL_TIMER_SELECT (1u << 0u)
3575 #define CC6_4389_PWROK_WDT_EN_IN_MASK (1u << 6u)
3576 #define CC6_4389_PWROK_WDT_EN_IN_SHIFT (6u)
3577 #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u)
3578 #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_SHIFT (24u)
3580 #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u)
3581 #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_SHIFT (15u)
3582 #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u)
3583 #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_SHIFT (16u)
3595 #define VREG5_4387_MISCLDO_PU_SHIFT (11u)
3645 #define SR_ASM_ADDR_BLK_SIZE_SHIFT (9u)
3684 #define SR_ASM_SIZE_DIG_4388 (65536u)
3691 #define SR_ASM_SIZE_DIG_4389C0 (8192u * 8u)
3697 #define SR_ASM_SIZE_DIG_4389 (8192u * 8u)
3762 #define SR0_4388_SR_ENG_CLK_EN (1u << 1u)
3763 #define SR0_4388_RSRC_TRIGGER (0xCu << 2u)
3764 #define SR0_4388_WD_MEM_MIN_DIV (0x2u << 6u)
3765 #define SR0_4388_INVERT_SR_CLK (1u << 11u)
3766 #define SR0_4388_MEM_STBY_ALLOW (1u << 16u)
3767 #define SR0_4388_ENABLE_SR_ILP (1u << 17u)
3768 #define SR0_4388_ENABLE_SR_ALP (1u << 18u)
3769 #define SR0_4388_ENABLE_SR_HT (1u << 19u)
3770 #define SR0_4388_ALLOW_PIC (3u << 20u)
3771 #define SR0_4388_ENB_PMU_MEM_DISABLE (1u << 30u)
3792 #define SR1_SELFTEST_ERR_INJCT_PRD_SHIFT (16u)
3851 #define LHL4362_UP_CNT (0u)
3852 #define LHL4362_DN_CNT (2u)
3898 #define LHL4378_CSR_OVERI_DIS_DWN_CNT 5u
3899 #define LHL4378_CSR_MODE_DWN_CNT 5u
3900 #define LHL4378_CSR_ADJ_DWN_CNT 5u
3902 #define LHL4378_CSR_OVERI_DIS_UP_CNT 1u
3903 #define LHL4378_CSR_MODE_UP_CNT 1u
3904 #define LHL4378_CSR_ADJ_UP_CNT 1u
3906 #define LHL4378_VDDC_SW_DIS_DWN_CNT 3u
3907 #define LHL4378_ASR_ADJ_DWN_CNT 3u
3910 #define LHL4378_VDDC_SW_DIS_UP_CNT 3u
3911 #define LHL4378_ASR_ADJ_UP_CNT 1u
3914 #define LHL4378_ASR_MANUAL_MODE_DWN_CNT 5u
3915 #define LHL4378_ASR_MODE_SEL_DWN_CNT 5u
3916 #define LHL4378_ASR_LPPFM_MODE_DWN_CNT 5u
3919 #define LHL4378_ASR_MANUAL_MODE_UP_CNT 1u
3920 #define LHL4378_ASR_MODE_SEL_UP_CNT 1u
3921 #define LHL4378_ASR_LPPFM_MODE_UP_CNT 1u
3924 #define LHL4378_PFM_PWR_SLICE_DWN_CNT 5u
3925 #define LHL4378_ASR_OVERI_DIS_DWN_CNT 5u
3926 #define LHL4378_SRBG_REF_SEL_DWN_CNT 5u
3927 #define LHL4378_HPBG_PU_EN_DWN_CNT 6u
3929 #define LHL4378_PFM_PWR_SLICE_UP_CNT 1u
3930 #define LHL4378_ASR_OVERI_DIS_UP_CNT 1u
3931 #define LHL4378_SRBG_REF_SEL_UP_CNT 1u
3934 #define LHL4378_CSR_TRIM_ADJ_CNT_SHIFT (16u)
3939 #define LHL4378_ASR_TRIM_ADJ_CNT_SHIFT (0u)
3945 #define LHL4378_SLB_EN_DWN_CNT 2u
3946 #define LHL4378_ISO_EN_DWN_CNT 1u
3948 #define LHL4378_VMUX_ASR_SEL_DWN_CNT 4u
3950 #define LHL4378_PWRSW_EN_UP_CNT 6u
3951 #define LHL4378_SLB_EN_UP_CNT 4u
3952 #define LHL4378_ISO_EN_UP_CNT 5u
3954 #define LHL4378_VMUX_ASR_SEL_UP_CNT 2u
3956 #define LHL4387_VMUX_ASR_SEL_DWN_CNT (8u)
3960 #define LHL4387_TO_CSR_OVERI_DIS_DWN_CNT 3u
3961 #define LHL4387_TO_CSR_MODE_DWN_CNT 3u
3964 #define LHL4387_TO_CSR_OVERI_DIS_UP_CNT 1u
3965 #define LHL4387_TO_CSR_MODE_UP_CNT 1u
3968 #define LHL4387_TO_VDDC_SW_DIS_DWN_CNT 4u
3969 #define LHL4387_TO_ASR_ADJ_DWN_CNT 3u
3970 #define LHL4387_TO_LP_MODE_DWN_CNT 6u
3971 #define LHL4387_TO_HPBG_CHOP_DIS_DWN_CNT 3u
3974 #define LHL4387_TO_ASR_ADJ_UP_CNT 1u
3976 #define LHL4387_TO_HPBG_CHOP_DIS_UP_CNT 1u
3978 #define LHL4387_TO_ASR_MANUAL_MODE_DWN_CNT 3u
3979 #define LHL4387_TO_ASR_MODE_SEL_DWN_CNT 3u
3980 #define LHL4387_TO_ASR_LPPFM_MODE_DWN_CNT 3u
3981 #define LHL4387_TO_ASR_CLK4M_DIS_DWN_CNT 3u
3983 #define LHL4387_TO_ASR_MANUAL_MODE_UP_CNT 1u
3984 #define LHL4387_TO_ASR_MODE_SEL_UP_CNT 1u
3985 #define LHL4387_TO_ASR_LPPFM_MODE_UP_CNT 1u
3986 #define LHL4387_TO_ASR_CLK4M_DIS_UP_CNT 1u
3988 #define LHL4387_TO_PFM_PWR_SLICE_DWN_CNT 3u
3989 #define LHL4387_TO_ASR_OVERI_DIS_DWN_CNT 3u
3990 #define LHL4387_TO_SRBG_REF_SEL_DWN_CNT 3u
3991 #define LHL4387_TO_HPBG_PU_EN_DWN_CNT 4u
3993 #define LHL4387_TO_PFM_PWR_SLICE_UP_CNT 1u
3994 #define LHL4387_TO_ASR_OVERI_DIS_UP_CNT 1u
3995 #define LHL4387_TO_SRBG_REF_SEL_UP_CNT 1u
3996 #define LHL4387_TO_HPBG_PU_EN_UP_CNT 1u
3999 #define LHL4387_TO_SLB_EN_DWN_CNT 4u
4000 #define LHL4387_TO_ISO_EN_DWN_CNT 2u
4006 #define LHL4387_TO_TOP_SLP_EN_UP_CNT 2u
4029 #define PMU32_MAC_SCAN_RSRC_REQ_TIMER ((1u << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \
4030 (1u << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \
4031 (1u << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \
4032 (1u << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \
4033 (0u << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
4083 #define RES4362_DUMMY (0u)
4084 #define RES4362_ABUCK (1u)
4085 #define RES4362_PMU_SLEEP (2u)
4086 #define RES4362_MISCLDO_PU (3u)
4087 #define RES4362_LDO3P3_PU (4u)
4088 #define RES4362_FAST_LPO_AVAIL (5u)
4089 #define RES4362_XTAL_PU (6u)
4090 #define RES4362_XTAL_STABLE (7u)
4091 #define RES4362_PWRSW_DIG (8u)
4092 #define RES4362_SR_DIG (9u)
4093 #define RES4362_SLEEP_DIG (10u)
4094 #define RES4362_PWRSW_AUX (11u)
4095 #define RES4362_SR_AUX (12u)
4096 #define RES4362_SLEEP_AUX (13u)
4097 #define RES4362_PWRSW_MAIN (14u)
4098 #define RES4362_SR_MAIN (15u)
4099 #define RES4362_SLEEP_MAIN (16u)
4100 #define RES4362_DIG_CORE_RDY (17u)
4101 #define RES4362_CORE_RDY_AUX (18u)
4102 #define RES4362_ALP_AVAIL (19u)
4103 #define RES4362_RADIO_AUX_PU (20u)
4104 #define RES4362_MINIPMU_AUX_PU (21u)
4105 #define RES4362_CORE_RDY_MAIN (22u)
4106 #define RES4362_RADIO_MAIN_PU (23u)
4107 #define RES4362_MINIPMU_MAIN_PU (24u)
4108 #define RES4362_PCIE_EP_PU (25u)
4109 #define RES4362_COLD_START_WAIT (26u)
4110 #define RES4362_ARMHTAVAIL (27u)
4111 #define RES4362_HT_AVAIL (28u)
4112 #define RES4362_MACPHY_AUX_CLK_AVAIL (29u)
4113 #define RES4362_MACPHY_MAIN_CLK_AVAIL (30u)
4114 #define RES4362_RESERVED_31 (31u)
4207 #define SR0_43012_SR_ENG_EN_SHIFT 0u
4208 #define SR0_43012_SR_ENG_CLK_EN (1u << 1u)
4209 #define SR0_43012_SR_RSRC_TRIGGER (0xCu << 2u)
4210 #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3u << 6u)
4211 #define SR0_43012_SR_MEM_STBY_ALLOW_MSK (1u << 16u)
4212 #define SR0_43012_SR_MEM_STBY_ALLOW_SHIFT 16u
4213 #define SR0_43012_SR_ENABLE_ILP (1u << 17u)
4214 #define SR0_43012_SR_ENABLE_ALP (1u << 18u)
4215 #define SR0_43012_SR_ENABLE_HT (1u << 19u)
4216 #define SR0_43012_SR_ALLOW_PIC (3u << 20u)
4217 #define SR0_43012_SR_PMU_MEM_DISABLE (1u << 30u)
4218 #define CC_43012_VDDM_PWRSW_EN_MASK (1u << 20u)
4219 #define CC_43012_VDDM_PWRSW_EN_SHIFT (20u)
4220 #define CC_43012_SDIO_AOS_WAKEUP_MASK (1u << 24u)
4221 #define CC_43012_SDIO_AOS_WAKEUP_SHIFT (24u)
4229 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0u
4231 #define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10u
4233 #define PMU43012_PLL0_PC3_PDIV_SHIFT 10u
4234 #define PMU43012_PLL_NDIV_FRAC_BITS 20u
4235 #define PMU43012_PLL_P_DIV_SCALE_BITS 10u
4238 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0u
4240 #define CCTL_43012_ARM_ONCOUNT_SHIFT 2u
4251 #define PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF (1u << 12u)
4265 #define PMUCCTL05_43012_DISABLE_SPM_CLK (1u << 8u)
4266 #define PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN (1u << 14u)
4267 #define PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB (1u << 31u)
4269 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6u
4271 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18u
4273 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24u
4275 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12u
4277 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3u
4280 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_SHIFT 6u
4348 #define CC_PIN_GPIO_00 (0u)
4349 #define CC_PIN_GPIO_01 (1u)
4350 #define CC_PIN_GPIO_02 (2u)
4351 #define CC_PIN_GPIO_03 (3u)
4352 #define CC_PIN_GPIO_04 (4u)
4353 #define CC_PIN_GPIO_05 (5u)
4354 #define CC_PIN_GPIO_06 (6u)
4355 #define CC_PIN_GPIO_07 (7u)
4356 #define CC_PIN_GPIO_08 (8u)
4357 #define CC_PIN_GPIO_09 (9u)
4358 #define CC_PIN_GPIO_10 (10u)
4359 #define CC_PIN_GPIO_11 (11u)
4360 #define CC_PIN_GPIO_12 (12u)
4361 #define CC_PIN_GPIO_13 (13u)
4362 #define CC_PIN_GPIO_14 (14u)
4363 #define CC_PIN_GPIO_15 (15u)
4364 #define CC_PIN_GPIO_16 (16u)
4365 #define CC_PIN_GPIO_17 (17u)
4366 #define CC_PIN_GPIO_18 (18u)
4367 #define CC_PIN_GPIO_19 (19u)
4368 #define CC_PIN_GPIO_20 (20u)
4369 #define CC_PIN_GPIO_21 (21u)
4370 #define CC_PIN_GPIO_22 (22u)
4371 #define CC_PIN_GPIO_23 (23u)
4372 #define CC_PIN_GPIO_24 (24u)
4373 #define CC_PIN_GPIO_25 (25u)
4374 #define CC_PIN_GPIO_26 (26u)
4375 #define CC_PIN_GPIO_27 (27u)
4376 #define CC_PIN_GPIO_28 (28u)
4377 #define CC_PIN_GPIO_29 (29u)
4378 #define CC_PIN_GPIO_30 (30u)
4379 #define CC_PIN_GPIO_31 (31u)
4428 #define CC_GCI_04_4387C0_XTAL_PM_CLK (1u << 20u)
4430 #define CC_GCI_05_4387C0_AFE_RET_ENB_MASK (1u << 7u)
4432 #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_NBIT 2u
4434 #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_NBIT 11u
4435 #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_MASK 1u
4437 #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_NBIT 10u
4439 #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_NBIT 15u
4440 #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_MASK 1u
4441 #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_NBIT 26u
4444 #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_NBIT 10u
4447 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_NBIT 16u
4448 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_NBIT 17u
4449 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_NBIT 18u
4450 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_NBIT 19u
4451 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_NBIT 20u
4452 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_NBIT 21u
4453 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_NBIT 22u
4454 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_NBIT 23u
4455 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_NBIT 24u
4456 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_NBIT 25u
4457 #define CC_GCI_CHIPCTRL_23_LVM_MODE_DISABLE_NBIT 26u
4459 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_MASK (1u <<\
4461 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_MASK (1u <<\
4463 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_MASK (1u <<\
4465 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_MASK (1u <<\
4467 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_MASK (1u <<\
4469 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_MASK (1u <<\
4471 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_MASK (1u <<\
4473 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_MASK (1u <<\
4475 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_MASK (1u <<\
4477 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_MASK (1u <<\
4479 #define CC_GCI_CHIPCTRL_23_LVM_MODE_DISABLE_MASK (1u <<\
4488 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u)
4493 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_NBIT (5u)
4494 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u)
4495 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_NBIT (21u)
4510 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_NBIT (5u)
4522 #define CC_GCI_06_JTAG_SEL_SHIFT 4u
4523 #define CC_GCI_06_JTAG_SEL_MASK (1u << 4u)
4525 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00u) >> 8u)
4527 #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFFu << 8u)
4528 #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCCu << 8u)
4530 #define CC_GCI_13_INSUFF_TREFUP_FIX_SHIFT 31u
4534 #define CC_GCI_16_INSUFF_TREFUP_FIX_SHIFT 31u
4536 #define GPIO_CTRL_REG_DISABLE_INTERRUPT (3u << 9u)
4548 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_SHIFT (9u)
4550 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_SHIFT (10u)
4553 #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_SHIFT (10u)
4557 #define CC_GCI_20_BBPLL_CH_CTRL_GRP_SHIFT (26u)
4561 #define GCI_CC28_IHRP_SEL_SHIFT (24u)
4605 #define GCI6_AVS_ENAB 1u
4606 #define GCI6_AVS_ENAB_SHIFT 31u
4607 #define GCI6_AVS_ENAB_MASK (1u << GCI6_AVS_ENAB_SHIFT)
4608 #define GCI6_AVS_CBUCK_VOLT_SHIFT 25u
4633 #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT (3u)
4634 #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_MASK (1u << LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT)
4637 #define LHL_LP_CTL5_SPMI_DATA_SEL_SHIFT (8u)
4639 #define LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT (6u)
4641 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO0 (0u)
4642 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO1 (1u)
4643 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO2 (2u)
4731 #define PMU_EXT_WAKE_MASK_0_SDIO (1u << 2u)
4732 #define PMU_EXT_WAKE_MASK_0_PCIE_PERST (1u << 5u)
4734 #define PMU_4362_EXT_WAKE_MASK_0_SDIO (1u << 1u | 1u << 2u)
5212 #define CC_RNG_CTRL_0_RBG_EN_SHIFT (0u)
5215 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT (12u)
5224 #define CC_RNG_FIFO_COUNT_RFC_SHIFT (0u)
5228 #define CC_RNG_TOT_BITS_CNT_IRQ_SHIFT (0u)
5230 #define CC_RNG_TOT_BITS_MAX_IRQ_SHIFT (1u)
5232 #define CC_RNG_FIFO_FULL_IRQ_SHIFT (2u)
5234 #define CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT (3u)
5236 #define CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT (4u)
5238 #define CC_RNG_NIST_FAIL_IRQ_SHIFT (5u)
5240 #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_SHIFT (17u)
5243 #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_SHIFT (31u)
5248 #define PMU_CLEAR_FIS_DONE_SHIFT 1u
5249 #define PMU_CLEAR_FIS_DONE_MASK (1u << PMU_CLEAR_FIS_DONE_SHIFT)
5251 #define PMU_FIS_FORCEON_ALL_SHIFT 4u
5252 #define PMU_FIS_FORCEON_ALL_MASK (1u << PMU_FIS_FORCEON_ALL_SHIFT)
5254 #define PMU_FIS_DN_TIMER_VAL_SHIFT 16u
5261 #define PMU_FIS_PCIE_SAVE_EN_SHIFT 5u
5262 #define PMU_FIS_PCIE_SAVE_EN_VALUE (1u << PMU_FIS_PCIE_SAVE_EN_SHIFT)
5271 #define CC_ETBMEMCTRL_FORCETMCINTFTOETB_SHIFT 1u
5272 #define CC_ETBMEMCTRL_FORCETMCINTFTOETB_MASK (1u << CC_ETBMEMCTRL_FORCETMCINTFTOETB_SHIFT)
5276 #define BCM4387_SSSR_DUMP_MAIN_SIZE 160000u
5278 #define BCM4387_SSSR_DUMP_AUX_SIZE 160000u
5280 #define BCM4387_SSSR_DUMP_SCAN_SIZE 32768u