Lines Matching +full:0 +full:x1d000000
5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
40 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
55 uint32 pmucontrol; /* 0x600 */
56 uint32 pmucapabilities; /* 0x604 */
57 uint32 pmustatus; /* 0x608 */
58 uint32 res_state; /* 0x60C */
59 uint32 res_pending; /* 0x610 */
60 uint32 pmutimer; /* 0x614 */
61 uint32 min_res_mask; /* 0x618 */
62 uint32 max_res_mask; /* 0x61C */
63 uint32 res_table_sel; /* 0x620 */
69 uint32 gpiosel; /* 0x638, rev >= 1 */
70 uint32 gpioenable; /* 0x63c, rev >= 1 */
71 uint32 res_req_timer_sel; /* 0x640 */
72 uint32 res_req_timer; /* 0x644 */
73 uint32 res_req_mask; /* 0x648 */
74 uint32 core_cap_ext; /* 0x64C */
75 uint32 chipcontrol_addr; /* 0x650 */
76 uint32 chipcontrol_data; /* 0x654 */
81 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
82 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
83 uint32 retention_ctl; /* 0x670 */
84 uint32 ILPPeriod; /* 0x674 */
86 uint32 retention_grpidx; /* 0x680 */
87 uint32 retention_grpctl; /* 0x684 */
88 uint32 mac_res_req_timer; /* 0x688 */
89 uint32 mac_res_req_mask; /* 0x68c */
90 uint32 spm_ctrl; /* 0x690 */
91 uint32 spm_cap; /* 0x694 */
92 uint32 spm_clk_ctrl; /* 0x698 */
93 uint32 int_hi_status; /* 0x69c */
94 uint32 int_lo_status; /* 0x6a0 */
95 uint32 mon_table_addr; /* 0x6a4 */
96 uint32 mon_ctrl_n; /* 0x6a8 */
97 uint32 mon_status_n; /* 0x6ac */
98 uint32 int_treshold_n; /* 0x6b0 */
99 uint32 watermarks_n; /* 0x6b4 */
100 uint32 spm_debug; /* 0x6b8 */
102 uint32 vtrim_ctrl; /* 0x6c0 */
103 uint32 vtrim_status; /* 0x6c4 */
104 uint32 usec_timer; /* 0x6c8 */
105 uint32 usec_timer_frac; /* 0x6cc */
106 uint32 pcie_tpower_on; /* 0x6d0 */
107 uint32 pcie_tport_cnt; /* 0x6d4 */
108 uint32 pmucontrol_ext; /* 0x6d8 */
109 uint32 slowclkperiod; /* 0x6dc */
110 uint32 pmu_statstimer_addr; /* 0x6e0 */
111 uint32 pmu_statstimer_ctrl; /* 0x6e4 */
112 uint32 pmu_statstimer_N; /* 0x6e8 */
114 uint32 mac_res_req_timer1; /* 0x6f0 */
115 uint32 mac_res_req_mask1; /* 0x6f4 */
117 uint32 pmuintmask0; /* 0x700 */
118 uint32 pmuintmask1; /* 0x704 */
120 uint32 fis_start_min_res_mask; /* 0x710 */
122 uint32 rsrc_event0; /* 0x720 */
124 uint32 slowtimer2; /* 0x730 */
125 uint32 slowtimerfrac2; /* 0x734 */
126 uint32 mac_res_req_timer2; /* 0x738 */
127 uint32 mac_res_req_mask2; /* 0x73c */
128 uint32 pmuintstatus; /* 0x740 */
129 uint32 extwakeupstatus; /* 0x744 */
130 uint32 watchdog_res_mask; /* 0x748 */
131 uint32 PAD[1]; /* 0x74C */
132 uint32 swscratch; /* 0x750 */
133 uint32 PAD[3]; /* 0x754-0x75C */
134 uint32 extwakemask0; /* 0x760 */
135 uint32 extwakemask1; /* 0x764 */
136 uint32 PAD[2]; /* 0x768-0x76C */
137 uint32 extwakereqmask[2]; /* 0x770-0x774 */
138 uint32 PAD[2]; /* 0x778-0x77C */
139 uint32 pmuintctrl0; /* 0x780 */
140 uint32 pmuintctrl1; /* 0x784 */
142 uint32 extwakectrl[2]; /* 0x790 */
144 uint32 fis_ctrl_status; /* 0x7b4 */
145 uint32 fis_min_res_mask; /* 0x7b8 */
147 uint32 precision_tmr_ctrl_status; /* 0x7c0 */
148 uint32 precision_tmr_capture_low; /* 0x7c4 */
149 uint32 precision_tmr_capture_high; /* 0x7c8 */
150 uint32 precision_tmr_capture_frac; /* 0x7cc */
151 uint32 precision_tmr_running_low; /* 0x7d0 */
152 uint32 precision_tmr_running_high; /* 0x7d4 */
153 uint32 precision_tmr_running_frac; /* 0x7d8 */
155 uint32 core_cap_ext1; /* 0x7e8 */
157 uint32 rsrc_substate_ctl_sts; /* 0x800 */
158 uint32 rsrc_substate_trans_tmr; /* 0x804 */
160 uint32 dvfs_ctrl1; /* 0x810 */
161 uint32 dvfs_ctrl2; /* 0x814 */
162 uint32 dvfs_voltage; /* 0x818 */
163 uint32 dvfs_status; /* 0x81c */
164 uint32 dvfs_core_table_address; /* 0x820 */
165 uint32 dvfs_core_ctrl; /* 0x824 */
214 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */
219 uint32 chipid; /* 0x0 */
225 uint32 otpstatus; /* 0x10, corerev >= 10 */
231 uint32 intstatus; /* 0x20 */
235 uint32 chipcontrol; /* 0x28, rev >= 11 */
236 uint32 chipstatus; /* 0x2c, rev >= 11 */
239 uint32 jtagcmd; /* 0x30, rev >= 10 */
245 uint32 flashcontrol; /* 0x40 */
251 uint32 broadcastaddress; /* 0x50 */
255 uint32 gpiopullup; /* 0x58, corerev >= 20 */
256 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
257 uint32 gpioin; /* 0x60 */
258 uint32 gpioout; /* 0x64 */
259 uint32 gpioouten; /* 0x68 */
260 uint32 gpiocontrol; /* 0x6C */
261 uint32 gpiointpolarity; /* 0x70 */
262 uint32 gpiointmask; /* 0x74 */
269 uint32 watchdog; /* 0x80 */
275 uint32 gpiotimerval; /* 0x88 */ /* Obsolete and unused now */
279 uint32 clockcontrol_n; /* 0x90 */
286 uint32 capabilities_ext; /* 0xac */
289 uint32 pll_on_delay; /* 0xb0 */
295 uint32 system_clk_ctl; /* 0xc0 */
300 uint32 bp_addrlow; /* 0xd0 */
314 uint32 fabid; /* 0xf8 */
317 uint32 eromptr; /* 0xfc */
320 uint32 pcmcia_config; /* 0x100 */
332 uint32 SECI_config; /* 0x130 SECI configuration */
338 union { /* 0x140 */
351 uint32 sromcontrol; /* 0x190 */
354 uint32 PAD[1]; /* 0x19C */
356 uint32 nflashctrl; /* 0x1a0 */
361 uint32 nflashwaitcnt0; /* 0x1b4 */
364 uint32 seci_uart_data; /* 0x1C0 */
373 uint32 clk_ctl_st; /* 0x1e0 */
375 uint32 powerctl; /* 0x1e8 */
376 uint32 powerctl2; /* 0x1ec */
380 uint8 uart0data; /* 0x300 */
389 uint32 rng_ctrl_0; /* 0x3c0 */
390 uint32 rng_rng_soft_reset; /* 0x3c4 */
391 uint32 rng_rbg_soft_reset; /* 0x3c8 */
392 uint32 rng_total_bit_cnt; /* 0x3cc */
393 uint32 rng_total_bit_thrshld; /* 0x3d0 */
394 uint32 rng_rev_id; /* 0x3d4 */
395 uint32 rng_int_status_0; /* 0x3d8 */
396 uint32 rng_int_enable_0; /* 0x3dc */
397 uint32 rng_fifo_data; /* 0x3e0 */
398 uint32 rng_fifo_cnt; /* 0x3e4 */
401 uint8 uart1data; /* 0x400 */
408 uint8 uart1scratch; /* 0x407 */
410 uint32 sr_memrw_addr; /* 0x4d0 */
411 uint32 sr_memrw_data; /* 0x4d4 */
412 uint32 etbmemctrl; /* 0x4d8 */
416 uint32 sr_capability; /* 0x500 */
417 uint32 sr_control0; /* 0x504 */
418 uint32 sr_control1; /* 0x508 */
419 uint32 gpio_control; /* 0x50C */
422 uint32 sr1_control0; /* 0x584 */
423 uint32 sr1_control1; /* 0x588 */
429 uint32 pmucontrol; /* 0x600 */
443 uint32 gpiosel; /* 0x638, rev >= 1 */
444 uint32 gpioenable; /* 0x63c, rev >= 1 */
448 uint32 core_cap_ext; /* 0x64c */
449 uint32 chipcontrol_addr; /* 0x650 */
450 uint32 chipcontrol_data; /* 0x654 */
455 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
456 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
457 uint32 retention_ctl; /* 0x670 */
458 uint32 ILPPeriod; /* 0x674 */
460 uint32 retention_grpidx; /* 0x680 */
461 uint32 retention_grpctl; /* 0x684 */
462 uint32 mac_res_req_timer; /* 0x688 */
463 uint32 mac_res_req_mask; /* 0x68c */
465 uint32 pmucontrol_ext; /* 0x6d8 */
466 uint32 slowclkperiod; /* 0x6dc */
467 uint32 pmu_statstimer_addr; /* 0x6e0 */
468 uint32 pmu_statstimer_ctrl; /* 0x6e4 */
469 uint32 pmu_statstimer_N; /* 0x6e8 */
471 uint32 mac_res_req_timer1; /* 0x6f0 */
472 uint32 mac_res_req_mask1; /* 0x6f4 */
474 uint32 pmuintmask0; /* 0x700 */
475 uint32 pmuintmask1; /* 0x704 */
477 uint32 pmuintstatus; /* 0x740 */
478 uint32 extwakeupstatus; /* 0x744 */
480 uint32 extwakemask0; /* 0x760 */
481 uint32 extwakemask1; /* 0x764 */
482 uint32 PAD[2]; /* 0x768-0x76C */
483 uint32 extwakereqmask[2]; /* 0x770-0x774 */
484 uint32 PAD[2]; /* 0x778-0x77C */
485 uint32 pmuintctrl0; /* 0x780 */
486 uint32 PAD[3]; /* 0x784 - 0x78c */
487 uint32 extwakectrl[1]; /* 0x790 */
488 uint32 PAD[PADSZ(0x794u, 0x7b0u)]; /* 0x794 - 0x7b0 */
489 uint32 fis_ctrl_status; /* 0x7b4 */
490 uint32 fis_min_res_mask; /* 0x7b8 */
491 uint32 PAD[PADSZ(0x7bcu, 0x7bcu)]; /* 0x7bc */
492 uint32 precision_tmr_ctrl_status; /* 0x7c0 */
493 uint32 precision_tmr_capture_low; /* 0x7c4 */
494 uint32 precision_tmr_capture_high; /* 0x7c8 */
495 uint32 precision_tmr_capture_frac; /* 0x7cc */
496 uint32 precision_tmr_running_low; /* 0x7d0 */
497 uint32 precision_tmr_running_high; /* 0x7d4 */
498 uint32 precision_tmr_running_frac; /* 0x7d8 */
499 uint32 PAD[PADSZ(0x7dcu, 0x7e4u)]; /* 0x7dc - 0x7e4 */
500 uint32 core_cap_ext1; /* 0x7e8 */
501 uint32 PAD[PADSZ(0x7ecu, 0x7fcu)]; /* 0x7ec - 0x7fc */
503 uint16 sromotp[512]; /* 0x800 */
506 uint32 nand_revision; /* 0xC00 */
573 uint32 gci_corecaps0; /* GCI starting at 0xC00 */
577 uint32 gci_corestat; /* 0xC10 */
578 uint32 gci_intstat; /* 0xC14 */
579 uint32 gci_intmask; /* 0xC18 */
580 uint32 gci_wakemask; /* 0xC1C */
581 uint32 gci_levelintstat; /* 0xC20 */
582 uint32 gci_eventintstat; /* 0xC24 */
584 uint32 gci_indirect_addr; /* 0xC40 */
585 uint32 gci_gpioctl; /* 0xC44 */
587 uint32 gci_gpiomask; /* 0xC4C */
588 uint32 gci_eventsummary; /* 0xC50 */
589 uint32 gci_miscctl; /* 0xC54 */
595 uint32 gci_control_0; /* 0xD70 */
596 uint32 gci_control_1; /* 0xD74 */
597 uint32 gci_intpolreg; /* 0xD78 */
598 uint32 gci_levelintmask; /* 0xD7C */
599 uint32 gci_eventintmask; /* 0xD80 */
601 uint32 gci_inbandlevelintmask; /* 0xD90 */
602 uint32 gci_inbandeventintmask; /* 0xD94 */
604 uint32 gci_seciauxtx; /* 0xDA0 */
605 uint32 gci_seciauxrx; /* 0xDA4 */
606 uint32 gci_secitx_datatag; /* 0xDA8 */
607 uint32 gci_secirx_datatag; /* 0xDAC */
608 uint32 gci_secitx_datamask; /* 0xDB0 */
609 uint32 gci_seciusef0tx_reg; /* 0xDB4 */
610 uint32 gci_secif0tx_offset; /* 0xDB8 */
611 uint32 gci_secif0rx_offset; /* 0xDBC */
612 uint32 gci_secif1tx_offset; /* 0xDC0 */
613 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */
614 uint32 gci_rxfifoctrl; /* 0xDC8 */
628 uint32 gci_chipctrl; /* 0xE00 */
629 uint32 gci_chipsts; /* 0xE04 */
630 uint32 gci_gpioout; /* 0xE08 */
631 uint32 gci_gpioout_read; /* 0xE0C */
632 uint32 gci_mpwaketx; /* 0xE10 */
633 uint32 gci_mpwakedetect; /* 0xE14 */
634 uint32 gci_seciin_ctrl; /* 0xE18 */
635 uint32 gci_seciout_ctrl; /* 0xE1C */
636 uint32 gci_seciin_auxfifo_en; /* 0xE20 */
637 uint32 gci_seciout_txen_txbr; /* 0xE24 */
638 uint32 gci_seciin_rxbrstatus; /* 0xE28 */
639 uint32 gci_seciin_rxerrstatus; /* 0xE2C */
640 uint32 gci_seciin_fcstatus; /* 0xE30 */
641 uint32 gci_seciout_txstatus; /* 0xE34 */
642 uint32 gci_seciout_txbrstatus; /* 0xE38 */
649 #define CC_CHIPID 0
651 #define CC_CHIPST 0x2c
652 #define CC_EROMPTR 0xfc
655 #define CC_OTPST 0x10
656 #define CC_INTSTATUS 0x20
657 #define CC_INTMASK 0x24
658 #define CC_JTAGCMD 0x30
659 #define CC_JTAGIR 0x34
660 #define CC_JTAGDR 0x38
661 #define CC_JTAGCTRL 0x3c
662 #define CC_GPIOPU 0x58
663 #define CC_GPIOPD 0x5c
664 #define CC_GPIOIN 0x60
665 #define CC_GPIOOUT 0x64
666 #define CC_GPIOOUTEN 0x68
667 #define CC_GPIOCTRL 0x6c
668 #define CC_GPIOPOL 0x70
669 #define CC_GPIOINTM 0x74
670 #define CC_GPIOEVENT 0x78
671 #define CC_GPIOEVENTMASK 0x7c
672 #define CC_WATCHDOG 0x80
673 #define CC_GPIOEVENTPOL 0x84
674 #define CC_CLKC_N 0x90
675 #define CC_CLKC_M0 0x94
676 #define CC_CLKC_M1 0x98
677 #define CC_CLKC_M2 0x9c
678 #define CC_CLKC_M3 0xa0
679 #define CC_CLKDIV 0xa4
680 #define CC_CAP_EXT 0xac
681 #define CC_SYS_CLK_CTL 0xc0
682 #define CC_BP_ADRLOW 0xd0
683 #define CC_BP_ADRHI 0xd4
684 #define CC_BP_DATA 0xd8
687 #define CC_CLKDIV2 0xf0
689 #define PMU_CTL 0x600
690 #define PMU_CAP 0x604
691 #define PMU_ST 0x608
692 #define PMU_RES_STATE 0x60c
693 #define PMU_RES_PENDING 0x610
694 #define PMU_TIMER 0x614
695 #define PMU_MIN_RES_MASK 0x618
696 #define PMU_MAX_RES_MASK 0x61c
697 #define CC_CHIPCTL_ADDR 0x650
698 #define CC_CHIPCTL_DATA 0x654
699 #define PMU_REG_CONTROL_ADDR 0x658
700 #define PMU_REG_CONTROL_DATA 0x65C
701 #define PMU_PLL_CONTROL_ADDR 0x660
702 #define PMU_PLL_CONTROL_DATA 0x664
703 #define PMU_RSRC_CONTROL_MASK 0x7B0
705 #define CC_SROM_CTRL 0x190
706 #define CC_SROM_ADDRESS 0x194u
707 #define CC_SROM_DATA 0x198u
708 #define CC_SROM_OTP 0x0800
709 #define CC_GCI_INDIRECT_ADDR_REG 0xC40
710 #define CC_GCI_CHIP_CTRL_REG 0xE00
713 #define CC_SWD_CTRL 0x380
714 #define CC_SWD_REQACK 0x384
715 #define CC_SWD_DATA 0x388
716 #define GPIO_SEL_0 0x00001111
717 #define GPIO_SEL_1 0x11110000
718 #define GPIO_SEL_8 0x00001111
719 #define GPIO_SEL_9 0x11110000
721 #define CHIPCTRLREG0 0x0
722 #define CHIPCTRLREG1 0x1
723 #define CHIPCTRLREG2 0x2
724 #define CHIPCTRLREG3 0x3
725 #define CHIPCTRLREG4 0x4
726 #define CHIPCTRLREG5 0x5
727 #define CHIPCTRLREG6 0x6
728 #define CHIPCTRLREG13 0xd
729 #define CHIPCTRLREG16 0x10
730 #define REGCTRLREG4 0x4
731 #define REGCTRLREG5 0x5
732 #define REGCTRLREG6 0x6
733 #define MINRESMASKREG 0x618
734 #define MAXRESMASKREG 0x61c
735 #define CHIPCTRLADDR 0x650
736 #define CHIPCTRLDATA 0x654
737 #define RSRCTABLEADDR 0x620
738 #define PMU_RES_DEP_MASK 0x624
739 #define RSRCUPDWNTIME 0x628
740 #define PMUREG_RESREQ_MASK 0x68c
741 #define PMUREG_RESREQ_TIMER 0x688
742 #define PMUREG_RESREQ_MASK1 0x6f4
743 #define PMUREG_RESREQ_TIMER1 0x6f0
744 #define EXT_LPO_AVAIL 0x100
745 #define LPO_SEL (1 << 0)
746 #define CC_EXT_LPO_PU 0x200000
747 #define GC_EXT_LPO_PU 0x2
748 #define CC_INT_LPO_PU 0x100000
749 #define GC_INT_LPO_PU 0x1
750 #define EXT_LPO_SEL 0x8
751 #define INT_LPO_SEL 0x4
753 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000
755 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000
769 #define LHL_LPO1_SEL 0
770 #define LHL_LPO2_SEL 0x1
771 #define LHL_32k_SEL 0x2
772 #define LHL_EXT_SEL 0x3
774 #define EXTLPO_BUF_PD 0x40
775 #define LPO1_PD_EN 0x1
776 #define LPO1_PD_SEL 0x6
777 #define LPO1_PD_SEL_VAL 0x4
778 #define LPO2_PD_EN 0x8
779 #define LPO2_PD_SEL 0x30
780 #define LPO2_PD_SEL_VAL 0x20
781 #define OSC_32k_PD 0x80
783 #define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3
785 #define LHL_LPO_AUTO 0x0
786 #define LHL_LPO1_ENAB 0x1
787 #define LHL_LPO2_ENAB 0x2
788 #define LHL_OSC_32k_ENAB 0x3
789 #define LHL_EXT_LPO_ENAB 0x4
790 #define RADIO_LPO_ENAB 0x5
792 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4
793 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8
794 #define LHL_CLK_DET_CNT 0xF0
798 #define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000
799 #define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600
804 #define SUBCORE_POWER_ON 0x0001
805 #define PHY_POWER_ON 0x0010
806 #define VDDM_POWER_ON 0x0100
807 #define MEMLPLDO_POWER_ON 0x1000
808 #define SUBCORE_POWER_ON_CHK 0x00040000
809 #define PHY_POWER_ON_CHK 0x00080000
810 #define VDDM_POWER_ON_CHK 0x00100000
811 #define MEMLPLDO_POWER_ON_CHK 0x00200000
816 #define CC_NAND_REVISION 0xC00
817 #define CC_NAND_CMD_START 0xC04
818 #define CC_NAND_CMD_ADDR 0xC0C
819 #define CC_NAND_SPARE_RD_0 0xC20
820 #define CC_NAND_SPARE_RD_4 0xC24
821 #define CC_NAND_SPARE_RD_8 0xC28
822 #define CC_NAND_SPARE_RD_C 0xC2C
823 #define CC_NAND_CONFIG 0xC48
824 #define CC_NAND_DEVID 0xC60
825 #define CC_NAND_DEVID_EXT 0xC64
826 #define CC_NAND_INTFC_STATUS 0xC6C
830 #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */
831 #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */
833 #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */
835 #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */
837 #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */
841 #define CC_CAP_UARTS_MASK 0x00000003u /**< Number of UARTs */
842 #define CC_CAP_MIPSEB 0x00000004u /**< MIPS is in big-endian mode */
843 #define CC_CAP_UCLKSEL 0x00000018u /**< UARTs clock select */
844 #define CC_CAP_UINTCLK 0x00000008u /**< UARTs are driven by internal divided clock */
845 #define CC_CAP_UARTGPIO 0x00000020u /**< UARTs own GPIOs 15:12 */
846 #define CC_CAP_EXTBUS_MASK 0x000000c0u /**< External bus mask */
847 #define CC_CAP_EXTBUS_NONE 0x00000000u /**< No ExtBus present */
848 #define CC_CAP_EXTBUS_FULL 0x00000040u /**< ExtBus: PCMCIA, IDE & Prog */
849 #define CC_CAP_EXTBUS_PROG 0x00000080u /**< ExtBus: ProgIf only */
850 #define CC_CAP_FLASH_MASK 0x00000700u /**< Type of flash */
851 #define CC_CAP_PLL_MASK 0x00038000u /**< Type of PLL */
852 #define CC_CAP_PWR_CTL 0x00040000u /**< Power control */
853 #define CC_CAP_OTPSIZE 0x00380000u /**< OTP Size (0 = none) */
856 #define CC_CAP_JTAGP 0x00400000u /**< JTAG Master Present */
857 #define CC_CAP_ROM 0x00800000u /**< Internal boot rom active */
858 #define CC_CAP_BKPLN64 0x08000000u /**< 64-bit backplane */
859 #define CC_CAP_PMU 0x10000000u /**< PMU Present, rev >= 20 */
860 #define CC_CAP_ECI 0x20000000u /**< ECI Present, rev >= 21 */
861 #define CC_CAP_SROM 0x40000000u /**< Srom Present, rev >= 32 */
862 #define CC_CAP_NFLASH 0x80000000u /**< Nand flash present, rev >= 35 */
864 #define CC_CAP2_SECI 0x00000001u /**< SECI Present, rev >= 36 */
865 #define CC_CAP2_GSIO 0x00000002u /**< GSIO (spi/i2c) present, rev >= 37 */
868 #define CC_CAP_EXT_SECI_PRESENT 0x00000001u /**< SECI present */
869 #define CC_CAP_EXT_GSIO_PRESENT 0x00000002u /**< GSIO present */
870 #define CC_CAP_EXT_GCI_PRESENT 0x00000004u /**< GCI present */
871 #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008u /**< UART present */
872 #define CC_CAP_EXT_AOB_PRESENT 0x00000040u /**< AOB present */
873 #define CC_CAP_EXT_SWD_PRESENT 0x00000400u /**< SWD present */
874 #define CC_CAP_SR_AON_PRESENT 0x0001E000u /**< SWD present */
875 #define CC_CAP_EXT1_DVFS_PRESENT 0x00001000u /**< DVFS present */
879 #define CC_CAP_EXT1_CORE_CNT_MASK ((0x1Fu) << CC_CAP_EXT1_CORE_CNT_SHIFT)
881 /* SpmCtrl (Chipcommon Offset 0x690)
894 * Indicates whether the spm controller is running (SpmIdle=0) or in idle
895 * state (SpmIdle=1); Note that after setting Spmen=1 (or 0), it takes a
896 * few clock cycles (ILP or divided ALP) for SpmIdle to go to 0 (or 1).
909 * Bits 0 Spmen
910 * 0 - SPM disabled
916 #define SPMCTRL_ALPDIV_FUNC 0x1ffu
917 #define SPMCTRL_ALPDIV_RO 0xfffu
919 #define SPMCTRL_ALPDIV_MASK (0xfffu << SPMCTRL_ALPDIV_SHIFT)
920 #define SPMCTRL_RSTSPM 0x1u
922 #define SPMCTRL_RSTSPM_MASK (0x1u << SPMCTRL_RSTSPM_SHIFT)
923 #define SPMCTRL_USEDIVALP 0x1u
925 #define SPMCTRL_USEDIVALP_MASK (0x1u << SPMCTRL_USEDIVALP_SHIFT)
926 #define SPMCTRL_SPMEN 0x1u
927 #define SPMCTRL_SPMEN_SHIFT 0u
928 #define SPMCTRL_SPMEN_MASK (0x1u << SPMCTRL_SPMEN_SHIFT)
930 /* SpmClkCtrl (Chipcommon Offset 0x698)
932 * 0 means Take periodic measurements based on IntervalValue
941 * 0 - no divide
948 * 0 - no divide
951 #define SPMCLKCTRL_SAMPLETIME 0x2u
953 #define SPMCLKCTRL_SAMPLETIME_MASK (0xfu << SPMCLKCTRL_SAMPLETIME_SHIFT)
954 #define SPMCLKCTRL_ONESHOT 0x1u
956 #define SPMCLKCTRL_ONESHOT_MASK (0x1u << SPMCLKCTRL_ONESHOT_SHIFT)
958 /* MonCtrlN (Chipcommon Offset 0x6a8)
974 * Bits 0 MonEn
977 #define MONCTRLN_TARGETRO_PMU_ALP_CLK 0u
983 #define MONCTRLN_TARGETRO_MASK (0xffu << MONCTRLN_TARGETRO_SHIFT)
986 #define MONCTRLN_TARGETROEXT_RO 0x0u
987 #define MONCTRLN_TARGETROEXT_FUNC 0x2u
988 #define MONCTRLN_TARGETROEXT_DFT 0x3u
990 #define MONCTRLN_TARGETROEXT_MASK (0x3u << MONCTRLN_TARGETROEXT_SHIFT)
991 #define MONCTRLN_MONEN 0x1u
992 #define MONCTRLN_MONEN_SHIFT 0u
993 #define MONCTRLN_MONEN_MASK (0x1u << MONCTRLN_MONENEXT_SHIFT)
1002 * Bits 4:0 DVFS_RsrcTrig_PDn
1008 #define CTRLN_REQUEST_OVERRIDE_MASK (0x1u << CTRLN_REQUEST_OVERRIDE_SHIFT)
1010 #define CTRLN_REQUEST_VAL_MASK (0x3u << CTRLN_REQUEST_VAL_SHIFT)
1011 #define CTRLN_RSRC_TRIG_SHIFT 0u
1012 #define CTRLN_RSRC_TRIG_MASK (0x1Fu << CTRLN_RSRC_TRIG_SHIFT)
1013 #define CTRLN_RSRC_TRIG_CHIPC 0x1Au
1014 #define CTRLN_RSRC_TRIG_PCIE 0x1Au
1015 #define CTRLN_RSRC_TRIG_ARM 0x8u
1016 #define CTRLN_RSRC_TRIG_D11_MAIN 0xEu
1017 #define CTRLN_RSRC_TRIG_D11_AUX 0xBu
1018 #define CTRLN_RSRC_TRIG_D11_SCAN 0xCu
1019 #define CTRLN_RSRC_TRIG_HWA 0x8u
1020 #define CTRLN_RSRC_TRIG_BT_MAIN 0x9u
1021 #define CTRLN_RSRC_TRIG_BT_SCAN 0xAu
1024 #define DVFS_CORE_CHIPC 0u
1035 #define DVFS_CORE_MASK 0xFu
1037 #define DVFS_CORE_INVALID_IDX 0xFFu
1039 /* DVFS_Ctrl2 (PMU_BASE + 0x814)
1048 * Bits 7:0 Clock stable time
1053 #define DVFS_VOLTAGE_RAMP_DOWN_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT)
1056 #define DVFS_VOLTAGE_RAMP_UP_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT)
1059 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT)
1062 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT)
1064 #define DVFS_CLOCK_STABLE_TIME_SHIFT 0
1065 #define DVFS_CLOCK_STABLE_TIME_MASK (0xFFu << DVFS_CLOCK_STABLE_TIME_SHIFT)
1067 /* DVFS_Voltage (PMU_BASE + 0x818)
1072 * Bits 6:0 LDV Voltage
1075 #define DVFS_VOLTAGE_XDV 0u /* Reserved */
1085 #define DVFS_VOLTAGE_HDV_MASK (0x7Fu << DVFS_VOLTAGE_HDV_SHIFT)
1097 #define DVFS_VOLTAGE_NDV_MASK (0x7Fu << DVFS_VOLTAGE_NDV_SHIFT)
1104 #define DVFS_VOLTAGE_LDV_SHIFT 0u
1105 #define DVFS_VOLTAGE_LDV_MASK (0x7Fu << DVFS_VOLTAGE_LDV_SHIFT)
1107 /* DVFS_Status (PMU_BASE + 0x81C)
1114 * Bits 6:0 Dvfs Voltage
1118 #define DVFS_RAW_CORE_REQ_MASK (0x3u << DVFS_RAW_CORE_REQ_SHIFT)
1120 #define DVFS_ACT_CORE_REQ_MASK (0x3u << DVFS_ACT_CORE_REQ_SHIFT)
1122 #define DVFS_CORE_STATUS_MASK (0x3u << DVFS_CORE_STATUS_SHIFT)
1124 #define DVFS_CLK_SEL_MASK (0x3u << DVFS_CLK_SEL_SHIFT)
1125 #define DVFS_VOLTAGE_SHIFT 0u
1126 #define DVFS_VOLTAGE_MASK (0x7Fu << DVFS_VOLTAGE_SHIFT)
1128 /* DVFS_Ctrl1 (PMU_BASE + 0x810)
1129 * Bits 0 Enable DVFS
1134 #define DVFS_DISABLE_DVFS 0u
1136 #define DVFS_ENABLE_DVFS_SHIFT 0u
1152 #define DVFS_LDV 0u
1156 /* PowerControl2 (Core Offset 0x1EC)
1162 * Bits 1:0 DVFSRequest
1168 #define DVFS_REQ_SHIFT 0u
1169 #define DVFS_REQ_MASK (0x3u << DVFS_REQ_SHIFT)
1171 #define DVFS_STATUS_MASK (0x3u << DVFS_STATUS_SHIFT)
1174 * Bits 0 CB Clock sel
1175 * 0 - 160MHz
1178 #define GCI_CC16_CB_CLOCK_SEL_160 0u
1180 #define GCI_CC16_CB_CLOCK_SEL_SHIFT 0u
1181 #define GCI_CC16_CB_CLOCK_SEL_MASK (0x1u << GCI_CC16_CB_CLOCK_SEL_SHIFT)
1185 #define GCI_WL_CHN_INFO_MASK (0xFF00)
1187 #define GCI_WL_MCHAN_BIT_MASK (0x0010)
1191 #define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002)
1192 #define GCI_SWDIV_ANT_VALID_SHIFT 0x1
1193 #define GCI_SWDIV_ANT_VALID_DISABLE 0x0
1197 #define GCI_WL2BT_ACL_BSD_BLE_SCAN_GRNT_MASK 0x8000000
1202 #define GCI_WL2BT_2G_HIB_STATE_MASK (0x0040000u)
1206 #define GCI_WL2BT_TRAFFIC_IND_MASK (0x3 << GCI_WL2BT_TRAFFIC_IND_SHIFT)
1209 #define GCI_WL_STROBE_BIT_MASK (0x0020)
1213 #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT)
1214 #define GCI_WL_ANT_BIT_MASK (0x00c0)
1218 #define GCI_WL_RC2CX_PERCTS_MASK 0x00000100u
1221 #define PLL_NONE 0x00000000
1222 #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */
1223 #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */
1224 #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */
1225 #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */
1226 #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */
1227 #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */
1228 #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */
1262 #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */
1263 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */
1264 #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */
1265 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */
1266 #define CC_RBG_RESET 0x00000040 /**< Reset RBG block (corerev > = 65 */
1273 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */
1276 #define OTPS_OL_MASK 0x000000ff
1277 #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */
1278 #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */
1279 #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */
1280 #define OTPS_OL_GU 0x00000008 /**< general use region is locked */
1281 #define OTPS_GUP_MASK 0x00000f00
1283 #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */
1284 #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */
1285 #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */
1286 #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */
1287 #define OTPS_READY 0x00001000
1289 #define OTPS_RV_MASK 0x0fff0000
1290 #define OTPS_PROGOK 0x40000000
1293 #define OTPC_PROGSEL 0x00000001
1294 #define OTPC_PCOUNT_MASK 0x0000000e
1296 #define OTPC_VSEL_MASK 0x000000f0
1298 #define OTPC_TMM_MASK 0x00000700
1300 #define OTPC_ODM 0x00000800
1301 #define OTPC_PROGEN 0x80000000
1304 #define OTPC_40NM_PROGSEL_SHIFT 0
1306 #define OTPC_40NM_PCOUNT_WR 0xA
1307 #define OTPC_40NM_PCOUNT_V1X 0xB
1309 #define OTPC_40NM_REGCSEL_DEF 0x4
1315 #define OTPC_40NM_VSEL_WR 0xA
1316 #define OTPC_40NM_VSEL_V1X 0xA
1317 #define OTPC_40NM_VSEL_R1X 0x5
1320 #define OTPC1_CPCSEL_SHIFT 0
1323 #define OTPC1_TM_WR 0x84
1324 #define OTPC1_TM_V1X 0x84
1325 #define OTPC1_TM_R1X 0x4
1326 #define OTPC1_CLK_EN_MASK 0x00020000
1327 #define OTPC1_CLK_DIV_MASK 0x00FC0000
1330 #define OTPP_COL_MASK 0x000000ff
1331 #define OTPP_COL_SHIFT 0
1332 #define OTPP_ROW_MASK 0x0000ff00
1333 #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */
1335 #define OTPP_OC_MASK 0x0f000000
1337 #define OTPP_READERR 0x10000000
1338 #define OTPP_VALUE_MASK 0x20000000
1340 #define OTPP_START_BUSY 0x80000000
1341 #define OTPP_READ 0x40000000 /* HND OTP */
1344 #define OTPL_HWRGN_OFF_MASK 0x00000FFF
1345 #define OTPL_HWRGN_OFF_SHIFT 0
1346 #define OTPL_WRAP_REVID_MASK 0x00F80000
1348 #define OTPL_WRAP_TYPE_MASK 0x00070000
1350 #define OTPL_WRAP_TYPE_65NM 0
1355 #define OTPL_ROW_SIZE_MASK 0x0000F000
1359 #define OTP_CISFORMAT_NEW 0x80000000
1362 #define OTPPOC_READ 0
1373 #define OTPPOC_READ_40NM 0
1391 #define OTPPOC_READ_28NM 0
1422 #define OTPP_OC_MASK_28NM 0x0f800000
1426 #define OTPC_PROGEN_28NM 0x8
1427 #define OTPC_DBLERRCLR 0x20
1428 #define OTPC_CLK_EN_MASK 0x00000040
1429 #define OTPC_CLK_DIV_MASK 0x00000F80
1430 #define OTPC_FORCE_OTP_PWR_DIS 0x00008000
1433 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF
1441 #define JCMD_START 0x80000000
1442 #define JCMD_BUSY 0x80000000
1443 #define JCMD_STATE_MASK 0x60000000
1444 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */
1445 #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */
1446 #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */
1447 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */
1448 #define JCMD0_ACC_MASK 0x0000f000
1449 #define JCMD0_ACC_IRDR 0x00000000
1450 #define JCMD0_ACC_DR 0x00001000
1451 #define JCMD0_ACC_IR 0x00002000
1452 #define JCMD0_ACC_RESET 0x00003000
1453 #define JCMD0_ACC_IRPDR 0x00004000
1454 #define JCMD0_ACC_PDR 0x00005000
1455 #define JCMD0_IRW_MASK 0x00000f00
1456 #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */
1457 #define JCMD_ACC_IRDR 0x00000000
1458 #define JCMD_ACC_DR 0x00010000
1459 #define JCMD_ACC_IR 0x00020000
1460 #define JCMD_ACC_RESET 0x00030000
1461 #define JCMD_ACC_IRPDR 0x00040000
1462 #define JCMD_ACC_PDR 0x00050000
1463 #define JCMD_ACC_PIR 0x00060000
1464 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */
1465 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */
1466 #define JCMD_IRW_MASK 0x00001f00
1468 #define JCMD_DRW_MASK 0x0000003f
1474 #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */
1483 #define CLKD_SFLASH 0x1f000000
1485 #define CLKD_OTP 0x000f0000
1487 #define CLKD_JTAG 0x00000f00
1489 #define CLKD_UART 0x000000ff
1491 #define CLKD2_SROM 0x00000007
1492 #define CLKD2_SROMDIV_32 0
1500 #define CLKD2_SWD 0xf8000000
1504 #define CI_GPIO 0x00000001 /**< gpio intr */
1505 #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */
1506 #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */
1507 #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */
1508 #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */
1509 #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */
1510 #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */
1511 #define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */
1512 #define CI_SPMI 0x00100000 /* SPMI (corerev >= 65) */
1513 #define CI_RNG 0x00200000 /**< rng intr (corerev >= 65) */
1514 #define CI_SSRESET_F0 0x10000000 /**< ss reset occurred */
1515 #define CI_SSRESET_F1 0x20000000 /**< ss reset occurred */
1516 #define CI_SSRESET_F2 0x40000000 /**< ss reset occurred */
1517 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */
1520 #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */
1521 #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */
1522 #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */
1523 #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */
1524 #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */
1525 #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled,
1526 * 0: LPO is enabled
1528 #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock,
1529 * 0: power logic control
1531 #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors
1534 #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't
1537 #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */
1538 #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */
1542 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */
1543 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */
1544 #define SYCC_FP 0x00000004 /**< ForcePLLOn */
1545 #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */
1546 #define SYCC_HR 0x00000010 /**< Force HT */
1547 #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */
1552 #define WD_SSRESET_PCIE_F0_EN 0x10000000
1554 #define WD_SSRESET_PCIE_F1_EN 0x20000000
1555 #define WD_SSRESET_PCIE_F2_EN 0x40000000
1557 #define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000
1558 #define WD_COUNTER_MASK 0x0fffffff
1564 #define BPIA_BYTEEN 0x0000000f
1565 #define BPIA_SZ1 0x00000001
1566 #define BPIA_SZ2 0x00000003
1567 #define BPIA_SZ4 0x00000007
1568 #define BPIA_SZ8 0x0000000f
1569 #define BPIA_WRITE 0x00000100
1570 #define BPIA_START 0x00000200
1571 #define BPIA_BUSY 0x00000200
1572 #define BPIA_ERROR 0x00000400
1575 #define CF_EN 0x00000001 /**< enable */
1576 #define CF_EM_MASK 0x0000000e /**< mode */
1578 #define CF_EM_FLASH 0 /**< flash/asynchronous mode */
1581 #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */
1582 #define CF_BS 0x00000020 /**< byteswap */
1583 #define CF_CD_MASK 0x000000c0 /**< clock divider */
1585 #define CF_CD_DIV2 0x00000000 /**< backplane/2 */
1586 #define CF_CD_DIV3 0x00000040 /**< backplane/3 */
1587 #define CF_CD_DIV4 0x00000080 /**< backplane/4 */
1588 #define CF_CE 0x00000100 /**< clock enable */
1589 #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */
1592 #define PM_W0_MASK 0x0000003f /**< waitcount0 */
1593 #define PM_W1_MASK 0x00001f00 /**< waitcount1 */
1595 #define PM_W2_MASK 0x001f0000 /**< waitcount2 */
1597 #define PM_W3_MASK 0x1f000000 /**< waitcount3 */
1601 #define PA_W0_MASK 0x0000003f /**< waitcount0 */
1602 #define PA_W1_MASK 0x00001f00 /**< waitcount1 */
1604 #define PA_W2_MASK 0x001f0000 /**< waitcount2 */
1606 #define PA_W3_MASK 0x1f000000 /**< waitcount3 */
1610 #define PI_W0_MASK 0x0000003f /**< waitcount0 */
1611 #define PI_W1_MASK 0x00001f00 /**< waitcount1 */
1613 #define PI_W2_MASK 0x001f0000 /**< waitcount2 */
1615 #define PI_W3_MASK 0x1f000000 /**< waitcount3 */
1619 #define PW_W0_MASK 0x0000001f /**< waitcount0 */
1620 #define PW_W1_MASK 0x00001f00 /**< waitcount1 */
1622 #define PW_W2_MASK 0x001f0000 /**< waitcount2 */
1624 #define PW_W3_MASK 0x1f000000 /**< waitcount3 */
1627 #define PW_W0 0x0000000c
1628 #define PW_W1 0x00000a00
1629 #define PW_W2 0x00020000
1630 #define PW_W3 0x01000000
1633 #define FW_W0_MASK 0x0000003f /**< waitcount0 */
1634 #define FW_W1_MASK 0x00001f00 /**< waitcount1 */
1636 #define FW_W2_MASK 0x001f0000 /**< waitcount2 */
1638 #define FW_W3_MASK 0x1f000000 /**< waitcount3 */
1642 #define SRC_START 0x80000000
1643 #define SRC_BUSY 0x80000000
1644 #define SRC_OPCODE 0x60000000
1645 #define SRC_OP_READ 0x00000000
1646 #define SRC_OP_WRITE 0x20000000
1647 #define SRC_OP_WRDIS 0x40000000
1648 #define SRC_OP_WREN 0x60000000
1649 #define SRC_OTPSEL 0x00000010
1650 #define SRC_OTPPRESENT 0x00000020
1651 #define SRC_LOCK 0x00000008
1652 #define SRC_SIZE_MASK 0x00000006
1653 #define SRC_SIZE_1K 0x00000000
1654 #define SRC_SIZE_4K 0x00000002
1655 #define SRC_SIZE_16K 0x00000004
1657 #define SRC_PRESENT 0x00000001
1660 #define PCTL_ILP_DIV_MASK 0xffff0000
1662 #define PCTL_LQ_REQ_EN 0x00008000
1663 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */
1664 #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */
1665 #define PCTL_HT_REQ_EN 0x00000100
1666 #define PCTL_ALP_REQ_EN 0x00000080
1667 #define PCTL_XTALFREQ_MASK 0x0000007c
1669 #define PCTL_ILP_DIV_EN 0x00000002
1670 #define PCTL_LPO_SEL 0x00000001
1673 #define PCTL_EXT_FAST_TRANS_ENAB 0x00000001u
1674 #define PCTL_EXT_USE_LHL_TIMER 0x00000010u
1675 #define PCTL_EXT_FASTLPO_ENAB 0x00000080u
1676 #define PCTL_EXT_FASTLPO_SWENAB 0x00000200u
1677 #define PCTL_EXT_FASTSEQ_ENAB 0x00001000u
1678 #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000u /**< rev33 for FLL1M */
1679 #define PCTL_EXT_FASTLPO_SB_SWENAB 0x00008000u /**< rev36 for FLL1M */
1680 #define PCTL_EXT_REQ_MIRROR_ENAB 0x00010000u /**< rev36 for ReqMirrorEn */
1682 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77
1685 #define PMU_RCTL_CLK_DIV_SHIFT 0
1697 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0
1706 #define CSTRETCH_HT 0xffff0000
1707 #define CSTRETCH_ALP 0x0000ffff
1708 #define CSTRETCH_REDUCE_8 0x00080008
1715 #define CN_N1_MASK 0x3f /**< n1 control */
1716 #define CN_N2_MASK 0x3f00 /**< n2 control */
1718 #define CN_PLLC_MASK 0xf0000 /**< pll control */
1722 #define CC_M1_MASK 0x3f /**< m1 control */
1723 #define CC_M2_MASK 0x3f00 /**< m2 control */
1725 #define CC_M3_MASK 0x3f0000 /**< m3 control */
1727 #define CC_MC_MASK 0x1f000000 /**< mux control */
1731 #define CC_F6_2 0x02 /**< A factor of 2 in */
1732 #define CC_F6_3 0x03 /**< 6-bit fields like */
1733 #define CC_F6_4 0x05 /**< N1, M1 or M3 */
1734 #define CC_F6_5 0x09
1735 #define CC_F6_6 0x11
1736 #define CC_F6_7 0x21
1740 #define CC_MC_BYPASS 0x08
1741 #define CC_MC_M1 0x04
1742 #define CC_MC_M1M2 0x02
1743 #define CC_MC_M1M2M3 0x01
1744 #define CC_MC_M1M3 0x11
1756 #define CC_T6_M0 120000000 /**< sb clock for m = 0 */
1765 #define FLASH_NONE 0x000 /**< No flash */
1766 #define SFLASH_ST 0x100 /**< ST serial flash */
1767 #define SFLASH_AT 0x200 /**< Atmel serial flash */
1768 #define NFLASH 0x300 /**< NAND flash */
1769 #define PFLASH 0x700 /**< Parallel flash */
1770 #define QSPIFLASH_ST 0x800
1771 #define QSPIFLASH_AT 0x900
1774 #define CC_CFG_EN 0x0001 /**< Enable */
1775 #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */
1776 #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */
1777 #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */
1778 #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */
1779 #define CC_CFG_EM_IDE 0x0006 /**< IDE */
1780 #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */
1781 #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */
1782 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */
1783 #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */
1784 #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */
1787 #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */
1788 #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */
1789 #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */
1790 #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */
1791 #define CC_EB_IDE 0x1a800000 /**< IDE memory base */
1792 #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */
1793 #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */
1794 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */
1795 #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */
1798 #define SFLASH_OPCODE 0x000000ff
1799 #define SFLASH_ACTION 0x00000700
1800 #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */
1801 #define SFLASH_START 0x80000000
1805 #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */
1806 #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */
1807 #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */
1808 #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */
1809 #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */
1810 #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */
1811 #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */
1814 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */
1815 #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */
1816 #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */
1817 #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */
1818 #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */
1819 #define SFLASH_ST_PP 0x0302 /**< Page Program */
1820 #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */
1821 #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */
1822 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */
1823 #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */
1824 #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */
1825 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */
1827 #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */
1828 #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */
1829 #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */
1830 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */
1832 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */
1833 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */
1835 #define SFLASH_WINBOND_RDID 0x0390 /* Read Manufacture ID */
1836 #define SFLASH_WINBOND_MFID 0xef /* Winbond Manufacture ID */
1839 #define SFLASH_ST_WIP 0x01 /**< Write In Progress */
1840 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */
1841 #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */
1843 #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */
1846 #define SFLASH_AT_READ 0x07e8
1847 #define SFLASH_AT_PAGE_READ 0x07d2
1851 #define SFLASH_AT_STATUS 0x01d7
1852 #define SFLASH_AT_BUF1_WRITE 0x0384
1853 #define SFLASH_AT_BUF2_WRITE 0x0387
1854 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
1855 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
1856 #define SFLASH_AT_BUF1_PROGRAM 0x0288
1857 #define SFLASH_AT_BUF2_PROGRAM 0x0289
1858 #define SFLASH_AT_PAGE_ERASE 0x0281
1859 #define SFLASH_AT_BLOCK_ERASE 0x0250
1860 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
1861 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
1862 #define SFLASH_AT_BUF1_LOAD 0x0253
1863 #define SFLASH_AT_BUF2_LOAD 0x0255
1864 #define SFLASH_AT_BUF1_COMPARE 0x0260
1865 #define SFLASH_AT_BUF2_COMPARE 0x0261
1866 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
1867 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
1870 #define SFLASH_AT_READY 0x80
1871 #define SFLASH_AT_MISMATCH 0x40
1872 #define SFLASH_AT_ID_MASK 0x38
1876 #define GSIO_START 0x80000000u
1880 #define MUXENAB_DEF_UART_MASK 0x0000000fu
1881 #define MUXENAB_DEF_UART_SHIFT 0
1884 #define MUXENAB_DEF_HOSTWAKE_MASK 0x000000f0u /**< configure GPIO for host_wake */
1888 #define MUXENAB_GCI_UART_MASK 0x00000f00u
1890 #define MUXENAB_GCI_UART_FNSEL_MASK 0x00003000u
1903 #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */
1904 #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */
1905 #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */
1906 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */
1915 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */
1916 #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */
1917 #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */
1918 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */
1919 #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */
1920 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */
1921 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */
1922 #define UART_LSR_BREAK 0x10 /**< Break interrupt */
1923 #define UART_LSR_FRAMING 0x08 /**< Framing error */
1924 #define UART_LSR_PARITY 0x04 /**< Parity error */
1925 #define UART_LSR_OVERRUN 0x02 /**< Overrun error */
1926 #define UART_LSR_RXRDY 0x01 /**< Receiver ready */
1930 #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */
1931 #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */
1932 #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */
1933 #define UART_IIR_NOINT 0x1 /**< No interrupt pending */
1934 #define UART_IIR_THRE 0x2 /**< THR empty */
1935 #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */
1936 #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */
1937 #define UART_IIR_CHAR_TIME 0xc /**< Character time */
1947 #define PST_SLOW_WR_PENDING 0x0400
1948 #define PST_EXTLPOAVAIL 0x0100
1949 #define PST_WDRESET 0x0080
1950 #define PST_INTPEND 0x0040
1951 #define PST_SBCLKST 0x0030
1952 #define PST_SBCLKST_ILP 0x0010
1953 #define PST_SBCLKST_ALP 0x0020
1954 #define PST_SBCLKST_HT 0x0030
1955 #define PST_ALPAVAIL 0x0008
1956 #define PST_HTAVAIL 0x0004
1957 #define PST_RESINIT 0x0003
1958 #define PST_ILPFASTLPO 0x00010000
1961 #define PCAP_REV_MASK 0x000000ff
1962 #define PCAP_RC_MASK 0x00001f00
1964 #define PCAP_TC_MASK 0x0001e000
1966 #define PCAP_PC_MASK 0x001e0000
1968 #define PCAP_VC_MASK 0x01e00000
1970 #define PCAP_CC_MASK 0x1e000000
1972 #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */
1974 #define PCAP5_VC_MASK 0x07c00000
1976 #define PCAP5_CC_MASK 0xf8000000
1981 #define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT)
1983 #define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT)
1990 #define PMU_ST_SRC_SHIFT (0) /* stat timer source number */
1991 #define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT)
1993 #define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT)
1995 #define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT)
1997 #define PMU_ST_DISAB 0
1999 #define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT)
2001 #define PMU_ST_INT_DISAB 0
2004 #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000
2008 #define PRRT_TIME_MASK 0x03ff
2009 #define PRRT_INTEN 0x0400
2014 #define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */
2015 #define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */
2016 #define PRRT_ALP_REQ 0x1000
2017 #define PRRT_HT_REQ 0x2000
2018 #define PRRT_HQ_REQ 0x4000
2021 #define PMU_INTC_ALP_REQ 0x1
2022 #define PMU_INTC_HT_REQ 0x2
2023 #define PMU_INTC_HQ_REQ 0x4
2025 /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */
2049 #define PMU_CHIPCTL0 0
2051 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0)
2052 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0)
2053 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6)
2054 #define PMU_CC0_4369B0_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6)
2055 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6)
2056 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12)
2057 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12)
2058 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15)
2059 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15)
2062 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20u << 0u)
2064 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3Fu << 0u)
2065 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1Au << 6u)
2066 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3Fu << 6u)
2067 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_VAL (0x00u << 12u)
2068 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_MASK (0x07u << 12u)
2069 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_VAL (0x02u << 15u)
2070 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_MASK (0x07u << 15u)
2072 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0)
2073 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0)
2074 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6)
2075 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6)
2076 #define PMU_CC0_4378_XTAL_RES_BYPASS_START_VAL (0 << 12)
2077 #define PMU_CC0_4378_XTAL_RES_BYPASS_START_MASK (0x7 << 12)
2078 #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15)
2079 #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15)
2081 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0)
2082 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0)
2083 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6)
2084 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6)
2085 #define PMU_CC0_4387_XTAL_RES_BYPASS_START_VAL (0 << 12)
2086 #define PMU_CC0_4387_XTAL_RES_BYPASS_START_MASK (0x7 << 12)
2087 #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15)
2088 #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15)
2089 #define PMU_CC0_4387_BT_PU_WAKE_MASK (0x3u << 30u)
2095 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
2105 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000
2106 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010
2108 #define PMU_CC1_IF_TYPE_MASK 0x00000030
2109 #define PMU_CC1_IF_TYPE_RMII 0x00000000
2110 #define PMU_CC1_IF_TYPE_MII 0x00000010
2111 #define PMU_CC1_IF_TYPE_RGMII 0x00000020
2113 #define PMU_CC1_SW_TYPE_MASK 0x000000c0
2114 #define PMU_CC1_SW_TYPE_EPHY 0x00000000
2115 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
2116 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
2117 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0
2119 #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080
2120 #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000
2122 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u
2124 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00002000u
2126 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u
2132 #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000u
2144 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2145 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2146 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2147 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2149 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2150 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2151 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2152 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2154 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2155 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2156 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2157 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2159 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u)
2160 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u)
2161 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u)
2162 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u)
2170 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u)
2171 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u)
2172 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u)
2173 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u)
2174 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u)
2175 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u)
2176 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21)
2177 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21)
2178 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2u << 12u)
2179 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7u << 12u)
2180 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x2u << 27u)
2181 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7u << 27u)
2183 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u)
2184 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u)
2185 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u)
2186 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u)
2187 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u)
2188 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u)
2189 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21u)
2190 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21u)
2191 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_VAL (0x02u << 12u)
2192 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_MASK (0x07u << 12u)
2194 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_VAL (0x02u << 27u)
2195 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_MASK (0x07u << 27u)
2197 #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_VAL (0x3F << 0)
2198 #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_MASK (0x3F << 0)
2199 #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15)
2200 #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15)
2201 #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_VAL (0x3F << 6)
2202 #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_MASK (0x3F << 6)
2203 #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21)
2204 #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21)
2205 #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_VAL (0x2 << 12)
2206 #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_MASK (0x7 << 12)
2207 #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_VAL (0x2 << 27)
2208 #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27)
2210 #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_VAL (0x3F << 0)
2211 #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_MASK (0x3F << 0)
2212 #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15)
2213 #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15)
2214 #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_VAL (0x3F << 6)
2215 #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_MASK (0x3F << 6)
2216 #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21)
2217 #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21)
2218 #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_VAL (0x2 << 12)
2219 #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_MASK (0x7 << 12)
2220 #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_VAL (0x5 << 27)
2221 #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27)
2227 #define PMU_CC4_IF_TYPE_MASK 0x00003000
2228 #define PMU_CC4_IF_TYPE_RMII 0x00000000
2229 #define PMU_CC4_IF_TYPE_MII 0x00001000
2230 #define PMU_CC4_IF_TYPE_RGMII 0x00002000
2232 #define PMU_CC4_SW_TYPE_MASK 0x0000c000
2233 #define PMU_CC4_SW_TYPE_EPHY 0x00000000
2234 #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000
2235 #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000
2236 #define PMU_CC4_SW_TYPE_RGMII 0x0000c000
2305 #define PMU_CC6_RX4_CLK_SEQ_SELECT_MASK BCM_MASK32(1u, 0u)
2318 /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */
2319 #define PMU_CC7_IF_TYPE_MASK 0x000000c0
2320 #define PMU_CC7_IF_TYPE_RMII 0x00000000
2321 #define PMU_CC7_IF_TYPE_MII 0x00000040
2322 #define PMU_CC7_IF_TYPE_RGMII 0x00000080
2328 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0
2329 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff
2331 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00
2333 #define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000
2335 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000
2343 #define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0
2346 #define PMU_CC10_PCIE_RESET0_CNT_SLOW_MASK (0xFu << 4u)
2347 #define PMU_CC10_PCIE_RESET1_CNT_SLOW_MASK (0xFu << 12u)
2358 #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u)
2406 #define SCAN_DIG_SR_CLK_80_MHZ (0) /* 80 MHz */
2434 #define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF)
2435 #define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4)
2436 #define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8)
2437 #define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12)
2438 #define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16)
2439 #define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20)
2442 #define PMU_CC15_PCIE_VDDB_CURRENT_LIMIT_DELAY_MASK (0xFu << 4u)
2443 #define PMU_CC15_PCIE_VDDB_FORCE_RPS_PWROK_DELAY_MASK (0xFu << 8u)
2451 #define PMU0_PLL0_PLLCTL0 0
2454 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
2459 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
2470 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
2472 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
2474 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
2478 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
2483 #define PMU1_PLL0_PLLCTL0 0
2484 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
2486 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
2491 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
2492 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
2493 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
2495 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
2497 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
2500 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
2501 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
2502 #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C
2503 #define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00
2504 #define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28
2507 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
2508 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
2512 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
2513 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
2514 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
2515 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
2516 #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f
2517 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
2518 #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a
2519 #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c
2520 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
2522 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
2523 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24
2524 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
2528 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
2533 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
2534 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
2541 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
2543 #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000
2545 #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000
2564 #define PMU2_PLL_PLLCTL0 0
2565 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
2567 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
2572 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
2573 #define PMU2_PLL_PC1_M1DIV_SHIFT 0
2574 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
2576 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
2578 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
2583 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
2584 #define PMU2_PLL_PC2_M5DIV_SHIFT 0
2585 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
2587 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
2589 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
2594 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
2595 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
2602 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
2604 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
2606 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
2608 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
2610 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
2612 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
2616 #define PMU5_PLL_P1P2_OFF 0
2617 #define PMU5_PLL_P1_MASK 0x0f000000
2619 #define PMU5_PLL_P2_MASK 0x00f00000
2622 #define PMU5_PLL_MDIV_MASK 0x000000ff
2625 #define PMU5_PLL_NDIV_MASK 0xfff00000
2627 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
2630 #define PMU5_PLL_MRAT_MASK 0xf0000000
2632 #define PMU5_PLL_ABRAT_MASK 0x08000000
2634 #define PMU5_PLL_FDIV_MASK 0x07ffffff
2637 #define PMU5_PLL_PCHI_MASK 0x0000003f
2640 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
2641 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
2650 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
2653 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc
2654 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18
2656 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff
2657 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0
2659 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc
2660 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18
2661 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00
2663 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc
2664 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18
2666 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00
2667 #define PMU7_PLL_PLLCTL11_VAL 0x22222200
2670 #define PMU15_PLL_PLLCTL0 0
2671 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
2672 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0
2673 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
2675 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
2677 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
2679 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
2681 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
2683 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
2687 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060
2689 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040
2691 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80
2693 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000
2695 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000
2697 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000
2699 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000
2703 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001
2704 #define PMU15_PLL_PC2_CTEN_SHIFT 0
2707 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001
2708 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0
2709 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000
2711 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01
2712 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0
2713 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02
2715 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04
2717 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18
2719 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60
2721 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0
2727 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007
2728 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0
2729 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038
2731 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0
2733 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00
2735 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000
2737 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000
2739 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000
2741 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000
2743 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000
2745 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000
2747 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000
2749 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000
2751 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000
2755 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF
2756 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0
2757 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000
2759 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000
2763 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF
2764 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0
2765 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000
2767 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000
2770 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1
2771 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5
2776 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070
2779 #define PMU17_PLLCTL2_NDIV_MODE_INT 0
2784 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0
2792 #define PMU4368_P1DIV_LO_SHIFT 0
2795 #define PMU4368_PLL1_PC4_P1DIV_MASK 0xC0000000
2797 #define PMU4368_PLL1_PC5_P1DIV_MASK 0x00000003
2798 #define PMU4368_PLL1_PC5_P1DIV_SHIFT 0
2799 #define PMU4368_PLL1_PC5_NDIV_INT_MASK 0x00000ffc
2801 #define PMU4368_PLL1_PC5_NDIV_FRAC_MASK 0xfffff000
2805 #define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000
2807 #define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
2809 #define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff
2810 #define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0
2811 #define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000
2813 #define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003
2814 #define PMU4369_PLL1_PC6_P1DIV_SHIFT 0
2815 #define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc
2817 #define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000
2820 #define PMU4369_P1DIV_LO_SHIFT 0
2831 #define PMU4378_PLL0_PC2_P1DIV_MASK 0x000f0000
2833 #define PMU4378_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
2838 #define PMU4387_PLL0_PC1_ICH2_MDIV_MASK 0x07FC0000
2839 #define PMU4387_PLL0_PC2_ICH3_MDIV_MASK 0x000001ff
2842 #define PMU4388_APLL_NDIV_P 0x154u
2843 #define PMU4388_APLL_NDIV_Q 0x1ffu
2844 #define PMU4388_APLL_PDIV 0x3u
2845 #define PMU4388_ARMPLL_I_NDIV_INT_MASK 0x01ff8000u
2849 #define PMU4389_APLL_NDIV_P 0x154u
2850 #define PMU4389_APLL_NDIV_Q 0x1ffu
2851 #define PMU4389_APLL_PDIV 0x3u
2852 #define PMU4389_ARMPLL_I_NDIV_INT_MASK 0x01ff8000u
2863 #define PMU1_PLL0_CHIPCTL0 0
2867 #define SOCDEVRAM_BP_ADDR 0x1E000000
2868 #define SOCDEVRAM_ARM_ADDR 0x00800000
2870 #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0
2874 #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F
2876 #define PMU_VREG0_RAMP_SEL_MASK 0x7
2883 #define PMU_VREG4_CLDO_PWM_MASK 0x7
2886 #define PMU_VREG4_LPLDO1_MASK 0x7
2887 #define PMU_VREG4_LPLDO1_1p20V 0
2897 #define PMU_VREG4_LPLDO2_LVM_MASK 0x7
2899 #define PMU_VREG4_LPLDO2_HVM_MASK 0x7
2900 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f
2901 #define PMU_VREG4_LPLDO2_1p00V 0
2908 #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1
2912 #define PMU_VREG5_HSICAVDD_PD_MASK 0x1
2914 #define PMU_VREG5_HSICDVDD_PD_MASK 0x1
2917 #define CST43228_OTP_PRESENT 0x2
2921 #define CCTRL4360_I2C_MODE (1 << 0)
2938 #define RES4360_REGULATOR 0
2950 #define CST4360_XTAL_40MZ 0x00000001
2951 #define CST4360_SFLASH 0x00000002
2952 #define CST4360_SPROM_PRESENT 0x00000004
2953 #define CST4360_SFLASH_TYPE 0x00000004
2954 #define CST4360_OTP_ENABLED 0x00000008
2955 #define CST4360_REMAP_ROM 0x00000010
2956 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060
2958 #define CST4360_ILP_DIVEN 0x00000080
2959 #define CST4360_MODE_USB 0x00000100
2960 #define CST4360_SPROM_SIZE_MASK 0x00000600
2962 #define CST4360_BBPLL_LOCK 0x00000800
2963 #define CST4360_AVBBPLL_LOCK 0x00001000
2964 #define CST4360_USBBBPLL_LOCK 0x00002000
2968 #define CCTRL_4360_UART_SEL 0x2
2976 #define RES43602_LPLDO_PU 0
3006 #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */
3018 #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */
3020 #define CC_SR1_43602_SR_ASM_ADDR (0x0)
3023 #define PMU43602_PLL_CTL6_VAL 0x68000528
3024 #define PMU43602_PLL_CTL7_VAL 0x6
3028 #define CC_SR0_43602_SR_ENG_EN_MASK 0x1
3029 #define CC_SR0_43602_SR_ENG_EN_SHIFT 0
3032 #define CC_FNSEL_HWDEF (0u)
3055 #define PMU_VREG_0 (0u)
3078 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03
3079 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490
3080 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03
3081 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410
3084 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07
3085 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF
3107 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
3108 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u
3120 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
3121 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u
3146 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
3147 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT (0u)
3165 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
3166 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_SHIFT (0u)
3174 #define VREG0_4378_CSR_VOLT_ADJ_PWM_MASK 0x00001F00u
3176 #define VREG0_4378_CSR_VOLT_ADJ_PFM_MASK 0x0003E000u
3178 #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_MASK 0x007C0000u
3180 #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_MASK 0x07800000u
3184 #define PMU_4387_VREG6_WL_PMU_LV_MODE_MASK (0x00000002u)
3185 #define PMU_4387_VREG6_MEMLDO_PU_MASK (0x00000008u)
3198 #define PMU_VREG13_ASR_OVADJ_PWM_MASK (0x001F0000u)
3204 #define CSR_VOLT_ADJ_PWM_4378 (0x17u)
3205 #define CSR_VOLT_ADJ_PFM_4378 (0x17u)
3206 #define CSR_VOLT_ADJ_LP_PFM_4378 (0x17u)
3207 #define CSR_OUT_VOLT_TRIM_ADJ_4378 (0xEu)
3214 #define ABUCK_VOLT_SW_DEFAULT_4387 (0x1Fu) /* 1.00V */
3215 #define CBUCK_VOLT_SW_DEFAULT_4387 (0xFu) /* 0.68V */
3216 #define CBUCK_VOLT_NON_LVM (0x13u) /* 0.76V */
3219 #define CC_GCI1_REG (0x1)
3222 #define FORCE_CLK_OFF 0
3224 #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0)
3236 #define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10)
3239 #define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12)
3240 #define PMU_4387_VREG6_BTLDO3P3_PU (0x1 << 8)
3249 #define RES4369_DUMMY 0
3284 #define RES4378_DUMMY 0
3320 #define RES4387_DUMMY 0
3358 #define RES4388_DUMMY 0u
3392 #define RES4389_DUMMY 0u
3426 #define RES4397_DUMMY 0u
3459 /* 0: BToverPCIe, 1: BToverUART */
3460 #define CST4378_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0)
3461 #define CST4378_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0)
3462 #define CST4378_SPROM_PRESENT 0x00000010
3464 #define CST4387_SFLASH_PRESENT 0x00000010U
3466 #define CST4387_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0)
3467 #define CST4387_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0)
3468 #define CST4387_SPROM_PRESENT 0x00000010
3475 #define GCI_CS_4387_FLL1MHZ_DAC_OUT_MASK (0x00ff0000u)
3477 #define GCI_CS_4389_FLL1MHZ_DAC_OUT_MASK (0x00ff0000u)
3485 #define GCI_CC12_PRISEL_MASK (1 << 0 | 1 << 1)
3486 #define GCI_CC12_PRISEL_SHIFT 0
3487 #define GCI_CC12_DMASK_MASK (0x3ff << 10)
3505 #define CC4_4378_LHL_TIMER_SELECT (1u << 0u)
3528 #define CC4_4387_LHL_TIMER_SELECT (1u << 0u)
3551 #define CC4_4388_LHL_TIMER_SELECT (1u << 0u)
3574 #define CC4_4389_LHL_TIMER_SELECT (1u << 0u)
3589 #define VREG5_4378_MEMLPLDO_ADJ_MASK 0xF0000000
3591 #define VREG5_4378_LPLDO_ADJ_MASK 0x00F00000
3594 #define VREG5_4387_MISCLDO_PU_MASK (0x00000800u)
3597 #define VREG5_4387_MEMLPLDO_ADJ_MASK 0xF0000000
3599 #define VREG5_4387_LPLDO_ADJ_MASK 0x00F00000
3601 #define VREG5_4387_MISC_LDO_ADJ_MASK (0xfu)
3602 #define VREG5_4387_MISC_LDO_ADJ_SHIFT (0)
3607 #define PMU_VREG5_MISC_LDO_VOLT_0p931 (0x7u) /* 0.93125 v */
3608 #define PMU_VREG5_MISC_LDO_VOLT_0p912 (0x6u) /* 0.91250 v */
3609 #define PMU_VREG5_MISC_LDO_VOLT_0p893 (0x5u) /* 0.89375 v */
3610 #define PMU_VREG5_MISC_LDO_VOLT_0p875 (0x4u) /* 0.87500 v */
3611 #define PMU_VREG5_MISC_LDO_VOLT_0p856 (0x3u) /* 0.85625 v */
3612 #define PMU_VREG5_MISC_LDO_VOLT_0p837 (0x2u) /* 0.83750 v */
3613 #define PMU_VREG5_MISC_LDO_VOLT_0p818 (0x1u) /* 0.81875 v */
3614 #define PMU_VREG5_MISC_LDO_VOLT_0p800 (0) /* 0.80000 v */
3615 #define PMU_VREG5_MISC_LDO_VOLT_0p781 (0xfu) /* 0.78125 v */
3616 #define PMU_VREG5_MISC_LDO_VOLT_0p762 (0xeu) /* 0.76250 v */
3617 #define PMU_VREG5_MISC_LDO_VOLT_0p743 (0xdu) /* 0.74375 v */
3618 #define PMU_VREG5_MISC_LDO_VOLT_0p725 (0xcu) /* 0.72500 v */
3619 #define PMU_VREG5_MISC_LDO_VOLT_0p706 (0xbu) /* 0.70625 v */
3620 #define PMU_VREG5_MISC_LDO_VOLT_0p687 (0xau) /* 0.68750 v */
3621 #define PMU_VREG5_MISC_LDO_VOLT_0p668 (0x9u) /* 0.66875 v */
3622 #define PMU_VREG5_MISC_LDO_VOLT_0p650 (0x8u) /* 0.65000 v */
3625 #define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */
3626 #define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */
3627 #define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */
3628 #define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */
3629 #define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */
3630 #define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */
3631 #define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */
3632 #define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */
3633 #define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */
3634 #define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */
3635 #define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */
3636 #define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */
3637 #define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */
3638 #define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */
3639 #define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */
3640 #define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */
3651 * We use first 12kB (0x3000) in BMC buffer for template in main core and
3652 * 6.5kB (0x1A00) in aux core, followed by ASM code
3654 #define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00)
3655 #define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00)
3656 #define SR_ASM_ADDR_DIG_4369 (0x0)
3658 #define SR_ASM_ADDR_MAIN_4362 BM_ADDR_TO_SR_ADDR(0xc00u)
3659 #define SR_ASM_ADDR_DIG_4362 (0x0u)
3661 #define SR_ASM_ADDR_MAIN_4378 (0x18)
3662 #define SR_ASM_ADDR_AUX_4378 (0xd)
3664 #define SR_ASM_ADDR_DIG_4378A0 (0x51c000)
3667 #define SR_ASM_ADDR_DIG_4378B0 (0x518000)
3669 #define SR_ASM_ADDR_MAIN_4387 (0x18)
3670 #define SR_ASM_ADDR_AUX_4387 (0xd)
3671 #define SR_ASM_ADDR_SCAN_4387 (0)
3673 #define SR_ASM_ADDR_DIG_4387 (0x800000)
3675 #define SR_ASM_ADDR_MAIN_4387C0 BM_ADDR_TO_SR_ADDR(0xC00)
3676 #define SR_ASM_ADDR_AUX_4387C0 BM_ADDR_TO_SR_ADDR(0xC00)
3677 #define SR_ASM_ADDR_DIG_4387C0 (0x931000)
3678 #define SR_ASM_ADDR_DIG_4387_C0 (0x931000)
3680 #define SR_ASM_ADDR_MAIN_4388 BM_ADDR_TO_SR_ADDR(0xC00)
3681 #define SR_ASM_ADDR_AUX_4388 BM_ADDR_TO_SR_ADDR(0xC00)
3682 #define SR_ASM_ADDR_SCAN_4388 BM_ADDR_TO_SR_ADDR(0)
3683 #define SR_ASM_ADDR_DIG_4388 (0x18520000)
3685 #define FIS_CMN_SUBCORE_ADDR_4388 (0x1640u)
3687 #define SR_ASM_ADDR_MAIN_4389C0 BM_ADDR_TO_SR_ADDR(0xC00)
3688 #define SR_ASM_ADDR_AUX_4389C0 BM_ADDR_TO_SR_ADDR(0xC00)
3689 #define SR_ASM_ADDR_SCAN_4389C0 BM_ADDR_TO_SR_ADDR(0x000)
3690 #define SR_ASM_ADDR_DIG_4389C0 (0x18520000)
3693 #define SR_ASM_ADDR_MAIN_4389 BM_ADDR_TO_SR_ADDR(0xC00)
3694 #define SR_ASM_ADDR_AUX_4389 BM_ADDR_TO_SR_ADDR(0xC00)
3695 #define SR_ASM_ADDR_SCAN_4389 BM_ADDR_TO_SR_ADDR(0x000)
3696 #define SR_ASM_ADDR_DIG_4389 (0x18520000)
3698 #define FIS_CMN_SUBCORE_ADDR_4389 (0x1640u)
3700 #define SR_ASM_ADDR_DIG_4397 (0x18520000)
3703 #define SR0_SR_ENG_EN_MASK 0x1
3704 #define SR0_SR_ENG_EN_SHIFT 0
3706 #define SR0_RSRC_TRIGGER (0xC << 2)
3707 #define SR0_WD_MEM_MIN_DIV (0x3 << 6)
3717 #define SR0_4369_SR_ENG_EN_MASK 0x1
3718 #define SR0_4369_SR_ENG_EN_SHIFT 0
3720 #define SR0_4369_RSRC_TRIGGER (0xC << 2)
3721 #define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6)
3731 #define SR0_4378_SR_ENG_EN_MASK 0x1
3732 #define SR0_4378_SR_ENG_EN_SHIFT 0
3734 #define SR0_4378_RSRC_TRIGGER (0xC << 2)
3735 #define SR0_4378_WD_MEM_MIN_DIV (0x2 << 6)
3745 #define SR0_4387_SR_ENG_EN_MASK 0x1
3746 #define SR0_4387_SR_ENG_EN_SHIFT 0
3748 #define SR0_4387_RSRC_TRIGGER (0xC << 2)
3749 #define SR0_4387_WD_MEM_MIN_DIV (0x2 << 6)
3750 #define SR0_4387_WD_MEM_MIN_DIV_AUX (0x4 << 6)
3760 #define SR0_4388_SR_ENG_EN_MASK 0x1u
3761 #define SR0_4388_SR_ENG_EN_SHIFT 0
3763 #define SR0_4388_RSRC_TRIGGER (0xCu << 2u)
3764 #define SR0_4388_WD_MEM_MIN_DIV (0x2u << 6u)
3774 #define SR0_4389_SR_ENG_EN_MASK 0x1
3775 #define SR0_4389_SR_ENG_EN_SHIFT 0
3777 #define SR0_4389_RSRC_TRIGGER (0xC << 2)
3778 #define SR0_4389_WD_MEM_MIN_DIV (0x2 << 6)
3788 #define SR1_INIT_ADDR_MASK (0x000003FFu)
3789 #define SR1_SELFTEST_ENB_MASK (0x00004000u)
3790 #define SR1_SELFTEST_ERR_INJCT_ENB_MASK (0x00008000u)
3791 #define SR1_SELFTEST_ERR_INJCT_PRD_MASK (0xFFFF0000u)
3795 #define SR2_INIT_ADDR_LONG_MASK (0x00003FFFu)
3797 #define SR_SELFTEST_ERR_INJCT_PRD (0x10u)
3800 #define SR_STS1_SR_ERR_MASK (0x00000001u)
3804 #define LHL4369_UP_CNT 0
3851 #define LHL4362_UP_CNT (0u)
3908 #define LHL4378_HPBG_CHOP_DIS_DWN_CNT 0
3912 #define LHL4378_HPBG_CHOP_DIS_UP_CNT 0
3917 #define LHL4378_ASR_CLK4M_DIS_DWN_CNT 0
3922 #define LHL4378_ASR_CLK4M_DIS_UP_CNT 0
3932 #define LHL4378_HPBG_PU_EN_UP_CNT 0
3935 #define LHL4378_CSR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT)
3936 #define LHL4378_CSR_TRIM_ADJ_DWN_CNT 0
3937 #define LHL4378_CSR_TRIM_ADJ_UP_CNT 0
3939 #define LHL4378_ASR_TRIM_ADJ_CNT_SHIFT (0u)
3940 #define LHL4378_ASR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)
3941 #define LHL4378_ASR_TRIM_ADJ_UP_CNT 0
3942 #define LHL4378_ASR_TRIM_ADJ_DWN_CNT 0
3944 #define LHL4378_PWRSW_EN_DWN_CNT 0
3957 #define LHL4387_VMUX_ASR_SEL_UP_CNT (0x14u)
3962 #define LHL4387_TO_CSR_ADJ_DWN_CNT 0
3966 #define LHL4387_TO_CSR_ADJ_UP_CNT 0
3973 #define LHL4387_TO_VDDC_SW_DIS_UP_CNT 0
3975 #define LHL4387_TO_LP_MODE_UP_CNT 0
3998 #define LHL4387_TO_PWRSW_EN_DWN_CNT 0
4001 #define LHL4387_TO_TOP_SLP_EN_DWN_CNT 0
4003 #define LHL4387_TO_PWRSW_EN_UP_CNT 0x16u
4004 #define LHL4387_TO_SLB_EN_UP_CNT 0xeu
4005 #define LHL4387_TO_ISO_EN_UP_CNT 0x10u
4020 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
4026 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
4033 (0u << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
4036 * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls
4038 #define RES4369_DUMMY 0
4071 #define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
4072 #define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
4073 #define CST4369_SPROM_PRESENT 0x00000010
4075 #define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF
4076 #define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647
4083 #define RES4362_DUMMY (0u)
4116 #define CST4362_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
4117 #define CST4362_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
4118 #define CST4362_SPROM_PRESENT (0x00000010u)
4120 #define PMU_4362_MACCORE_0_RES_REQ_MASK (0x3FCBF7FFu)
4121 #define PMU_4362_MACCORE_1_RES_REQ_MASK (0x7FFB3647u)
4123 #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000
4124 #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F
4126 #define PMU43012_MAC_RES_REQ_TIMER 0x1D000000
4127 #define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF
4129 #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000
4130 #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F
4133 #define CHIP_HOSTIF_PCIEMODE 0x1
4134 #define CHIP_HOSTIF_USBMODE 0x2
4135 #define CHIP_HOSTIF_SDIOMODE 0x4
4140 #define PATCHTBL_SIZE (0x800)
4141 #define CR4_4335_RAM_BASE (0x180000)
4142 #define CR4_4345_LT_C0_RAM_BASE (0x1b0000)
4143 #define CR4_4345_GE_C0_RAM_BASE (0x198000)
4144 #define CR4_4349_RAM_BASE (0x180000)
4145 #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000)
4146 #define CR4_4350_RAM_BASE (0x180000)
4147 #define CR4_4360_RAM_BASE (0x0)
4148 #define CR4_43602_RAM_BASE (0x180000)
4150 #define CR4_4347_RAM_BASE (0x170000)
4151 #define CR4_4362_RAM_BASE (0x170000)
4152 #define CR4_4364_RAM_BASE (0x160000)
4153 #define CR4_4369_RAM_BASE (0x170000)
4154 #define CR4_4377_RAM_BASE (0x170000)
4155 #define CR4_43751_RAM_BASE (0x170000)
4156 #define CR4_43752_RAM_BASE (0x170000)
4157 #define CR4_4376_RAM_BASE (0x352000)
4158 #define CR4_4378_RAM_BASE (0x352000)
4159 #define CR4_4387_RAM_BASE (0x740000)
4160 #define CR4_4385_RAM_BASE (0x740000)
4161 #define CA7_4388_RAM_BASE (0x200000)
4162 #define CA7_4389_RAM_BASE (0x200000)
4163 #define CA7_4385_RAM_BASE (0x200000)
4166 * the memory space allows 192KB (0x1850_0000 - 0x1852_FFFF)
4168 #define HWA_MEM_BASE_4388 (0x18520000u)
4169 #define HWA_MEM_SIZE_4388 (0x10000u)
4172 #define RES43012_MEMLPLDO_PU 0
4203 #define CST43012_SPROM_PRESENT 0x00000010
4206 #define SR0_43012_SR_ENG_EN_MASK 0x1u
4207 #define SR0_43012_SR_ENG_EN_SHIFT 0u
4209 #define SR0_43012_SR_RSRC_TRIGGER (0xCu << 2u)
4210 #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3u << 6u)
4224 #define SR1_43012_SR_INIT_ADDR_MASK 0x3ffu
4225 #define SR1_43012_SR_ASM_ADDR 0xAu
4228 #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003fu
4229 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0u
4230 #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00u
4232 #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00u
4237 #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003u
4238 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0u
4239 #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000cu
4243 #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000u
4246 #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010u
4247 #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040u
4248 #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800u
4249 #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000u
4250 #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000u
4253 #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000u
4254 #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000u
4255 #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000u
4256 #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000u
4257 #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000u
4258 #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000u
4259 #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000u
4260 #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000u
4261 #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000u
4262 #define PMUCCTL04_43012_USE_LOCK 0x20000000u
4263 #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000u
4264 #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000u
4268 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0u
4270 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000u
4272 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000u
4274 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000u
4276 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038u
4279 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0u
4282 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1Fu
4284 #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400
4286 #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001
4287 #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020
4288 #define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080
4289 #define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200
4290 #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400
4291 #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000
4292 #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000
4293 #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000
4294 #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000
4296 #define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000
4299 #define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0
4302 #define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000
4306 #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000
4308 #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F
4310 #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000
4312 #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F
4314 #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000
4316 #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0
4318 #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0
4320 #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5
4322 #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000
4324 #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_VAL 0x7
4327 #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000
4329 #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F
4331 #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000
4333 #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F
4335 #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000
4337 #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0
4339 #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0
4341 #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5
4343 #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000
4345 #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_VAL 0x7
4348 #define CC_PIN_GPIO_00 (0u)
4385 #define CC_GCI_CHIPCTRL_00 (0)
4419 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12)
4422 #define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */
4433 #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_MASK 0xFu
4438 #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_MASK 0x1Fu
4442 #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_MASK 0x3Fu
4445 #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_MASK 0x7u
4482 /* 2G core0/core1 Pulse width register (offset : 0x47C)
4483 * wl_rx_long_pulse_width_2g_core0 [4:0];
4489 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu)
4490 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\
4497 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu)
4498 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\
4500 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu <<\
4502 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\
4505 /* 5G core0/Core1 (offset : 0x480)
4506 * wl_rx_long_pulse_width_5g[4:0];
4512 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_5G_MASK (0x1Fu)
4513 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_MASK (0x1Fu <<\
4516 #define CC_GCI_CNCB_GLITCH_FILTER_WIDTH_MASK (0xFFu)
4518 #define CC_GCI_RESET_OVERRIDE_NBIT 0x1u
4519 #define CC_GCI_RESET_OVERRIDE_MASK (0x1u << \
4525 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00u) >> 8u)
4527 #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFFu << 8u)
4528 #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCCu << 8u)
4543 #define XTAL_HQ_SETTING_4387 (0xFFF94D30u)
4544 #define XTAL_LQ_SETTING_4387 (0xFFF94380u)
4547 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_MASK (0x00000200u)
4549 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_MASK (0xFFFFFC00u)
4552 #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_MASK (0x0000FC00u)
4554 #define CC_GCI_17_BBPLL_CH_CTRL_EN_MASK (0x04000000u)
4556 #define CC_GCI_20_BBPLL_CH_CTRL_GRP_MASK (0xFC000000u)
4566 #define GRP_PD_TRIGGER_MASK_4387 (0x60d44800u)
4569 #define GRP_PD_MASK_4387 (0x25u)
4571 #define CC_GCI_CHIPCTRL_11_2x2_ANT_MASK 0x03
4575 #define GCI_CHIPSTATUS_00 (0)
4595 #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */
4609 #define GCI6_AVS_CBUCK_VOLT_MASK (0x1Fu << GCI6_AVS_CBUCK_VOLT_SHIFT)
4611 /* GCI GPIO for function sel GCI-0/GCI-1 */
4612 #define CC_GCI_GPIO_0 (0)
4630 #define CC_GCI_GPIO_INVALID 0xFF
4638 #define LHL_LP_CTL5_SPMI_DATA_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_DATA_SHIFT)
4640 #define LHL_LP_CTL5_SPMI_CLK_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT)
4641 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO0 (0u)
4647 #define GCIMASK(pos) (((uint32)0xF) << pos)
4651 #define GCIGETNBL(val, pos) ((val >> pos) & 0xF)
4654 #define GCIMASK_8B(pos) (((uint32)0xFF) << pos)
4658 #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF)
4661 #define GCIMASK_4B(pos) (((uint32)0xF) << pos)
4665 #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF)
4668 #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */
4686 #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */
4704 #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */
4737 #define LHL_PWRSEQCTL_SLEEP_EN (1 << 0)
4769 #define LHL_PWRSEQ_CTL (0x000000ff)
4771 /* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78)
4774 #define LHL_PWRUP_ISOLATION_CNT (0x6 << 8)
4775 #define LHL_PWRUP_RETENTION_CNT (0x5 << 16)
4776 #define LHL_PWRUP_PWRSW_CNT (0x7 << 24)
4780 #define LHL_PWRUP_CTL_MASK (0x3F3F3F00)
4785 #define LHL_PWRUP2_CLDO_DN_CNT (0x0)
4786 #define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8)
4787 #define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16)
4788 #define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24)
4789 #define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F)
4795 /* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */
4796 #define LHL_PWRDN_SLEEP_CNT (0x4)
4797 #define LHL_PWRDN_CTL_MASK (0x3F)
4799 /* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */
4800 #define LHL_PWRDN2_CLDO_DN_CNT (0x4)
4801 #define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8)
4802 #define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16)
4803 #define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24)
4808 #define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F)
4812 #define LHL_WL_MACTIMER_MASK 0xFFFFFFFF
4814 #define LHL_WL_MACTIMER_INT_ST_MASK (0x1u)
4817 #define LHL_WL_ARMTIM0_INTRP_EN 0x00000001
4818 #define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002
4821 #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001
4824 #define LHL_WL_MACTIM_INTRP_EN 0x00000001
4825 #define LHL_WL_MACTIM_INTRP_EDGE_TRIGGER 0x00000002
4828 #define LHL_WL_MACTIM_ST_WL_MACTIM_INT_ST 0x00000001
4831 #define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000
4833 #define LHL_PS_MODE_0 0
4837 #define GCI_MAILBOXDATA_TOWLAN (1 << 0)
4855 #define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0)
4859 #define MUXENAB43012_HOSTWAKE_MASK (0x00000001)
4880 /* Fields in eci_inputlo register - [0:31] */
4881 #define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */
4882 #define ECI_INLO_TASKTYPE_SHIFT 0
4883 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
4885 #define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */
4887 #define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */
4889 #define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */
4891 #define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */
4893 #define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */
4898 * - BT packet type information bits [7:0]
4900 /* [3:0] - Task (link) type */
4901 #define BT_ACL 0x00
4902 #define BT_SCO 0x01
4903 #define BT_eSCO 0x02
4904 #define BT_A2DP 0x03
4905 #define BT_SNIFF 0x04
4906 #define BT_PAGE_SCAN 0x05
4907 #define BT_INQUIRY_SCAN 0x06
4908 #define BT_PAGE 0x07
4909 #define BT_INQUIRY 0x08
4910 #define BT_MSS 0x09
4911 #define BT_PARK 0x0a
4912 #define BT_RSSISCAN 0x0b
4913 #define BT_MD_ACL 0x0c
4914 #define BT_MD_eSCO 0x0d
4915 #define BT_SCAN_WITH_SCO_LINK 0x0e
4916 #define BT_SCAN_WITHOUT_SCO_LINK 0x0f
4919 #define BT_MASTER 0
4922 #define BT_LOWEST_PRIO 0x0
4923 #define BT_HIGHEST_PRIO 0x3
4932 /* Fields in eci_output register - [0:31] */
4933 #define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000
4934 #define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000))
4935 #define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12)
4936 #define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00))
4938 #define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100))
4941 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80))
4944 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40))
4948 * 0 => FW control, 1=> MAC/ucode control
4951 * 0 - TxConf (ucode)
4959 * 15:0 - wl
4966 #define ECI_MACCTRL_BITS 0xbffb0000
4967 #define ECI_MACCTRLLO_BITS 0x1
4968 #define ECI_MACCTRLHI_BITS 0xFF
4972 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
4973 #define SECI_STAT_BI (1 << 0) /* Break Interrupt */
4988 #define SECI_MODE_UART 0x0
4989 #define SECI_MODE_SECI 0x1
4990 #define SECI_MODE_LEGACY_3WIRE_BT 0x2
4991 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3
4992 #define SECI_MODE_HALF_SECI 0x4
4994 #define SECI_RESET (1 << 0)
4998 #define SECI_MODE_MASK 0x7
5003 #define SECI_SLIP_ESC_CHAR 0xDB
5005 #define SECI_SIGNOFF_1 0
5006 #define SECI_REFRESH_REQ 0xDA
5013 #define SECI_UART_MSR_CTS_STATE (1 << 0)
5019 #define GCI_RXF_LVL_MASK (0xFF << 0)
5020 #define GCI_RXF_TIMEOUT_MASK (0xFF << 8)
5024 #define SECI_TXF_LVL_MASK (0x3F << 8)
5025 #define TXF_AE_LVL_DEFAULT 0x4
5026 #define SECI_RXF_LVL_FC_MASK (0x3F << 16)
5029 #define SECI_UART_FCR_RFR (1 << 0)
5040 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
5042 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
5054 #define SECI_UART_MCR_TX_EN (1 << 0)
5065 #define SECI_UART_LSR_RXOVR_MASK (1 << 0)
5073 #define SECI_UART_MSR_CTSS_MASK (1 << 0)
5082 #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF
5090 #define LTECX_MUX_MODE_IDX 0
5091 #define LTECX_MUX_MODE_WCI2 0x0
5092 #define LTECX_MUX_MODE_GPIO 0x1
5095 #define LTECX_NVRAM_FSYNC_IDX 0
5101 #define LTECX_NVRAM_WCI2IN_IDX 0
5112 #define ECI_BW_20 0x0
5113 #define ECI_BW_25 0x1
5114 #define ECI_BW_30 0x2
5115 #define ECI_BW_35 0x3
5116 #define ECI_BW_40 0x4
5117 #define ECI_BW_45 0x5
5118 #define ECI_BW_50 0x6
5119 #define ECI_BW_ALL 0x7
5125 /* otpctrl1 0xF4 */
5126 #define OTPC_FORCE_PWR_OFF 0x02000000
5128 #define CC_SR_CTL0_ENABLE_MASK 0x1
5129 #define CC_SR_CTL0_ENABLE_SHIFT 0
5131 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */
5140 #define CC_SR_CTL1_SR_INIT_MASK 0x3FF
5141 #define CC_SR_CTL1_SR_INIT_SHIFT 0
5143 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
5147 #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0
5157 #define GCI_GPIO_STS_VALUE_BIT 0
5161 #define GCI_GPIO_STS_CLEAR 0xF
5163 #define GCI_GPIO_STS_EDGE_TRIG_BIT 0
5171 #define SRPWR_DMN0_PCIE (0) /* PCIE */
5199 #define SRPWR_BT_STATUS_MASK (0x3)
5202 #define SRPWR_DMN_ID_MASK (0xF)
5207 #define PMU_PREC_USEC_TIMER_ENABLE 0x1
5210 #define MASK_1BIT(offset) (0x1u << offset)
5212 #define CC_RNG_CTRL_0_RBG_EN_SHIFT (0u)
5213 #define CC_RNG_CTRL_0_RBG_EN_MASK (0x1FFFu << CC_RNG_CTRL_0_RBG_EN_SHIFT)
5214 #define CC_RNG_CTRL_0_RBG_EN (0x1FFFu)
5216 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_MASK (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT)
5217 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_1MHz (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT)
5218 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_2MHz (0x2u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT)
5219 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_4MHz (0x1u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT)
5220 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_8MHz (0x0u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT)
5224 #define CC_RNG_FIFO_COUNT_RFC_SHIFT (0u)
5225 #define CC_RNG_FIFO_COUNT_RFC_MASK (0xFFu << CC_RNG_FIFO_COUNT_RFC_SHIFT)
5228 #define CC_RNG_TOT_BITS_CNT_IRQ_SHIFT (0u)
5229 #define CC_RNG_TOT_BITS_CNT_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_CNT_IRQ_SHIFT)
5231 #define CC_RNG_TOT_BITS_MAX_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_MAX_IRQ_SHIFT)
5233 #define CC_RNG_FIFO_FULL_IRQ_MASK (0x1u << CC_RNG_FIFO_FULL_IRQ_SHIFT)
5235 #define CC_RNG_FIFO_OVER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT)
5237 #define CC_RNG_FIFO_UNDER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT)
5239 #define CC_RNG_NIST_FAIL_IRQ_MASK (0x1u << CC_RNG_NIST_FAIL_IRQ_SHIFT)
5241 #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_MASK (0x1u << \
5244 #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_MASK (0x1u << \
5255 #define PMU_FIS_DN_TIMER_VAL_MASK 0x7FFF0000u
5257 #define PMU_FIS_DN_TIMER_VAL_4378 0x2f80u /* micro second */
5258 #define PMU_FIS_DN_TIMER_VAL_4388 0x3f80u /* micro second */
5259 #define PMU_FIS_DN_TIMER_VAL_4389 0x3f80u /* micro second */
5264 #define PMU_REG6_RFLDO_CTRL 0x000000E0
5267 #define PMU_REG6_BTLDO_CTRL 0x0000E000
5275 #define BCM4387_SSSR_DUMP_AXI_MAIN 0xE8C00000u
5277 #define BCM4387_SSSR_DUMP_AXI_AUX 0xE8400000u
5279 #define BCM4387_SSSR_DUMP_AXI_SCAN 0xE9400000u