Lines Matching refs:sih
142 static void si_pmu_chipcontrol_xtal_settings_4369(si_t *sih);
143 static void si_pmu_chipcontrol_xtal_settings_4362(si_t *sih);
144 static void si_pmu_chipcontrol_xtal_settings_4378(si_t *sih);
147 static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 xtal);
148 static void si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask,
150 static void si_pmu_pll_on(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 min_mask,
152 static void si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh);
153 static void si_pmu_otp_vreg_control(si_t *sih, osl_t *osh);
154 static void si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh);
155 static uint32 si_pmu_def_alp_clock(si_t *sih, osl_t *osh);
156 static bool si_pmu_update_pllcontrol(si_t *sih, osl_t *osh, uint32 xtal, bool update_required);
157 static uint32 si_pmu_htclk_mask(si_t *sih);
159 static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, pmuregs_t *pmu);
160 static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, pmuregs_t *pmu);
162 static uint32 si_pmu1_cpuclk0_pll2(si_t *sih);
165 static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 rsrcs, bool all);
166 static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, pmuregs_t *pmu,
168 static void si_pmu_res_masks(si_t *sih, uint32 *pmin, uint32 *pmax);
170 uint32 si_pmu_get_pmutime_diff(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *prev);
171 bool si_pmu_wait_for_res_pending(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint usec,
175 static uint32 si_pmu_mem_ca7clock(si_t *sih, osl_t *osh);
181 static uint32 si_pmu_bpclk_4387(si_t *sih);
183 static int si_pmu_openloop_cal_43012(si_t *sih, uint16 currtemp);
187 static bool si_pmu_armpll_write_required(si_t *sih, uint32 xtal);
191 void si_pmu_armpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac);
192 void si_pmu_bbpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac);
193 void si_pmu_armpll_chmdiv_upd(si_t *sih, uint32 ch0_mdiv, uint32 ch1_mdiv);
196 static int si_pmu_ldo3p3_soft_start_get(si_t *sih, osl_t *osh, uint32 bt_or_wl, int *res);
197 static int si_pmu_ldo3p3_soft_start_set(si_t *sih, osl_t *osh, uint32 bt_or_wl, uint32 slew_rate);
200 static void si_pmu_chipcontrol_xtal_bias_from_otp(si_t *sih, uint8* flag, uint8* val);
202 static void si_pmu_chipcontrol_xtal_bias_cal_done_offsets(si_t *sih, uint16* wrd_offset,
204 static void si_pmu_chipcontrol_xtal_bias_val_offsets(si_t *sih, uint16* wrd_offset,
288 si_pmu_pllupd(si_t *sih) in si_pmu_pllupd() argument
290 pmu_corereg(sih, SI_CC_IDX, pmucontrol, in si_pmu_pllupd()
337 static rsc_per_chip_t* BCMRAMFN(si_pmu_get_rsc_positions)(si_t *sih) in BCMRAMFN()
341 switch (CHIPID(sih->chip)) { in BCMRAMFN()
422 BCMATTACHFN(si_pmu_otp_pllcontrol)(si_t *sih, osl_t *osh) in BCMATTACHFN()
434 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
435 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
437 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
446 si_pmu_pllcontrol(sih, i, ~0, val); in BCMATTACHFN()
455 BCMATTACHFN(si_pmu_otp_vreg_control)(si_t *sih, osl_t *osh) in BCMATTACHFN()
467 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
468 vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
470 vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT; in BCMATTACHFN()
479 si_pmu_vreg_control(sih, i, ~0, val); in BCMATTACHFN()
488 BCMATTACHFN(si_pmu_otp_chipcontrol)(si_t *sih, osl_t *osh) in BCMATTACHFN()
497 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
498 cc_ctrlcnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMATTACHFN()
500 cc_ctrlcnt = (sih->pmucaps & PCAP_CC_MASK) >> PCAP_CC_SHIFT; in BCMATTACHFN()
509 si_pmu_chipcontrol(sih, i, 0xFFFFFFFF, val); /* writes to PMU chipctrl reg 'i' */ in BCMATTACHFN()
519 si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, uint8 ldo, uint8 voltage) in si_pmu_set_ldo_voltage() argument
527 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_set_ldo_voltage()
529 switch (CHIPID(sih->chip)) { in si_pmu_set_ldo_voltage()
568 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, /* PMU VREG register */ in si_pmu_set_ldo_voltage()
570 pmu_corereg(sih, SI_CC_IDX, regcontrol_data, in si_pmu_set_ldo_voltage()
574 si_pmu_vreg_control(sih, addr2, (mask2 >> rshift2) << rc_shift2, in si_pmu_set_ldo_voltage()
584 BCMINITFN(si_pmu_fast_pwrup_delay_legacy)(si_t *sih, osl_t *osh, pmuregs_t *pmu) in BCMINITFN()
591 switch (CHIPID(sih->chip)) { in BCMINITFN()
598 if (CHIPREV(sih->chiprev) < 4) { in BCMINITFN()
610 rsc = si_pmu_get_rsc_positions(sih); in BCMINITFN()
612 ilp = si_ilp_clock(sih); in BCMINITFN()
614 pmudelay = (si_pmu_res_uptime(sih, osh, pmu, rsc->macphy_clkavail, FALSE) + in BCMINITFN()
620 rsc = si_pmu_get_rsc_positions(sih); in BCMINITFN()
622 ilp = si_ilp_clock(sih); in BCMINITFN()
624 pmudelay = si_pmu_res_uptime(sih, osh, pmu, rsc->ht_avail, FALSE) + in BCMINITFN()
646 BCMINITFN(si_pmu_fast_pwrup_delay)(si_t *sih, osl_t *osh) in BCMINITFN()
655 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMINITFN()
657 if (ISSIM_ENAB(sih)) { in BCMINITFN()
662 macunit = si_coreunit(sih); in BCMINITFN()
664 origidx = si_coreidx(sih); in BCMINITFN()
668 if (AOB_ENAB(sih)) { in BCMINITFN()
669 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
671 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMINITFN()
678 rsc = si_pmu_get_rsc_positions(sih); in BCMINITFN()
680 switch (CHIPID(sih->chip)) { in BCMINITFN()
686 pmudelay = si_pmu_res_uptime(sih, osh, pmu, in BCMINITFN()
689 pmudelay = si_pmu_res_uptime(sih, osh, pmu, in BCMINITFN()
700 pmudelay = si_pmu_res_uptime(sih, osh, pmu, in BCMINITFN()
703 pmudelay = si_pmu_res_uptime(sih, osh, pmu, in BCMINITFN()
706 pmudelay = si_pmu_res_uptime(sih, osh, pmu, in BCMINITFN()
714 pmudelay = si_pmu_fast_pwrup_delay_legacy(sih, osh, pmu); in BCMINITFN()
719 si_setcoreidx(sih, origidx); in BCMINITFN()
729 BCMINITFN(si_pmu_fast_pwrup_delay_rsrc)(si_t *sih, osl_t *osh, uint8 rsrc) in BCMINITFN()
736 origidx = si_coreidx(sih); in BCMINITFN()
737 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
743 pmudelay = si_pmu_res_uptime(sih, osh, pmu, rsrc, pmu_fast_trans_en); in BCMINITFN()
746 si_setcoreidx(sih, origidx); in BCMINITFN()
755 BCMINITFN(si_pmu_fast_pwrup_delay_dig)(si_t *sih, osl_t *osh) in BCMINITFN()
758 rsc_per_chip_t *rsc = si_pmu_get_rsc_positions(sih); in BCMINITFN()
762 delay = si_pmu_fast_pwrup_delay_rsrc(sih, osh, rsc->dig_ready); in BCMINITFN()
793 bool (*filter)(si_t *sih); /* action is taken when filter is NULL or return TRUE */
1695 void si_pmu_avbtimer_enable(si_t *sih, osl_t *osh, bool set_flag) in si_pmu_avbtimer_enable() argument
1702 origidx = si_coreidx(sih); in si_pmu_avbtimer_enable()
1703 if (AOB_ENAB(sih)) { in si_pmu_avbtimer_enable()
1704 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_avbtimer_enable()
1706 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_avbtimer_enable()
1710 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID || CHIPID(sih->chip) == BCM43460_CHIP_ID) && in si_pmu_avbtimer_enable()
1711 CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_avbtimer_enable()
1712 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_avbtimer_enable()
1740 si_setcoreidx(sih, origidx); in si_pmu_avbtimer_enable()
1748 si_pmu_res_masks(si_t *sih, uint32 *pmin, uint32 *pmax) in si_pmu_res_masks() argument
1753 switch (CHIPID(sih->chip)) { in si_pmu_res_masks()
1756 if (CHIPREV(sih->chiprev) >= 0x4) { in si_pmu_res_masks()
1762 if (CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_res_masks()
1764 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_res_masks()
1783 if (sih->chippkg == BCM43602_12x12_PKG_ID) /* LPLDO WAR */ in si_pmu_res_masks()
1792 if (SR_ENAB() && sr_isenab(sih)) { in si_pmu_res_masks()
1793 ASSERT(sih->chippkg != BCM43602_12x12_PKG_ID); in si_pmu_res_masks()
1808 if (SR_ENAB() && sr_isenab(sih)) { in si_pmu_res_masks()
1809 if (si_get_nvram_rfldo3p3_war(sih)) { in si_pmu_res_masks()
1823 if (!sr_isenab(sih)) { in si_pmu_res_masks()
1837 if (sr_isenab(sih)) { in si_pmu_res_masks()
1840 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1856 if (sr_isenab(sih)) { in si_pmu_res_masks()
1859 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1878 if (sr_isenab(sih)) { in si_pmu_res_masks()
1881 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1900 if (SR_ENAB() && sr_isenab(sih)) { in si_pmu_res_masks()
1914 si_nvram_res_masks(sih, &min_mask, &max_mask); in si_pmu_res_masks()
1928 si_pmu_resdeptbl_upd(si_t *sih, osl_t *osh, pmuregs_t *pmu, in si_pmu_resdeptbl_upd() argument
1932 BCMATTACHFN(si_pmu_resdeptbl_upd)(si_t *sih, osl_t *osh, pmuregs_t *pmu, in si_pmu_resdeptbl_upd()
1943 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in si_pmu_resdeptbl_upd()
1947 !(restable[tablesz].filter)(sih)) in si_pmu_resdeptbl_upd()
1982 BCMATTACHFN(si_pmu_dep_table_fll_pu_fixup)(si_t *sih, osl_t *osh, in BCMATTACHFN()
1991 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
2054 BCMATTACHFN(si_pmu_res_init)(si_t *sih, osl_t *osh) in BCMATTACHFN()
2075 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
2078 origidx = si_coreidx(sih); in BCMATTACHFN()
2079 if (AOB_ENAB(sih)) { in BCMATTACHFN()
2080 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
2082 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
2090 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
2093 if (CHIPREV(sih->chiprev) < 4) { in BCMATTACHFN()
2110 if (sih->chippkg == BCM43602_12x12_PKG_ID) { /* LPLDO WAR */ in BCMATTACHFN()
2131 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2144 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2172 GCI_REG_NEW(sih, bt_smem_control1, (0xFF<<16), 0); in BCMATTACHFN()
2174 si_pmu_chipcontrol(sih, PMU_CHIPCTL14, in BCMATTACHFN()
2182 si_pmu_chipcontrol(sih, PMU_CHIPCTL15, in BCMATTACHFN()
2186 si_pmu_chipcontrol(sih, PMU_CHIPCTL10, in BCMATTACHFN()
2190 GCI_REG_NEW(sih, bt_smem_control0, (0xF<<16), 0); in BCMATTACHFN()
2191 GCI_REG_NEW(sih, bt_smem_control0, (0xF<<24), 0); in BCMATTACHFN()
2210 if (ISSIM_ENAB(sih)) { in BCMATTACHFN()
2211 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
2237 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
2257 si_pmu_dep_table_fll_pu_fixup(sih, osh, in BCMATTACHFN()
2279 if (ISSIM_ENAB(sih)) { in BCMATTACHFN()
2299 si_pmu_dep_table_fll_pu_fixup(sih, osh, in BCMATTACHFN()
2308 if (ISSIM_ENAB(sih)) { in BCMATTACHFN()
2327 si_pmu_dep_table_fll_pu_fixup(sih, osh, in BCMATTACHFN()
2351 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMATTACHFN()
2362 if (PMUREV(sih->pmurev) >= 13) { in BCMATTACHFN()
2391 si_pmu_resdeptbl_upd(sih, osh, pmu, pmu_res_depend_table, pmu_res_depend_table_sz); in BCMATTACHFN()
2413 if (BUSTYPE(sih->bustype) == PCI_BUS || BUSTYPE(sih->bustype) == SI_BUS) { in BCMATTACHFN()
2414 bool is_pciedev = BCM43602_CHIP(sih->chip); in BCMATTACHFN()
2419 si_pmu_resdeptbl_upd(sih, osh, pmu, in BCMATTACHFN()
2427 si_pmu_res_masks(sih, &min_mask, &max_mask); in BCMATTACHFN()
2429 min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, FALSE); in BCMATTACHFN()
2448 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2449 (CHIPREV(sih->chiprev) < 4) && in BCMATTACHFN()
2450 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2452 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, ~0, 0x09048562); in BCMATTACHFN()
2454 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG14, ~0, 0x09048562); in BCMATTACHFN()
2455 si_pmu_pllupd(sih); in BCMATTACHFN()
2456 } else if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
2457 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2458 (CHIPREV(sih->chiprev) >= 4) && in BCMATTACHFN()
2459 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2463 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, 0x800, 0x800); in BCMATTACHFN()
2466 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, ~0, 0x080004e2); in BCMATTACHFN()
2467 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG7, ~0, 0xE); in BCMATTACHFN()
2469 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG14, ~0, 0x080004e2); in BCMATTACHFN()
2470 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG15, ~0, 0xE); in BCMATTACHFN()
2471 si_pmu_pllupd(sih); in BCMATTACHFN()
2474 si_pll_closeloop(sih); in BCMATTACHFN()
2513 si_pmu_min_res_ldo3p3_set(sih, osh, TRUE); in BCMATTACHFN()
2519 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2520 (BUSTYPE(sih->bustype) == PCI_BUS) && in BCMATTACHFN()
2521 (CHIPREV(sih->chiprev) < 4)) { in BCMATTACHFN()
2524 pcie_clk_ctl_st = si_corereg(sih, 3, 0x1e0, 0, 0); in BCMATTACHFN()
2525 si_corereg(sih, 3, 0x1e0, ~0, (pcie_clk_ctl_st | CCS_HTAREQ)); in BCMATTACHFN()
2528 si_pmu_wait_for_steady_state(sih, osh, pmu); in BCMATTACHFN()
2533 si_setcoreidx(sih, origidx); in BCMATTACHFN()
2897 BCMPOSTTRAPFN(si_pmu1_xtaltab0)(si_t *sih) in BCMPOSTTRAPFN()
2902 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
2925 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
2934 BCMPOSTTRAPFN(si_pmu1_xtaldef0)(si_t *sih) in BCMPOSTTRAPFN()
2940 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
2969 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
2983 BCMPOSTTRAPFN(si_pmu_pll1_fvco_4360)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
2998 si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val); in BCMPOSTTRAPFN()
3000 xf = si_pmu_alp_clock(sih, osh)/1000; in BCMPOSTTRAPFN()
3003 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG10, 0, 0); in BCMPOSTTRAPFN()
3008 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG11, 0, 0); in BCMPOSTTRAPFN()
3035 si_restore_core(sih, origidx, &intr_val); in BCMPOSTTRAPFN()
3046 BCMPOSTTRAPFN(si_pmu_pll1_fvco_43012)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
3056 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val); in BCMPOSTTRAPFN()
3060 xf = si_pmu_alp_clock(sih, osh)/1000; in BCMPOSTTRAPFN()
3062 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG0, 0, 0); in BCMPOSTTRAPFN()
3070 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in BCMPOSTTRAPFN()
3102 si_restore_core(sih, origidx, &intr_val); in BCMPOSTTRAPFN()
3108 BCMPOSTTRAPFN(si_pmu1_pllfvco0)(si_t *sih) in BCMPOSTTRAPFN()
3114 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
3125 osh = si_osh(sih); in BCMPOSTTRAPFN()
3126 return si_pmu_pll1_fvco_4360(sih, osh); in BCMPOSTTRAPFN()
3133 osh = si_osh(sih); in BCMPOSTTRAPFN()
3134 return si_pmu_pll1_fvco_43012(sih, osh); in BCMPOSTTRAPFN()
3150 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
3161 BCMPOSTTRAPFN(si_pmu1_pllfvco0_pll2)(si_t *sih) in BCMPOSTTRAPFN()
3167 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
3172 return si_get_armpllclkfreq(sih) * 1000; in BCMPOSTTRAPFN()
3174 return SI_INFO(sih)->armpllclkfreq ? si_get_armpllclkfreq(sih) * 1000 : FVCO_1002p8; in BCMPOSTTRAPFN()
3182 bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
3191 BCMPOSTTRAPFN(si_pmu1_alpclk0)(si_t *sih, osl_t *osh, pmuregs_t *pmu) in BCMPOSTTRAPFN()
3197 BCM_REFERENCE(sih); in BCMPOSTTRAPFN()
3202 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMPOSTTRAPFN()
3207 xt = si_pmu1_xtaldef0(sih); in BCMPOSTTRAPFN()
3210 switch (CHIPID(sih->chip)) in BCMPOSTTRAPFN()
3235 si_pmu_htclk_mask(si_t *sih) in si_pmu_htclk_mask() argument
3238 rsc_per_chip_t *rsc = si_pmu_get_rsc_positions(sih); in si_pmu_htclk_mask()
3242 switch (CHIPID(sih->chip)) in si_pmu_htclk_mask()
3269 BCMATTACHFN(si_pmu_def_alp_clock)(si_t *sih, osl_t *osh) in BCMATTACHFN()
3275 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3316 si_pmu_pllctrlreg_update(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 xtal, in si_pmu_pllctrlreg_update() argument
3325 if (PMUREV(sih->pmurev) >= 5) { in si_pmu_pllctrlreg_update()
3326 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in si_pmu_pllctrlreg_update()
3328 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in si_pmu_pllctrlreg_update()
3343 si_pmu_pllcontrol(sih, reg_offset, ~0, in si_pmu_pllctrlreg_update()
3348 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in si_pmu_pllctrlreg_update()
3351 si_get_armpllclkfreq(sih), xtal, TRUE); in si_pmu_pllctrlreg_update()
3384 si_pmu_armpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac) in si_pmu_armpll_freq_upd() argument
3386 switch (CHIPID(sih->chip)) { in si_pmu_armpll_freq_upd()
3388 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4388_ARMPLL_I_NDIV_INT_MASK, in si_pmu_armpll_freq_upd()
3390 si_pmu_pllupd(sih); in si_pmu_armpll_freq_upd()
3393 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4389_ARMPLL_I_NDIV_INT_MASK, in si_pmu_armpll_freq_upd()
3395 si_pmu_pllupd(sih); in si_pmu_armpll_freq_upd()
3398 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, PMU4369_PLL1_PC5_P1DIV_MASK, in si_pmu_armpll_freq_upd()
3400 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_P1DIV_MASK, in si_pmu_armpll_freq_upd()
3402 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_NDIV_INT_MASK, in si_pmu_armpll_freq_upd()
3404 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_NDIV_FRAC_MASK, in si_pmu_armpll_freq_upd()
3406 si_pmu_pllupd(sih); in si_pmu_armpll_freq_upd()
3410 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, PMU4369_PLL1_PC5_P1DIV_MASK, in si_pmu_armpll_freq_upd()
3412 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_P1DIV_MASK, in si_pmu_armpll_freq_upd()
3414 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_NDIV_INT_MASK, in si_pmu_armpll_freq_upd()
3416 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, PMU4369_PLL1_PC6_NDIV_FRAC_MASK, in si_pmu_armpll_freq_upd()
3418 si_pmu_pllupd(sih); in si_pmu_armpll_freq_upd()
3427 si_pmu_bbpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac) in si_pmu_bbpll_freq_upd() argument
3429 switch (CHIPID(sih->chip)) { in si_pmu_bbpll_freq_upd()
3433 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, PMU4369_PLL0_PC2_PDIV_MASK, p1div); in si_pmu_bbpll_freq_upd()
3434 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, PMU4369_PLL0_PC2_NDIV_INT_MASK, in si_pmu_bbpll_freq_upd()
3436 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, PMU4369_PLL0_PC3_NDIV_FRAC_MASK, in si_pmu_bbpll_freq_upd()
3438 si_pmu_pllupd(sih); in si_pmu_bbpll_freq_upd()
3447 si_pmu_armpll_chmdiv_upd(si_t *sih, uint32 ch0_mdiv, uint32 ch1_mdiv) in si_pmu_armpll_chmdiv_upd() argument
3449 switch (CHIPID(sih->chip)) { in si_pmu_armpll_chmdiv_upd()
3457 si_pmu_armpll_write_required(si_t *sih, uint32 xtal) in si_pmu_armpll_write_required() argument
3461 uint32 armclk_mhz = si_get_armpllclkfreq(sih); in si_pmu_armpll_write_required()
3463 switch (CHIPID(sih->chip)) { in si_pmu_armpll_write_required()
3500 BCMATTACHFN(si_pmu_update_pllcontrol)(si_t *sih, osl_t *osh, uint32 xtal, bool update_required) in BCMATTACHFN()
3535 if (xtal != (si_pmu_def_alp_clock(sih, osh)/1000)) in BCMATTACHFN()
3542 xtal = si_pmu_def_alp_clock(sih, osh)/1000; in BCMATTACHFN()
3546 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3603 origidx = si_coreidx(sih); in BCMATTACHFN()
3604 if (AOB_ENAB(sih)) { in BCMATTACHFN()
3605 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
3607 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
3617 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update, in BCMATTACHFN()
3636 write_en = si_pmu_armpll_write_required(sih, xtal); in BCMATTACHFN()
3646 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 0, pllctrlreg_update, array_size, in BCMATTACHFN()
3651 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3653 uint32 armclk_mhz = si_get_armpllclkfreq(sih); in BCMATTACHFN()
3667 si_pmu_armpll_freq_upd(sih, 0, ndiv_int, 0); in BCMATTACHFN()
3672 uint32 armclk_mhz = si_get_armpllclkfreq(sih); in BCMATTACHFN()
3686 si_pmu_armpll_freq_upd(sih, 0, ndiv_int, 0); in BCMATTACHFN()
3697 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMATTACHFN()
3719 if (BCM4389_CHIP(sih->chip)) { in BCMATTACHFN()
3723 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, in BCMATTACHFN()
3725 } else if (BCM4388_CHIP(sih->chip)) { in BCMATTACHFN()
3729 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, in BCMATTACHFN()
3731 } else if (BCM4369_CHIP(sih->chip) || in BCMATTACHFN()
3732 BCM4362_CHIP(sih->chip) || in BCMATTACHFN()
3739 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, in BCMATTACHFN()
3745 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, in BCMATTACHFN()
3751 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, in BCMATTACHFN()
3759 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG0, in BCMATTACHFN()
3767 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, in BCMATTACHFN()
3772 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, in BCMATTACHFN()
3787 si_setcoreidx(sih, origidx); in BCMATTACHFN()
3796 BCMPOSTTRAPFN(si_pmu_get_pmutimer)(si_t *sih) in BCMPOSTTRAPFN()
3798 osl_t *osh = si_osh(sih); in BCMPOSTTRAPFN()
3802 BCM_REFERENCE(sih); in BCMPOSTTRAPFN()
3804 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
3805 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
3806 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
3808 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
3816 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
3823 si_cur_pmu_time(si_t *sih) in si_cur_pmu_time() argument
3829 origidx = si_coreidx(sih); in si_cur_pmu_time()
3831 pmu_time = si_pmu_get_pmutimer(sih); in si_cur_pmu_time()
3834 si_setcoreidx(sih, origidx); in si_cur_pmu_time()
3845 BCMPOSTTRAPFN(si_pmu_get_pmutime_diff)(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *prev) in BCMPOSTTRAPFN()
3852 pmutime_val = si_pmu_get_pmutimer(sih); in BCMPOSTTRAPFN()
3870 BCMPOSTTRAPFN(si_pmu_wait_for_res_pending)(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint usec, in BCMPOSTTRAPFN()
3879 pmutime_prev = si_pmu_get_pmutimer(sih); in BCMPOSTTRAPFN()
3900 pmutime_elapsed += si_pmu_get_pmutime_diff(sih, osh, pmu, &pmutime_prev); in BCMPOSTTRAPFN()
3921 BCMPOSTTRAPFN(si_pmu_wait_for_steady_state)(si_t *sih, osl_t *osh, pmuregs_t *pmu) in BCMPOSTTRAPFN()
3923 si_info_t *sii = SI_INFO(sih); in BCMPOSTTRAPFN()
3931 pmutime_prev = si_pmu_get_pmutimer(sih); in BCMPOSTTRAPFN()
3935 timedout = si_pmu_wait_for_res_pending(sih, osh, pmu, in BCMPOSTTRAPFN()
3939 si_pmu_get_pmutime_diff(sih, osh, pmu, &pmutime_prev); in BCMPOSTTRAPFN()
3955 timedout = si_pmu_wait_for_res_pending(sih, osh, pmu, in BCMPOSTTRAPFN()
3961 si_pmu_get_pmutime_diff(sih, osh, pmu, &pmutime_prev); in BCMPOSTTRAPFN()
3990 si_pmu_pll_delay_43012(si_t *sih, uint32 delay_us, uint32 poll) in si_pmu_pll_delay_43012() argument
4004 if (si_gci_chipstatus(sih, GCI_CHIPSTATUS_07) & in si_pmu_pll_delay_43012()
4010 delay = ((current - initial) * 1000) / si_xtalfreq(sih); in si_pmu_pll_delay_43012()
4015 if (si_gci_chipstatus(sih, GCI_CHIPSTATUS_07) & in si_pmu_pll_delay_43012()
4033 si_pmu_pll_on_43012(si_t *sih, osl_t *osh, pmuregs_t *pmu, bool openloop_cal) in si_pmu_pll_on_43012() argument
4037 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_PWROFF, 0); in si_pmu_pll_on_43012()
4038 total_time += si_pmu_pll_delay_43012(sih, 2, 0); in si_pmu_pll_on_43012()
4039 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH | in si_pmu_pll_on_43012()
4041 total_time += si_pmu_pll_delay_43012(sih, 2, 0); in si_pmu_pll_on_43012()
4042 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_ARESET, 0); in si_pmu_pll_on_43012()
4050 total_time += si_pmu_pll_delay_43012(sih, 200, 1); in si_pmu_pll_on_43012()
4054 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_on_43012()
4059 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_DRESET, 0); in si_pmu_pll_on_43012()
4060 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_on_43012()
4061 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_DISABLE_LQ_AVAIL, 0); in si_pmu_pll_on_43012()
4062 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_DISABLE_HT_AVAIL, 0); in si_pmu_pll_on_43012()
4069 si_pmu_pll_off_43012(si_t *sih, osl_t *osh, pmuregs_t *pmu) in si_pmu_pll_off_43012() argument
4074 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in si_pmu_pll_off_43012()
4077 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_off_43012()
4079 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in si_pmu_pll_off_43012()
4084 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_off_43012()
4086 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in si_pmu_pll_off_43012()
4095 si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask, in si_pmu_pll_off() argument
4103 *clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0); in si_pmu_pll_off()
4105 ht_req = si_pmu_htclk_mask(sih); in si_pmu_pll_off()
4109 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off()
4110 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off()
4111 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in si_pmu_pll_off()
4112 (BCM4369_CHIP(sih->chip)) || in si_pmu_pll_off()
4113 (BCM4362_CHIP(sih->chip)) || in si_pmu_pll_off()
4114 (BCM4376_CHIP(sih->chip)) || in si_pmu_pll_off()
4115 (BCM4378_CHIP(sih->chip)) || in si_pmu_pll_off()
4116 (BCM4385_CHIP(sih->chip)) || in si_pmu_pll_off()
4117 (BCM4387_CHIP(sih->chip)) || in si_pmu_pll_off()
4118 (BCM4388_CHIP(sih->chip)) || in si_pmu_pll_off()
4119 (BCM4389_CHIP(sih->chip)) || in si_pmu_pll_off()
4120 BCM43602_CHIP(sih->chip) || in si_pmu_pll_off()
4125 if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4127 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_pll_off()
4131 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4133 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4137 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off()
4138 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off()
4139 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_pmu_pll_off()
4140 si_pmu_pll_off_43012(sih, osh, pmu); in si_pmu_pll_off()
4145 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4147 ASSERT(!(si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4156 si_pmu_pll_off_PARR(si_t *sih, osl_t *osh, uint32 *min_mask, in si_pmu_pll_off_PARR() argument
4165 si_introff(sih, &intr_val); in si_pmu_pll_off_PARR()
4166 origidx = si_coreidx(sih); in si_pmu_pll_off_PARR()
4167 if (AOB_ENAB(sih)) { in si_pmu_pll_off_PARR()
4168 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_pll_off_PARR()
4170 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_pll_off_PARR()
4177 *clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0); in si_pmu_pll_off_PARR()
4178 ht_req = si_pmu_htclk_mask(sih); in si_pmu_pll_off_PARR()
4181 si_setcoreidx(sih, origidx); in si_pmu_pll_off_PARR()
4182 si_intrrestore(sih, &intr_val); in si_pmu_pll_off_PARR()
4186 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off_PARR()
4187 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off_PARR()
4188 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in si_pmu_pll_off_PARR()
4189 (BCM4369_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4190 (BCM4362_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4191 (BCM4376_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4192 (BCM4378_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4193 (BCM4385_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4194 (BCM4387_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4195 (BCM4388_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4196 (BCM4389_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4197 (BCM4397_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4198 (BCM43602_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4203 if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4206 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_pll_off_PARR()
4210 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4212 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4220 si_setcoreidx(sih, origidx); in si_pmu_pll_off_PARR()
4221 si_intrrestore(sih, &intr_val); in si_pmu_pll_off_PARR()
4226 si_pmu_pll_on(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 min_mask_mask, in si_pmu_pll_on() argument
4231 ht_req = si_pmu_htclk_mask(sih); in si_pmu_pll_on()
4246 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_on()
4248 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_on()
4252 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_on()
4253 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_on()
4254 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_pmu_pll_on()
4255 si_pmu_pll_on_43012(sih, osh, pmu, 0); in si_pmu_pll_on()
4265 BCMATTACHFN(si_pmu1_pllinit1)(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 xtal) in BCMATTACHFN()
4277 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
4278 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
4280 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
4299 (si_pmu_update_pllcontrol(sih, osh, xtal, FALSE) == FALSE)) { in BCMATTACHFN()
4305 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in BCMATTACHFN()
4306 (regval = si_pmu_pllcontrol(sih, 3, 0, 0)) != PMU_PLL3_4369B0_DEFAULT) { in BCMATTACHFN()
4314 si_gci_output(sih, GCI_ECI_SW1(GCI_WLAN_IP_ID), GCI_SWREADY, GCI_SWREADY); in BCMATTACHFN()
4327 if (si_gci_input(sih, GCI_ECI_SW1(GCI_BT_IP_ID)) & GCI_SWREADY) { in BCMATTACHFN()
4331 if (si_pmu_update_pllcontrol(sih, osh, xtal, FALSE)) { in BCMATTACHFN()
4333 si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st); in BCMATTACHFN()
4336 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in BCMATTACHFN()
4340 si_get_armpllclkfreq(sih), xtal, TRUE); in BCMATTACHFN()
4344 if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
4350 si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st); in BCMATTACHFN()
4356 if ((regval = si_pmu_pllcontrol(sih, 3, 0, 0)) != otpval) { in BCMATTACHFN()
4367 si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st); in BCMATTACHFN()
4370 si_pmu_update_pllcontrol(sih, osh, xtal, TRUE); in BCMATTACHFN()
4373 si_pmu_otp_pllcontrol(sih, osh); in BCMATTACHFN()
4376 if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
4382 si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st); in BCMATTACHFN()
4384 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
4385 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
4386 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in BCMATTACHFN()
4396 origidx = si_coreidx(sih); in BCMATTACHFN()
4397 si_setcore(sih, SDIOD_CORE_ID, 0); in BCMATTACHFN()
4399 si_wrapperreg(sih, AI_OOBSELOUTB30, (AI_OOBSEL_MASK << AI_OOBSEL_1_SHIFT), in BCMATTACHFN()
4401 si_setcoreidx(sih, origidx); in BCMATTACHFN()
4407 si_gci_output(sih, GCI_ECI_SW1(GCI_WLAN_IP_ID), GCI_SWREADY, GCI_SWREADY); in BCMATTACHFN()
4418 uint32 si_pmu_get_backplaneclkspeed(si_t *sih) in si_pmu_get_backplaneclkspeed() argument
4423 switch (CHIPID(sih->chip)) { in si_pmu_get_backplaneclkspeed()
4429 return si_pmu_bpclk_4387(sih); in si_pmu_get_backplaneclkspeed()
4434 FVCO = si_pmu1_pllfvco0(sih); in si_pmu_get_backplaneclkspeed()
4436 switch (CHIPID(sih->chip)) { in si_pmu_get_backplaneclkspeed()
4440 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_get_backplaneclkspeed()
4452 si_pmu_update_backplane_clock(si_t *sih, osl_t *osh, uint reg, uint32 mask, uint32 val) in si_pmu_update_backplane_clock() argument
4460 origidx = si_coreidx(sih); in si_pmu_update_backplane_clock()
4462 if (AOB_ENAB(sih)) { in si_pmu_update_backplane_clock()
4463 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_update_backplane_clock()
4465 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_update_backplane_clock()
4471 si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st); in si_pmu_update_backplane_clock()
4473 si_pmu_pllcontrol(sih, reg, mask, val); in si_pmu_update_backplane_clock()
4476 if (PMUREV(sih->pmurev) >= 2) in si_pmu_update_backplane_clock()
4482 si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st); in si_pmu_update_backplane_clock()
4483 si_setcoreidx(sih, origidx); in si_pmu_update_backplane_clock()
4493 BCMPOSTTRAPFN(si_pmu_bpclk_4387)(si_t *sih) in BCMPOSTTRAPFN()
4498 FVCO = si_pmu1_pllfvco0(sih); in BCMPOSTTRAPFN()
4500 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in BCMPOSTTRAPFN()
4512 BCMPOSTTRAPFN(si_pmu1_cpuclk0)(si_t *sih, osl_t *osh, pmuregs_t *pmu) in BCMPOSTTRAPFN()
4524 FVCO = si_pmu1_pllfvco0(sih); in BCMPOSTTRAPFN()
4526 if (BCM43602_CHIP(sih->chip) && in BCMPOSTTRAPFN()
4529 (si_arm_clockratio(sih, 0) == 1) && in BCMPOSTTRAPFN()
4534 return si_pmu_si_clock(sih, osh); /* in [hz] units */ in BCMPOSTTRAPFN()
4537 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
4543 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in BCMPOSTTRAPFN()
4549 ASSERT(si_arm_clockratio(sih, 0) == 2); in BCMPOSTTRAPFN()
4552 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in BCMPOSTTRAPFN()
4564 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4568 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4574 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4579 PMU_MSG(("si_pmu1_cpuclk0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
4588 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG0, 0, 0); in BCMPOSTTRAPFN()
4595 tmp = si_pmu_pllcontrol(sih, tmp, 0, 0); in BCMPOSTTRAPFN()
4597 if (BCM4362_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4598 BCM4369_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
4603 } else if (BCM4378_CHIP(sih->chip) || BCM4376_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
4616 tmp = si_pmu_pllcontrol(sih, tmp, 0, 0); in BCMPOSTTRAPFN()
4618 if (BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4619 BCM4376_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4620 BCM4378_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4625 fref = si_pmu1_alpclk0(sih, osh, pmu) / 1000; /* [KHz] */ in BCMPOSTTRAPFN()
4637 fref = si_pmu1_alpclk0(sih, osh, pmu) / 1000; in BCMPOSTTRAPFN()
4665 BCMPOSTTRAPFN(si_pmu1_cpuclk0_pll2)(si_t *sih) in BCMPOSTTRAPFN()
4667 uint32 FVCO = si_pmu1_pllfvco0_pll2(sih); /* in [khz] units */ in BCMPOSTTRAPFN()
4678 si_mac_clk(si_t *sih, osl_t *osh) in si_mac_clk() argument
4689 uint32 FVCO = si_pmu1_pllfvco0(sih); /* in [khz] units */ in si_mac_clk()
4694 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val); in si_mac_clk()
4698 switch (CHIPID(sih->chip)) { in si_mac_clk()
4707 bcm_chipname(CHIPID(sih->chip), chn, 8))); in si_mac_clk()
4713 si_restore_core(sih, origidx, &intr_val); in si_mac_clk()
4720 si_pmu_macdiv_4387(si_t *sih) in si_pmu_macdiv_4387() argument
4727 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_macdiv_4387()
4736 si_pmu_fvco_macdiv(si_t *sih, uint32 *fvco, uint32 *div) in si_pmu_fvco_macdiv() argument
4747 *fvco = si_pmu1_pllfvco0(sih)/1000; in si_pmu_fvco_macdiv()
4750 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val); in si_pmu_fvco_macdiv()
4754 switch (CHIPID(sih->chip)) { in si_pmu_fvco_macdiv()
4758 *div = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG12, 0, 0) & in si_pmu_fvco_macdiv()
4764 *div = (si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0) & in si_pmu_fvco_macdiv()
4771 *div = (si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0) in si_pmu_fvco_macdiv()
4785 *div = (si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0) in si_pmu_fvco_macdiv()
4794 *div = si_pmu_macdiv_4387(sih); in si_pmu_fvco_macdiv()
4798 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in si_pmu_fvco_macdiv()
4803 si_restore_core(sih, origidx, &intr_val); in si_pmu_fvco_macdiv()
4810 BCMPOSTTRAPFN(si_pmu_reset_ret_sleep_log)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
4818 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
4819 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
4820 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
4822 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
4833 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
4840 BCMPOSTTRAPFN(si_pmu_reset_chip_sleep_log)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
4847 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
4848 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
4849 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
4851 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
4855 if (PMUREV(sih->pmurev) >= 36) { in BCMPOSTTRAPFN()
4863 was_sleep = si_pmu_reset_ret_sleep_log(sih, osh); in BCMPOSTTRAPFN()
4867 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
4874 si_pmu_switch_on_PARLDO(si_t *sih, osl_t *osh) in si_pmu_switch_on_PARLDO() argument
4881 origidx = si_coreidx(sih); in si_pmu_switch_on_PARLDO()
4882 if (AOB_ENAB(sih)) { in si_pmu_switch_on_PARLDO()
4883 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_switch_on_PARLDO()
4885 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_switch_on_PARLDO()
4889 switch (CHIPID(sih->chip)) { in si_pmu_switch_on_PARLDO()
4900 si_setcoreidx(sih, origidx); in si_pmu_switch_on_PARLDO()
4905 si_pmu_switch_off_PARLDO(si_t *sih, osl_t *osh) in si_pmu_switch_off_PARLDO() argument
4912 origidx = si_coreidx(sih); in si_pmu_switch_off_PARLDO()
4913 if (AOB_ENAB(sih)) { in si_pmu_switch_off_PARLDO()
4914 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_switch_off_PARLDO()
4916 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_switch_off_PARLDO()
4920 switch (CHIPID(sih->chip)) { in si_pmu_switch_off_PARLDO()
4932 si_setcoreidx(sih, origidx); in si_pmu_switch_off_PARLDO()
4939 BCMATTACHFN(si_set_bb_vcofreq_frac)(si_t *sih, osl_t *osh, int vcofreq, int frac, int xtalfreq) in BCMATTACHFN()
4948 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
4949 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMATTACHFN()
4950 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMATTACHFN()
4951 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in BCMATTACHFN()
4952 BCM43602_CHIP(sih->chip)) { in BCMATTACHFN()
4953 if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in BCMATTACHFN()
4981 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, pllctrl2_mask, reg); in BCMATTACHFN()
4990 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, pllctrl3_mask, fraca); in BCMATTACHFN()
4993 si_pmu_pllupd(sih); in BCMATTACHFN()
5002 si_pmu_get_bb_vcofreq(si_t *sih, osl_t *osh, int xtalfreq) in si_pmu_get_bb_vcofreq() argument
5013 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5014 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5015 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5016 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5017 BCM43602_CHIP(sih->chip)) { in si_pmu_get_bb_vcofreq()
5018 reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in si_pmu_get_bb_vcofreq()
5024 frac = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in si_pmu_get_bb_vcofreq()
5025 } else if ((BCM4369_CHIP(sih->chip) && in si_pmu_get_bb_vcofreq()
5026 CST4369_CHIPMODE_PCIE(sih->chipst)) || in si_pmu_get_bb_vcofreq()
5027 BCM4376_CHIP(sih->chip) || in si_pmu_get_bb_vcofreq()
5028 BCM4378_CHIP(sih->chip) || in si_pmu_get_bb_vcofreq()
5029 (BCM4362_CHIP(sih->chip) && in si_pmu_get_bb_vcofreq()
5030 CST4362_CHIPMODE_PCIE(sih->chipst))) { in si_pmu_get_bb_vcofreq()
5031 reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in si_pmu_get_bb_vcofreq()
5034 frac = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0) & 0x00fffff; in si_pmu_get_bb_vcofreq()
5069 si_pmu_enb_slow_clk(si_t *sih, osl_t *osh, uint32 xtalfreq) in si_pmu_enb_slow_clk() argument
5075 if (PMUREV(sih->pmurev) < 24) { in si_pmu_enb_slow_clk()
5076 PMU_ERROR(("si_pmu_enb_slow_clk: Not supported %d\n", PMUREV(sih->pmurev))); in si_pmu_enb_slow_clk()
5081 origidx = si_coreidx(sih); in si_pmu_enb_slow_clk()
5082 if (AOB_ENAB(sih)) { in si_pmu_enb_slow_clk()
5083 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_enb_slow_clk()
5085 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_enb_slow_clk()
5090 if (PMUREV(sih->pmurev) >= 38) { in si_pmu_enb_slow_clk()
5096 if (PMUREV(sih->pmurev) >= 30) { in si_pmu_enb_slow_clk()
5118 si_setcoreidx(sih, origidx); in si_pmu_enb_slow_clk()
5127 si_setcoreidx(sih, origidx); in si_pmu_enb_slow_clk()
5138 BCMATTACHFN(si_pmu_pll_init)(si_t *sih, osl_t *osh, uint xtalfreq) in BCMATTACHFN()
5148 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
5151 origidx = si_coreidx(sih); in BCMATTACHFN()
5152 if (AOB_ENAB(sih)) { in BCMATTACHFN()
5153 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5155 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
5159 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
5163 if (CHIPREV(sih->chiprev) > 2) in BCMATTACHFN()
5164 si_set_bb_vcofreq_frac(sih, osh, 960, 98, 40); in BCMATTACHFN()
5168 si_set_bb_vcofreq_frac(sih, osh, 960, 98, 40); in BCMATTACHFN()
5181 si_pmu1_pllinit1(sih, osh, pmu, xtalfreq); /* nvram PLL overrides + enables PLL */ in BCMATTACHFN()
5186 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), PMUREV(sih->pmurev))); in BCMATTACHFN()
5191 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, CCS_FORCEHT) in BCMATTACHFN()
5194 si_pmu_enb_slow_clk(sih, osh, xtalfreq); in BCMATTACHFN()
5197 si_setcoreidx(sih, origidx); in BCMATTACHFN()
5202 BCMPOSTTRAPFN(si_pmu_alp_clock)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
5211 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5214 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
5215 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
5216 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5218 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
5222 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
5227 if (sih->chipst & CST4360_XTAL_40MZ) in BCMPOSTTRAPFN()
5251 clock = si_pmu1_alpclk0(sih, osh, pmu); in BCMPOSTTRAPFN()
5263 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), in BCMPOSTTRAPFN()
5264 PMUREV(sih->pmurev), clock)); in BCMPOSTTRAPFN()
5269 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
5279 BCMPOSTTRAPFN(si_pmu5_clock)(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint pll0, uint m) in BCMPOSTTRAPFN()
5311 fc = si_pmu_alp_clock(sih, osh) / 1000000; in BCMPOSTTRAPFN()
5326 BCMPOSTTRAPFN(si_pmu_si_clock)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
5335 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5338 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
5339 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
5340 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5342 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
5346 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
5354 clock = si_pmu1_cpuclk0(sih, osh, pmu); in BCMPOSTTRAPFN()
5360 mdiv = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0); in BCMPOSTTRAPFN()
5363 clock = si_pmu1_pllfvco0(sih) / mdiv * 1000; in BCMPOSTTRAPFN()
5371 clock = si_pmu1_cpuclk0(sih, osh, pmu); in BCMPOSTTRAPFN()
5379 clock = si_pmu_bpclk_4387(sih); in BCMPOSTTRAPFN()
5386 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), in BCMPOSTTRAPFN()
5387 PMUREV(sih->pmurev), clock)); in BCMPOSTTRAPFN()
5392 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
5399 BCMPOSTTRAPFN(si_pmu_cpu_clock)(si_t *sih, osl_t *osh) in BCMPOSTTRAPFN()
5408 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5411 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
5412 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
5413 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5415 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
5419 if (BCM4369_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5420 BCM4376_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5421 BCM4378_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5422 BCM4385_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5423 BCM4387_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5424 BCM4388_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5425 BCM4389_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5426 BCM4397_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5427 BCM4362_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
5428 clock = si_pmu1_cpuclk0_pll2(sih); /* for chips with separate CPU PLL */ in BCMPOSTTRAPFN()
5429 } else if ((PMUREV(sih->pmurev) >= 5) && in BCMPOSTTRAPFN()
5430 !((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMPOSTTRAPFN()
5431 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in BCMPOSTTRAPFN()
5432 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMPOSTTRAPFN()
5433 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMPOSTTRAPFN()
5434 (CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMPOSTTRAPFN()
5435 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMPOSTTRAPFN()
5436 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMPOSTTRAPFN()
5440 if (BCM43602_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
5441 clock = si_pmu1_cpuclk0(sih, osh, pmu); in BCMPOSTTRAPFN()
5443 clock = si_pmu5_clock(sih, osh, pmu, pll, PMU5_MAINPLL_CPU); in BCMPOSTTRAPFN()
5446 clock = si_pmu_si_clock(sih, osh); in BCMPOSTTRAPFN()
5449 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMPOSTTRAPFN()
5450 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMPOSTTRAPFN()
5451 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in BCMPOSTTRAPFN()
5456 tmp = si_pmu_chipcontrol(sih, PMU1_PLL0_CHIPCTL1, 0, 0); in BCMPOSTTRAPFN()
5465 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
5471 si_pmu_mem_ca7clock(si_t *sih, osl_t *osh) in si_pmu_mem_ca7clock() argument
5475 uint idx = si_coreidx(sih); in si_pmu_mem_ca7clock()
5477 ca7regs_t *regs = si_setcore(sih, ARMCA7_CORE_ID, 0); in si_pmu_mem_ca7clock()
5486 uint32 fvco = si_pmu_pll28nm_fvco(sih); in si_pmu_mem_ca7clock()
5487 if (si_corerev(sih) >= 7) { in si_pmu_mem_ca7clock()
5501 clock = si_pmu_si_clock(sih, osh); in si_pmu_mem_ca7clock()
5505 si_setcoreidx(sih, idx); in si_pmu_mem_ca7clock()
5513 BCMINITFN(si_pmu_mem_clock)(si_t *sih, osl_t *osh) in BCMINITFN()
5519 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMINITFN()
5522 origidx = si_coreidx(sih); in BCMINITFN()
5523 if (AOB_ENAB(sih)) { in BCMINITFN()
5524 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
5526 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMINITFN()
5530 if ((PMUREV(sih->pmurev) >= 5) && in BCMINITFN()
5531 !((BCM4369_CHIP(sih->chip)) || in BCMINITFN()
5532 (BCM4362_CHIP(sih->chip)) || in BCMINITFN()
5533 BCM43602_CHIP(sih->chip) || in BCMINITFN()
5534 (CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMINITFN()
5535 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMINITFN()
5536 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMINITFN()
5537 BCM4376_CHIP(sih->chip) || in BCMINITFN()
5538 BCM4378_CHIP(sih->chip) || in BCMINITFN()
5539 BCM4387_CHIP(sih->chip) || in BCMINITFN()
5540 BCM4388_CHIP(sih->chip) || in BCMINITFN()
5541 BCM4389_CHIP(sih->chip) || in BCMINITFN()
5542 BCM4397_CHIP(sih->chip) || in BCMINITFN()
5546 clock = si_pmu5_clock(sih, osh, pmu, pll, PMU5_MAINPLL_MEM); in BCMINITFN()
5549 clock = si_pmu_mem_ca7clock(sih, osh); in BCMINITFN()
5551 clock = si_pmu_si_clock(sih, osh); /* mem clk same as backplane clk */ in BCMINITFN()
5555 si_setcoreidx(sih, origidx); in BCMINITFN()
5586 BCMINITFN(si_pmu_ilp_clock)(si_t *sih, osl_t *osh) in BCMINITFN()
5588 if (ISSIM_ENAB(sih)) in BCMINITFN()
5594 uint origidx = si_coreidx(sih); in BCMINITFN()
5596 if (AOB_ENAB(sih)) { in BCMINITFN()
5597 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
5599 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMINITFN()
5613 si_setcoreidx(sih, origidx); in BCMINITFN()
5627 BCMPOSTTRAPFN(si_pmu_chipcontrol)(si_t *sih, uint reg, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
5629 pmu_corereg(sih, SI_CC_IDX, chipcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5630 return pmu_corereg(sih, SI_CC_IDX, chipcontrol_data, mask, val); in BCMPOSTTRAPFN()
5639 BCMPOSTTRAPFN(si_pmu_vreg_control)(si_t *sih, uint reg, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
5641 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5642 return pmu_corereg(sih, SI_CC_IDX, regcontrol_data, mask, val); in BCMPOSTTRAPFN()
5651 BCMPOSTTRAPFN(si_pmu_pllcontrol)(si_t *sih, uint reg, uint32 mask, uint32 val) in BCMPOSTTRAPFN()
5653 pmu_corereg(sih, SI_CC_IDX, pllcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5654 return pmu_corereg(sih, SI_CC_IDX, pllcontrol_data, mask, val); in BCMPOSTTRAPFN()
5667 BCMINITFN(si_sdiod_drive_strength_init)(si_t *sih, osl_t *osh, uint32 drivestrength) in BCMINITFN()
5678 UNUSED_PARAMETER(sih); in BCMINITFN()
5686 BCMATTACHFN(si_pmu_init)(si_t *sih, osl_t *osh) in BCMATTACHFN()
5691 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
5694 origidx = si_coreidx(sih); in BCMATTACHFN()
5695 if (AOB_ENAB(sih)) { in BCMATTACHFN()
5696 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5698 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
5703 si_pmu_reg_on_war_ext_wake_perst_clear(sih); in BCMATTACHFN()
5704 si_pmu_reg_on_war_ext_wake_perst_set(sih); in BCMATTACHFN()
5708 if (PMUREV(sih->pmurev) == 1) in BCMATTACHFN()
5710 else if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
5714 if ((PMUREV(sih->pmurev) >= 26) && (PMUREV(sih->pmurev) != 27)) { in BCMATTACHFN()
5716 pmu_corereg(sih, SI_CC_IDX, pmuintctrl0, val, val); in BCMATTACHFN()
5719 pmu_corereg(sih, SI_CC_IDX, pmuintmask0, val, val); in BCMATTACHFN()
5720 (void)pmu_corereg(sih, SI_CC_IDX, pmuintmask0, 0, 0); in BCMATTACHFN()
5724 si_setcoreidx(sih, origidx); in BCMATTACHFN()
5728 si_pmu_rsrc_macphy_clk_deps(si_t *sih, osl_t *osh, int macunit) in si_pmu_rsrc_macphy_clk_deps() argument
5737 origidx = si_coreidx(sih); in si_pmu_rsrc_macphy_clk_deps()
5738 if (AOB_ENAB(sih)) { in si_pmu_rsrc_macphy_clk_deps()
5739 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_rsrc_macphy_clk_deps()
5741 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_rsrc_macphy_clk_deps()
5746 rsc = si_pmu_get_rsc_positions(sih); in si_pmu_rsrc_macphy_clk_deps()
5758 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc_num), TRUE); in si_pmu_rsrc_macphy_clk_deps()
5762 si_setcoreidx(sih, origidx); in si_pmu_rsrc_macphy_clk_deps()
5768 si_pmu_set_mac_rsrc_req_sc(si_t *sih, osl_t *osh) in si_pmu_set_mac_rsrc_req_sc() argument
5777 origidx = si_coreidx(sih); in si_pmu_set_mac_rsrc_req_sc()
5778 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_mac_rsrc_req_sc()
5781 rsc = si_pmu_get_rsc_positions(sih); in si_pmu_set_mac_rsrc_req_sc()
5786 deps = si_pmu_res_deps(sih, osh, pmu, rsrc, TRUE); in si_pmu_set_mac_rsrc_req_sc()
5793 si_setcoreidx(sih, origidx); in si_pmu_set_mac_rsrc_req_sc()
5797 BCMATTACHFN(si_pmu_rsrc_ht_avail_clk_deps)(si_t *sih, osl_t *osh) in BCMATTACHFN()
5805 origidx = si_coreidx(sih); in BCMATTACHFN()
5806 if (AOB_ENAB(sih)) { in BCMATTACHFN()
5807 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5809 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
5814 rsc = si_pmu_get_rsc_positions(sih); in BCMATTACHFN()
5815 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->ht_avail), FALSE); in BCMATTACHFN()
5819 si_setcoreidx(sih, origidx); in BCMATTACHFN()
5825 BCMATTACHFN(si_pmu_rsrc_cb_ready_deps)(si_t *sih, osl_t *osh) in BCMATTACHFN()
5833 origidx = si_coreidx(sih); in BCMATTACHFN()
5834 if (AOB_ENAB(sih)) { in BCMATTACHFN()
5835 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5837 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
5842 rsc = si_pmu_get_rsc_positions(sih); in BCMATTACHFN()
5846 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->cb_ready), FALSE); in BCMATTACHFN()
5851 si_setcoreidx(sih, origidx); in BCMATTACHFN()
5857 si_pmu_set_mac_rsrc_req(si_t *sih, int macunit) in si_pmu_set_mac_rsrc_req() argument
5861 osl_t *osh = si_osh(sih); in si_pmu_set_mac_rsrc_req()
5864 origidx = si_coreidx(sih); in si_pmu_set_mac_rsrc_req()
5865 if (AOB_ENAB(sih)) { in si_pmu_set_mac_rsrc_req()
5866 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_mac_rsrc_req()
5868 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_set_mac_rsrc_req()
5874 W_REG(osh, &pmu->mac_res_req_mask, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5877 W_REG(osh, &pmu->mac_res_req_mask1, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5880 W_REG(osh, &pmu->mac_res_req_mask2, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5884 si_setcoreidx(sih, origidx); in si_pmu_set_mac_rsrc_req()
5896 BCMINITFN(si_pmu_res_uptime)(si_t *sih, osl_t *osh, in BCMINITFN()
5908 if (PMUREV(sih->pmurev) >= 30) in BCMINITFN()
5910 else if (PMUREV(sih->pmurev) >= 13) in BCMINITFN()
5916 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsrc), FALSE); in BCMINITFN()
5920 deps &= ~si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(i), TRUE); in BCMINITFN()
5923 si_pmu_res_masks(sih, &min_mask, &max_mask); in BCMINITFN()
5935 dup = si_pmu_res_uptime(sih, osh, pmu, (uint8)i, pmu_fast_trans_en); in BCMINITFN()
5951 si_pmu_res_deps(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 rsrcs, bool all) in si_pmu_res_deps() argument
5963 return !all ? deps : (deps ? (deps | si_pmu_res_deps(sih, osh, pmu, deps, TRUE)) : 0); in si_pmu_res_deps()
5967 si_pmu_otp_is_ready(si_t *sih) in si_pmu_otp_is_ready() argument
5971 if (AOB_ENAB(sih)) { in si_pmu_otp_is_ready()
5972 otps = si_corereg(sih, si_findcoreidx(sih, GCI_CORE_ID, 0u), in si_pmu_otp_is_ready()
5975 otps = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpstatus), 0u, 0u); in si_pmu_otp_is_ready()
5981 si_pmu_otp_is_ready_and_wait(si_t *sih, bool on) in si_pmu_otp_is_ready_and_wait() argument
5983 SPINWAIT((si_pmu_otp_is_ready(sih) != on), 3000u); in si_pmu_otp_is_ready_and_wait()
5985 if (si_pmu_otp_is_ready(sih) != on) { in si_pmu_otp_is_ready_and_wait()
5990 return si_pmu_otp_is_ready(sih) == on; in si_pmu_otp_is_ready_and_wait()
5999 si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask) in si_pmu_otp_power() argument
6006 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_otp_power()
6009 if (si_is_otp_disabled(sih)) { in si_pmu_otp_power()
6015 origidx = si_coreidx(sih); in si_pmu_otp_power()
6016 if (AOB_ENAB(sih)) { in si_pmu_otp_power()
6017 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_otp_power()
6019 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_otp_power()
6029 if (CCREV(sih->ccrev) == 45) { in si_pmu_otp_power()
6031 otpctrl1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), 0, 0); in si_pmu_otp_power()
6036 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), ~0, otpctrl1); in si_pmu_otp_power()
6038 si_setcoreidx(sih, origidx); in si_pmu_otp_power()
6042 switch (CHIPID(sih->chip)) { in si_pmu_otp_power()
6056 rsc = si_pmu_get_rsc_positions(sih); in si_pmu_otp_power()
6064 si_gci_direct(sih, GCI_OFFSETOF(sih, otpcontrol), OTPC_FORCE_OTP_PWR_DIS, in si_pmu_otp_power()
6066 if (!si_pmu_otp_is_ready_and_wait(sih, on)) { in si_pmu_otp_power()
6084 min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE); in si_pmu_otp_power()
6089 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_otp_power()
6109 min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE); in si_pmu_otp_power()
6114 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_otp_power()
6117 if (!si_pmu_otp_is_ready_and_wait(sih, on_check)) { in si_pmu_otp_power()
6127 ASSERT(si_pmu_otp_is_ready(sih) == on_check); in si_pmu_otp_power()
6132 si_setcoreidx(sih, origidx); in si_pmu_otp_power()
6136 si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid) in si_pmu_spuravoid() argument
6142 si_introff(sih, &intr_val); in si_pmu_spuravoid()
6143 origidx = si_coreidx(sih); in si_pmu_spuravoid()
6146 si_setcoreidx(sih, origidx); in si_pmu_spuravoid()
6147 si_intrrestore(sih, &intr_val); in si_pmu_spuravoid()
6159 si_pmu_pll28nm_fvco(si_t *sih) in si_pmu_pll28nm_fvco() argument
6162 uint32 xf = si_alp_clock(sih); in si_pmu_pll28nm_fvco()
6164 uint32 pllreg5 = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in si_pmu_pll28nm_fvco()
6165 uint32 pllreg4 = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0); in si_pmu_pll28nm_fvco()
6175 if (ISSIM_ENAB(sih)) { in si_pmu_pll28nm_fvco()
6199 si_pmu_is_otp_powered(si_t *sih, osl_t *osh) in si_pmu_is_otp_powered() argument
6207 idx = si_coreidx(sih); in si_pmu_is_otp_powered()
6208 if (AOB_ENAB(sih)) { in si_pmu_is_otp_powered()
6209 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_is_otp_powered()
6211 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_is_otp_powered()
6215 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_is_otp_powered()
6217 switch (CHIPID(sih->chip)) { in si_pmu_is_otp_powered()
6229 rsc = si_pmu_get_rsc_positions(sih); in si_pmu_is_otp_powered()
6237 st = (!(si_gci_direct(sih, GCI_OFFSETOF(sih, otpcontrol), 0u, 0u) & in si_pmu_is_otp_powered()
6238 OTPC_FORCE_OTP_PWR_DIS)) && si_pmu_otp_is_ready_and_wait(sih, TRUE); in si_pmu_is_otp_powered()
6246 si_setcoreidx(sih, idx); in si_pmu_is_otp_powered()
6255 BCMATTACHFN(si_pmu_set_lpoclk)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6267 origidx = si_coreidx(sih); in BCMATTACHFN()
6268 if (AOB_ENAB(sih)) { in BCMATTACHFN()
6269 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
6271 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
6282 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6285 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU43602_CC2_XTAL32_SEL, in BCMATTACHFN()
6290 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_EXT_LPO_PU, CC_EXT_LPO_PU); in BCMATTACHFN()
6291 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_EXT_LPO_PU, GC_EXT_LPO_PU); in BCMATTACHFN()
6309 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6311 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU43602_CC2_FORCE_EXT_LPO, in BCMATTACHFN()
6316 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, EXT_LPO_SEL); in BCMATTACHFN()
6318 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0); in BCMATTACHFN()
6332 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6334 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, in BCMATTACHFN()
6338 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0); in BCMATTACHFN()
6343 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6347 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_INT_LPO_PU, 0x0); in BCMATTACHFN()
6348 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_INT_LPO_PU, 0x0); in BCMATTACHFN()
6354 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6359 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_INT_LPO_PU, CC_INT_LPO_PU); in BCMATTACHFN()
6360 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_INT_LPO_PU, GC_INT_LPO_PU); in BCMATTACHFN()
6365 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, INT_LPO_SEL); in BCMATTACHFN()
6367 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0); in BCMATTACHFN()
6381 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0); in BCMATTACHFN()
6384 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_EXT_LPO_PU, 0x0); in BCMATTACHFN()
6385 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_EXT_LPO_PU, 0x0); in BCMATTACHFN()
6389 if ((PMUREV(sih->pmurev) >= 33)) { in BCMATTACHFN()
6391 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTSEQ_ENAB, PCTL_EXT_FASTSEQ_ENAB); in BCMATTACHFN()
6396 si_setcoreidx(sih, origidx); in BCMATTACHFN()
6400 si_pmu_fast_lpo_locked(si_t *sih, osl_t *osh) in si_pmu_fast_lpo_locked() argument
6403 switch (CHIPID(sih->chip)) { in si_pmu_fast_lpo_locked()
6407 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in si_pmu_fast_lpo_locked()
6412 lock = si_gci_chipstatus(sih, GCI_CHIPSTATUS_13) & GCI_CS_4369_FLL1MHZ_LOCK_MASK; in si_pmu_fast_lpo_locked()
6419 lock = si_gci_chipstatus(sih, GCI_CHIPSTATUS_15) & GCI_CS_4387_FLL1MHZ_LOCK_MASK; in si_pmu_fast_lpo_locked()
6429 BCMATTACHFN(si_pmu_fast_lpo_enable)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6436 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6440 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_ENAB, PCTL_EXT_FASTLPO_ENAB); in BCMATTACHFN()
6441 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in BCMATTACHFN()
6445 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in BCMATTACHFN()
6457 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, PCTL_EXT_FASTLPO_SWENAB); in BCMATTACHFN()
6473 if ((LHLREV(sih->lhlrev) >= 6) && !PMU_FLL_PU_ENAB()) { in BCMATTACHFN()
6474 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, in BCMATTACHFN()
6478 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_ENAB, PCTL_EXT_FASTLPO_ENAB); in BCMATTACHFN()
6480 lock = si_pmu_fast_lpo_locked(sih, osh); in BCMATTACHFN()
6482 lock = si_pmu_fast_lpo_locked(sih, osh); in BCMATTACHFN()
6490 PMU_REG(sih, pmucontrol_ext, in BCMATTACHFN()
6505 BCMATTACHFN(si_pmu_fast_lpo_enable_pcie)(si_t *sih) in BCMATTACHFN()
6511 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6524 PMU_REG(sih, pmucontrol_ext, in BCMATTACHFN()
6541 BCMATTACHFN(si_pmu_fast_lpo_enable_pmu)(si_t *sih) in BCMATTACHFN()
6547 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6603 BCMATTACHFN(si_pmu_fll_preload_enable)(si_t *sih) in BCMATTACHFN()
6609 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6616 fll_dac_out = (si_gci_chipstatus(sih, GCI_CHIPSTATUS_15) & in BCMATTACHFN()
6620 LHL_REG(sih, lhl_wl_hw_ctl_adr[1], in BCMATTACHFN()
6623 LHL_REG(sih, lhl_wl_hw_ctl_adr[1], in BCMATTACHFN()
6642 BCMATTACHFN(si_set_lv_sleep_mode_pmu)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6645 if (BCM4369_CHIP(sih->chip) && (CHIPREV(sih->chiprev) == 0)) { in BCMATTACHFN()
6646 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON, 0); in BCMATTACHFN()
6660 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK, in BCMATTACHFN()
6662 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK, in BCMATTACHFN()
6664 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK, in BCMATTACHFN()
6666 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4369_VREG16_RSRC2_ABUCK_MODE_MASK, in BCMATTACHFN()
6670 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK, in BCMATTACHFN()
6674 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN0_ASR_MASK, in BCMATTACHFN()
6676 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN1_ASR_MASK, in BCMATTACHFN()
6678 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN2_ASR_MASK, in BCMATTACHFN()
6681 si_pmu_vreg_control(sih, PMU_VREG_14, PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK, in BCMATTACHFN()
6685 si_pmu_vreg_control(sih, PMU_VREG_7, in BCMATTACHFN()
6693 if (!(BCM4389_CHIP(sih->chip) || BCM4388_CHIP(sih->chip) || BCM4397_CHIP(sih->chip) || in BCMATTACHFN()
6694 BCM4387_CHIP(sih->chip))) { in BCMATTACHFN()
6695 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK, in BCMATTACHFN()
6696 ((CHIPREV(sih->chiprev) == 0) ? 1 : 0) << in BCMATTACHFN()
6699 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4369_VREG_5_LPLDO_POWER_UP_MASK, 0x0u); in BCMATTACHFN()
6700 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK, in BCMATTACHFN()
6702 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_MASK, in BCMATTACHFN()
6706 si_pmu_vreg_control(sih, PMU_VREG_6, PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK, in BCMATTACHFN()
6715 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6719 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6725 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in BCMATTACHFN()
6735 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6739 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6743 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6749 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
6754 BCMATTACHFN(si_set_lv_sleep_mode_4369)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6756 si_set_lv_sleep_mode_pmu(sih, osh); in BCMATTACHFN()
6758 si_set_lv_sleep_mode_lhl_config_4369(sih); in BCMATTACHFN()
6761 CHIPC_REG(sih, intmask, (1u << 4u), (1u << 4u)); in BCMATTACHFN()
6764 void si_set_abuck_mode_4362(si_t *sih, uint8 mode) in si_set_abuck_mode_4362() argument
6772 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4362_VREG16_RSRC0_ABUCK_MODE_MASK, in si_set_abuck_mode_4362()
6774 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4362_VREG16_RSRC1_ABUCK_MODE_MASK, in si_set_abuck_mode_4362()
6776 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4362_VREG16_RSRC2_ABUCK_MODE_MASK, in si_set_abuck_mode_4362()
6781 BCMATTACHFN(si_set_lv_sleep_mode_4378)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6783 si_set_lv_sleep_mode_pmu(sih, osh); in BCMATTACHFN()
6785 si_set_lv_sleep_mode_lhl_config_4378(sih); in BCMATTACHFN()
6789 BCMATTACHFN(si_set_lv_sleep_mode_pmu_4387)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6794 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK, in BCMATTACHFN()
6798 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK, in BCMATTACHFN()
6802 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN0_ASR_MASK, in BCMATTACHFN()
6804 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN1_ASR_MASK, in BCMATTACHFN()
6806 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4369_VREG13_RSRC_EN2_ASR_MASK, in BCMATTACHFN()
6809 si_pmu_vreg_control(sih, PMU_VREG_14, PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK, in BCMATTACHFN()
6813 si_pmu_vreg_control(sih, PMU_VREG_7, in BCMATTACHFN()
6818 si_pmu_vreg_control(sih, PMU_VREG_6, PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK, in BCMATTACHFN()
6824 if (PMUREV(sih->pmurev) < 39) { in BCMATTACHFN()
6831 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6837 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6844 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in BCMATTACHFN()
6858 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6863 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6867 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6871 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6874 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in BCMATTACHFN()
6877 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6890 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in BCMATTACHFN()
6897 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6903 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in BCMATTACHFN()
6908 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
6914 if (PMUREV(sih->pmurev) == 38) { in BCMATTACHFN()
6915 si_pmu_vreg_control(sih, PMU_VREG_14, in BCMATTACHFN()
6921 si_pmu_vreg_control(sih, PMU_VREG_1, in BCMATTACHFN()
6926 si_pmu_vreg_control(sih, PMU_VREG_5, VREG5_4387_MISCLDO_PU_MASK, 0); in BCMATTACHFN()
6928 si_pmu_vreg_control(sih, PMU_VREG_8, in BCMATTACHFN()
6933 si_pmu_vreg_control(sih, PMU_VREG_6, in BCMATTACHFN()
6937 si_pmu_vreg_control(sih, PMU_VREG_6, in BCMATTACHFN()
6940 si_pmu_vreg_control(sih, PMU_VREG_6, in BCMATTACHFN()
6947 BCMATTACHFN(si_set_lv_sleep_mode_4387)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6949 si_set_lv_sleep_mode_pmu_4387(sih, osh); in BCMATTACHFN()
6950 si_set_lv_sleep_mode_lhl_config_4387(sih); in BCMATTACHFN()
6954 BCMATTACHFN(si_set_lv_sleep_mode_4389)(si_t *sih, osl_t *osh) in BCMATTACHFN()
6956 si_set_lv_sleep_mode_pmu(sih, osh); in BCMATTACHFN()
6958 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
6962 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in BCMATTACHFN()
6965 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
6969 si_pmu_chipcontrol(sih, PMU_CHIPCTL12, in BCMATTACHFN()
6972 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6980 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
6990 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in BCMATTACHFN()
6997 si_set_lv_sleep_mode_lhl_config_4389(sih); in BCMATTACHFN()
6999 si_pmu_vreg_control(sih, PMU_VREG_6, in BCMATTACHFN()
7004 if (CHIPREV(sih->chiprev) == 1) { in BCMATTACHFN()
7005 si_pmu_vreg_control(sih, PMU_VREG_1, in BCMATTACHFN()
7009 si_pmu_vreg_control(sih, PMU_VREG_8, in BCMATTACHFN()
7016 BCMATTACHFN(si_set_lv_sleep_mode_4362)(si_t *sih, osl_t *osh) in BCMATTACHFN()
7021 si_pmu_vreg_control(sih, PMU_VREG_16, PMU_4362_VREG16_RSRC0_CBUCK_MODE_MASK, in BCMATTACHFN()
7024 si_set_abuck_mode_4362(sih, 0x3u); in BCMATTACHFN()
7027 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK, in BCMATTACHFN()
7031 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4362_VREG13_RSRC_EN0_ASR_MASK, in BCMATTACHFN()
7033 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4362_VREG13_RSRC_EN1_ASR_MASK, in BCMATTACHFN()
7035 si_pmu_vreg_control(sih, PMU_VREG_13, PMU_4362_VREG13_RSRC_EN2_ASR_MASK, in BCMATTACHFN()
7038 si_pmu_vreg_control(sih, PMU_VREG_14, PMU_4362_VREG14_RSRC_EN_CSR_MASK0_MASK, in BCMATTACHFN()
7042 si_pmu_vreg_control(sih, PMU_VREG_7, in BCMATTACHFN()
7047 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4362_VREG_5_MISCLDO_POWER_UP_MASK, in BCMATTACHFN()
7049 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4362_VREG_5_LPLDO_POWER_UP_MASK, 0x0u); in BCMATTACHFN()
7050 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK, in BCMATTACHFN()
7054 si_pmu_vreg_control(sih, PMU_VREG_6, PMU_4362_VREG_6_MEMLPLDO_POWER_UP_MASK, in BCMATTACHFN()
7063 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in BCMATTACHFN()
7069 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, in BCMATTACHFN()
7079 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
7083 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMATTACHFN()
7089 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
7092 si_set_lv_sleep_mode_lhl_config_4362(sih); in BCMATTACHFN()
7095 CHIPC_REG(sih, intmask, (1u << 4u), (1u << 4u)); in BCMATTACHFN()
7099 BCMATTACHFN(si_pmu_fis_setup)(si_t *sih) in BCMATTACHFN()
7104 osl_t *osh = si_osh(sih); in BCMATTACHFN()
7106 origidx = si_coreidx(sih); in BCMATTACHFN()
7107 if (AOB_ENAB(sih)) { in BCMATTACHFN()
7108 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7110 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
7114 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7153 si_setcoreidx(sih, origidx); in BCMATTACHFN()
7163 BCMATTACHFN(si_pmu_dynamic_clk_switch_enab)(si_t *sih) in BCMATTACHFN()
7165 if (PMUREV(sih->pmurev) >= 36) { in BCMATTACHFN()
7167 PMU_REG(sih, pmucontrol_ext, in BCMATTACHFN()
7169 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, in BCMATTACHFN()
7179 BCMATTACHFN(si_pmu_enb_slp_cnt_on_rsrc)(si_t *sih, osl_t *osh) in BCMATTACHFN()
7185 origidx = si_coreidx(sih); in BCMATTACHFN()
7186 if (AOB_ENAB(sih)) { in BCMATTACHFN()
7187 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7189 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
7193 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7219 si_setcoreidx(sih, origidx); in BCMATTACHFN()
7226 BCMATTACHFN(si_pmu_chip_init)(si_t *sih, osl_t *osh) in BCMATTACHFN()
7228 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
7229 if (AOB_ENAB(sih)) { in BCMATTACHFN()
7231 uint coreidx = si_coreidx(sih); in BCMATTACHFN()
7232 hnd_pmur = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7235 si_setcoreidx(sih, coreidx); in BCMATTACHFN()
7239 si_pmu_otp_chipcontrol(sih, osh); in BCMATTACHFN()
7242 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP); in BCMATTACHFN()
7245 si_pmu_enb_slp_cnt_on_rsrc(sih, osh); in BCMATTACHFN()
7248 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7255 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_LHL_TIMER_SELECT, in BCMATTACHFN()
7258 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_LHL_TIMER_SELECT, 0); in BCMATTACHFN()
7261 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON, 0); in BCMATTACHFN()
7262 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL14_43012_DISABLE_LQ_AVAIL, 0); in BCMATTACHFN()
7264 PMU_REG_NEW(sih, extwakemask0, in BCMATTACHFN()
7266 PMU_REG_NEW(sih, extwakereqmask[0], ~0, si_pmu_rsrc_ht_avail_clk_deps(sih, osh)); in BCMATTACHFN()
7268 if (sih->lpflags & LPFLAGS_SI_FORCE_PWM_WHEN_RADIO_ON) { in BCMATTACHFN()
7271 si_pmu_vreg_control(sih, PMU_VREG_8, in BCMATTACHFN()
7274 si_pmu_vreg_control(sih, PMU_VREG_9, in BCMATTACHFN()
7280 si_pmu_chipcontrol(sih, PMU_CHIPCTL16, PMU_CC16_CLK4M_DIS, 1); in BCMATTACHFN()
7281 si_pmu_chipcontrol(sih, PMU_CHIPCTL16, PMU_CC16_FF_ZERO_ADJ, 4); in BCMATTACHFN()
7283 si_pmu_vreg_control(sih, PMU_VREG_8, in BCMATTACHFN()
7286 si_pmu_vreg_control(sih, PMU_VREG_9, in BCMATTACHFN()
7291 si_lhl_set_lpoclk(sih, osh, LHL_LPO_AUTO); in BCMATTACHFN()
7294 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB, in BCMATTACHFN()
7297 si_pmu_chipcontrol(sih, PMU_CHIPCTL9, in BCMATTACHFN()
7303 si_pmu_vreg_control(sih, PMU_VREG_6, VREG6_43012_MEMLPLDO_ADJ_MASK, in BCMATTACHFN()
7307 si_pmu_vreg_control(sih, PMU_VREG_6, VREG6_43012_LPLDO_ADJ_MASK, in BCMATTACHFN()
7311 si_pmu_vreg_control(sih, PMU_VREG_7, VREG7_43012_PWRSW_1P8_PU_MASK, 0); in BCMATTACHFN()
7314 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, ~0, PMU_SLEEP_MODE_0); in BCMATTACHFN()
7316 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7319 GCI_REG_NEW(sih, bt_smem_control0, GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL, in BCMATTACHFN()
7326 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7341 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_LHL_TIMER_SELECT, lhl_tmr_sel); in BCMATTACHFN()
7347 if (!ISSIM_ENAB(sih)) { in BCMATTACHFN()
7348 si_lhl_set_lpoclk(sih, osh, lpo); in BCMATTACHFN()
7352 si_pmu_regcontrol(sih, 4, in BCMATTACHFN()
7355 si_pmu_regcontrol(sih, 6, in BCMATTACHFN()
7361 si_pmu_chipcontrol_xtal_settings_4362(sih); in BCMATTACHFN()
7363 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
7367 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK, in BCMATTACHFN()
7369 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4362_VREG8_ASR_OVADJ_PFM_MASK, in BCMATTACHFN()
7371 si_pmu_vreg_control(sih, PMU_VREG_8, PMU_4362_VREG8_ASR_OVADJ_PWM_MASK, in BCMATTACHFN()
7375 si_set_lv_sleep_mode_4362(sih, osh); in BCMATTACHFN()
7379 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7380 if ((PMUREV(sih->pmurev) >= 33) && FASTLPO_ENAB()) { in BCMATTACHFN()
7385 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTSEQ_ENAB, in BCMATTACHFN()
7395 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7412 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4369_LHL_TIMER_SELECT, lhl_tmr_sel); in BCMATTACHFN()
7418 if (!ISSIM_ENAB(sih)) { in BCMATTACHFN()
7419 si_lhl_set_lpoclk(sih, osh, lpo); in BCMATTACHFN()
7423 si_pmu_regcontrol(sih, 4, in BCMATTACHFN()
7426 si_pmu_regcontrol(sih, 6, in BCMATTACHFN()
7432 si_pmu_chipcontrol_xtal_settings_4369(sih); in BCMATTACHFN()
7434 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in BCMATTACHFN()
7439 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
7440 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK, in BCMATTACHFN()
7446 si_set_lv_sleep_mode_4369(sih, osh); in BCMATTACHFN()
7450 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7452 if (CHIPID(sih->chip) != BCM4377_CHIP_ID) { in BCMATTACHFN()
7453 si_pmu_ldo3p3_soft_start_wl_set(sih, osh, 3); in BCMATTACHFN()
7456 if ((PMUREV(sih->pmurev) >= 33) && FASTLPO_ENAB()) { in BCMATTACHFN()
7461 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FASTSEQ_ENAB, in BCMATTACHFN()
7471 si_pmu_set_lpoclk(sih, osh); in BCMATTACHFN()
7477 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7484 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4378_LHL_TIMER_SELECT, lhl_tmr_sel); in BCMATTACHFN()
7490 if (!ISSIM_ENAB(sih)) { in BCMATTACHFN()
7491 si_lhl_set_lpoclk(sih, osh, lpo); in BCMATTACHFN()
7497 si_pmu_bt_ldo_pu(sih, FALSE); in BCMATTACHFN()
7500 si_pmu_chipcontrol_xtal_settings_4378(sih); in BCMATTACHFN()
7502 if (LHL_IS_PSMODE_1(sih)) { in BCMATTACHFN()
7503 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_07, in BCMATTACHFN()
7509 si_lhl_setup(sih, osh); in BCMATTACHFN()
7517 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4378_MEMLPLDO_ADJ_MASK, in BCMATTACHFN()
7530 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4378_LPLDO_ADJ_MASK, in BCMATTACHFN()
7538 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7542 si_set_lv_sleep_mode_4378(sih, osh); in BCMATTACHFN()
7546 si_pmu_dynamic_clk_switch_enab(sih); in BCMATTACHFN()
7548 if (CHIPID(sih->chip) == BCM4378_CHIP_GRPID) { in BCMATTACHFN()
7549 si_pmu_vreg_control(sih, PMU_VREG_0, in BCMATTACHFN()
7560 si_pmu_ldo3p3_soft_start_wl_set(sih, osh, 0x03u); in BCMATTACHFN()
7561 si_pmu_ldo3p3_soft_start_bt_set(sih, osh, 0x03u); in BCMATTACHFN()
7567 si_pmu_vreg_control(sih, PMU_VREG_0, in BCMATTACHFN()
7582 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7590 si_set_arm_clkfreq_high(sih); in BCMATTACHFN()
7603 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_LHL_TIMER_SELECT, lhl_tmr_sel); in BCMATTACHFN()
7607 si_set_lv_sleep_mode_4387(sih, osh); in BCMATTACHFN()
7615 if (!ISSIM_ENAB(sih)) { in BCMATTACHFN()
7616 si_lhl_set_lpoclk(sih, osh, lpo); in BCMATTACHFN()
7620 si_pmu_regcontrol(sih, 4, in BCMATTACHFN()
7623 si_pmu_regcontrol(sih, 6, in BCMATTACHFN()
7628 if (LHL_IS_PSMODE_1(sih)) { in BCMATTACHFN()
7629 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_07, in BCMATTACHFN()
7635 si_lhl_setup(sih, osh); in BCMATTACHFN()
7643 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4387_MEMLPLDO_ADJ_MASK, in BCMATTACHFN()
7656 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4387_LPLDO_ADJ_MASK, in BCMATTACHFN()
7664 curr_misc_ldo_volt = (si_pmu_regcontrol(sih, PMU_VREG_5, 0, 0) & in BCMATTACHFN()
7672 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4387_MISC_LDO_ADJ_MASK, in BCMATTACHFN()
7679 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7684 si_pmu_fll_preload_enable(sih); in BCMATTACHFN()
7687 si_pmu_dynamic_clk_switch_enab(sih); in BCMATTACHFN()
7690 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_25, in BCMATTACHFN()
7694 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_26, in BCMATTACHFN()
7698 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_ENAB_RADIO_REG_CLK, 0); in BCMATTACHFN()
7705 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_16, in BCMATTACHFN()
7713 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_17, in BCMATTACHFN()
7720 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_20, in BCMATTACHFN()
7724 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7726 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_28, in BCMATTACHFN()
7737 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7739 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_28, in BCMATTACHFN()
7745 if (sih->chip != BCM4397_CHIP_ID) { in BCMATTACHFN()
7746 si_pmu_vreg_control(sih, PMU_VREG_13, in BCMATTACHFN()
7757 si_pmu_vreg_control(sih, PMU_VREG_0, in BCMATTACHFN()
7762 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FAST_TRANS_ENAB, PCTL_EXT_FAST_TRANS_ENAB); in BCMATTACHFN()
7764 if (si_hib_ext_wakeup_isenab(sih)) { in BCMATTACHFN()
7768 si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsrc_num), TRUE); in BCMATTACHFN()
7772 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in BCMATTACHFN()
7782 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7798 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_LHL_TIMER_SELECT, lhl_tmr_sel); in BCMATTACHFN()
7802 si_set_lv_sleep_mode_4389(sih, osh); in BCMATTACHFN()
7806 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU_CC2_CB2WL_INTR_PWRREQ_EN, in BCMATTACHFN()
7813 if (!ISSIM_ENAB(sih)) { in BCMATTACHFN()
7814 si_lhl_set_lpoclk(sih, osh, lpo); in BCMATTACHFN()
7818 si_pmu_regcontrol(sih, 4, in BCMATTACHFN()
7821 si_pmu_regcontrol(sih, 6, in BCMATTACHFN()
7826 if (LHL_IS_PSMODE_1(sih)) { in BCMATTACHFN()
7827 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_07, in BCMATTACHFN()
7833 si_lhl_setup(sih, osh); in BCMATTACHFN()
7841 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4387_MEMLPLDO_ADJ_MASK, in BCMATTACHFN()
7854 si_pmu_regcontrol(sih, PMU_VREG_5, VREG5_4387_LPLDO_ADJ_MASK, in BCMATTACHFN()
7862 si_pmu_fast_lpo_enable(sih, osh); in BCMATTACHFN()
7867 si_pmu_fll_preload_enable(sih); in BCMATTACHFN()
7870 si_pmu_dynamic_clk_switch_enab(sih); in BCMATTACHFN()
7873 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_25, in BCMATTACHFN()
7877 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_26, in BCMATTACHFN()
7881 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_ENAB_RADIO_REG_CLK, 0); in BCMATTACHFN()
7888 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_16, in BCMATTACHFN()
7896 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_17, in BCMATTACHFN()
7903 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_20, in BCMATTACHFN()
7913 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7915 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_28, in BCMATTACHFN()
7921 if (sih->chip != BCM4397_CHIP_ID) { in BCMATTACHFN()
7922 si_pmu_vreg_control(sih, PMU_VREG_13, in BCMATTACHFN()
7934 si_pmu_vreg_control(sih, PMU_VREG_0, in BCMATTACHFN()
7939 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_FAST_TRANS_ENAB, PCTL_EXT_FAST_TRANS_ENAB); in BCMATTACHFN()
7941 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
7942 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_04, in BCMATTACHFN()
7956 si_pmu_openloop_cal(si_t *sih, uint16 currtemp) in si_pmu_openloop_cal() argument
7959 switch (CHIPID(sih->chip)) { in si_pmu_openloop_cal()
7963 err = si_pmu_openloop_cal_43012(sih, currtemp); in si_pmu_openloop_cal()
7974 si_pmu_openloop_cal_43012(si_t *sih, uint16 currtemp) in si_pmu_openloop_cal_43012() argument
7982 osl_t *osh = si_osh(sih); in si_pmu_openloop_cal_43012()
7983 uint32 final_dco_code = si_get_openloop_dco_code(sih); in si_pmu_openloop_cal_43012()
7985 xtal = si_xtalfreq(sih); in si_pmu_openloop_cal_43012()
7988 origidx = si_coreidx(sih); in si_pmu_openloop_cal_43012()
7989 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_openloop_cal_43012()
7999 SPINWAIT(((si_corereg(sih, SI_CC_IDX, in si_pmu_openloop_cal_43012()
8002 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_openloop_cal_43012()
8008 si_pmu_pll_off_43012(sih, osh, pmu); in si_pmu_openloop_cal_43012()
8014 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 100, in si_pmu_openloop_cal_43012()
8023 si_pmu_pll_on_43012(sih, osh, pmu, 1); in si_pmu_openloop_cal_43012()
8027 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_openloop_cal_43012()
8029 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, ~0, pll_reg); in si_pmu_openloop_cal_43012()
8033 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, ~0, pll_reg); in si_pmu_openloop_cal_43012()
8037 dco_code = (si_gci_chipstatus(sih, GCI_CHIPSTATUS_07)); in si_pmu_openloop_cal_43012()
8060 si_pmu_pll_off_43012(sih, osh, pmu); in si_pmu_openloop_cal_43012()
8064 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 0, in si_pmu_openloop_cal_43012()
8071 si_pmu_pll_on_43012(sih, osh, pmu, 0); in si_pmu_openloop_cal_43012()
8077 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in si_pmu_openloop_cal_43012()
8084 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, in si_pmu_openloop_cal_43012()
8089 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0x00004000, (1<<14)); in si_pmu_openloop_cal_43012()
8100 si_restore_core(sih, origidx, &intr_val); in si_pmu_openloop_cal_43012()
8101 si_set_openloop_dco_code(sih, final_dco_code); in si_pmu_openloop_cal_43012()
8107 si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh) in si_pmu_slow_clk_reinit() argument
8115 if (!PMUCTL_ENAB(sih)) in si_pmu_slow_clk_reinit()
8118 origidx = si_coreidx(sih); in si_pmu_slow_clk_reinit()
8119 cc = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_slow_clk_reinit()
8129 switch (CHIPID(sih->chip)) { in si_pmu_slow_clk_reinit()
8138 xtalfreq = si_pmu_measure_alpclk(sih, osh); in si_pmu_slow_clk_reinit()
8139 si_pmu_enb_slow_clk(sih, osh, xtalfreq); in si_pmu_slow_clk_reinit()
8141 si_setcoreidx(sih, origidx); in si_pmu_slow_clk_reinit()
8147 BCMATTACHFN(si_pmu_swreg_init)(si_t *sih, osl_t *osh) in BCMATTACHFN()
8149 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
8151 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
8154 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_PAREF, 0x0c); in BCMATTACHFN()
8157 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_04, GPIO_DRIVE_4378_MASK, in BCMATTACHFN()
8165 si_pmu_set_avs(sih); in BCMATTACHFN()
8172 si_pmu_otp_vreg_control(sih, osh); in BCMATTACHFN()
8177 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk, uint32 delay_val) in si_pmu_waitforclk_on_backplane() argument
8183 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_waitforclk_on_backplane()
8185 origidx = si_coreidx(sih); in si_pmu_waitforclk_on_backplane()
8186 if (AOB_ENAB(sih)) { in si_pmu_waitforclk_on_backplane()
8187 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_waitforclk_on_backplane()
8189 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_waitforclk_on_backplane()
8198 si_setcoreidx(sih, origidx); in si_pmu_waitforclk_on_backplane()
8209 BCMATTACHFN(si_pmu_measure_alpclk)(si_t *sih, osl_t *osh) in BCMATTACHFN()
8216 if (PMUREV(sih->pmurev) < 10) in BCMATTACHFN()
8219 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
8222 origidx = si_coreidx(sih); in BCMATTACHFN()
8223 if (AOB_ENAB(sih)) { in BCMATTACHFN()
8224 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
8226 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMATTACHFN()
8230 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
8231 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
8232 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMATTACHFN()
8233 (PMUREV(sih->pmurev) >= 22)) in BCMATTACHFN()
8262 si_setcoreidx(sih, origidx); in BCMATTACHFN()
8269 si_pmu_res_minmax_update(si_t *sih, osl_t *osh) in si_pmu_res_minmax_update() argument
8277 si_introff(sih, &intr_val); in si_pmu_res_minmax_update()
8279 origidx = si_coreidx(sih); in si_pmu_res_minmax_update()
8280 if (AOB_ENAB(sih)) { in si_pmu_res_minmax_update()
8281 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_res_minmax_update()
8283 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_res_minmax_update()
8287 switch (CHIPID(sih->chip)) { in si_pmu_res_minmax_update()
8305 si_pmu_res_masks(sih, &min_mask, &max_mask); in si_pmu_res_minmax_update()
8313 min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, FALSE); in si_pmu_res_minmax_update()
8317 max_mask |= si_pmu_res_deps(sih, osh, pmu, max_mask, FALSE); in si_pmu_res_minmax_update()
8321 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_res_minmax_update()
8324 si_setcoreidx(sih, origidx); in si_pmu_res_minmax_update()
8325 si_intrrestore(sih, &intr_val); in si_pmu_res_minmax_update()
8394 BCMATTACHFN(si_pmu_dump_buf_size_pmucap)(si_t *sih) in BCMATTACHFN()
8400 if (PMUREV(sih->pmurev) < 5) in BCMATTACHFN()
8404 cnt = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMATTACHFN()
8409 cnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
8415 cnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
8421 cnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMATTACHFN()
8436 if ((PMUREV(sih->pmurev) > 27) && ARRAYSIZE(pmuregsdump) != 0) { in BCMATTACHFN()
8437 uint8 rsrc_cnt = si_pmu_get_mac_rsrc_req_tmr_cnt(sih); in BCMATTACHFN()
8449 si_pmu_get_pmu_interrupt_rcv_cnt(sih) > 1) { in BCMATTACHFN()
8466 BCMPOSTTRAPFN(si_pmu_dump_pmucap_binary)(si_t *sih, uchar *p) in BCMPOSTTRAPFN()
8478 if (PMUREV(sih->pmurev) < 5) in BCMPOSTTRAPFN()
8481 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
8483 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
8484 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
8487 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
8491 osh = si_osh(sih); in BCMPOSTTRAPFN()
8493 cnt = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMPOSTTRAPFN()
8503 cnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMPOSTTRAPFN()
8507 *p32++ = si_pmu_pllcontrol(sih, i, 0, 0); in BCMPOSTTRAPFN()
8511 cnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMPOSTTRAPFN()
8515 *p32++ = si_pmu_vreg_control(sih, i, 0, 0); in BCMPOSTTRAPFN()
8518 cnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMPOSTTRAPFN()
8522 *p32++ = si_pmu_chipcontrol(sih, i, 0, 0); in BCMPOSTTRAPFN()
8529 addr = (uint32 *)(SI_ENUM_BASE(sih) + chipc_regs_to_dump[i]); in BCMPOSTTRAPFN()
8535 if ((PMUREV(sih->pmurev) > 27)) { in BCMPOSTTRAPFN()
8544 mac_res_cnt = si_pmu_get_mac_rsrc_req_tmr_cnt(sih); in BCMPOSTTRAPFN()
8565 pmu_int_rcv_cnt = si_pmu_get_pmu_interrupt_rcv_cnt(sih); in BCMPOSTTRAPFN()
8583 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
8593 si_pmu_min_res_set(si_t *sih, osl_t *osh, uint min_mask, bool set) in si_pmu_min_res_set() argument
8601 si_introff(sih, &intr_val); in si_pmu_min_res_set()
8604 origidx = si_coreidx(sih); in si_pmu_min_res_set()
8605 if (AOB_ENAB(sih)) { in si_pmu_min_res_set()
8606 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_min_res_set()
8608 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_min_res_set()
8612 si_pmu_res_masks(sih, &min_res, &max_res); in si_pmu_min_res_set()
8613 min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE); in si_pmu_min_res_set()
8626 si_pmu_wait_for_steady_state(sih, osh, pmu); in si_pmu_min_res_set()
8629 si_setcoreidx(sih, origidx); in si_pmu_min_res_set()
8630 si_intrrestore(sih, &intr_val); in si_pmu_min_res_set()
8636 si_pmu_bt_ldo_pu(si_t *sih, bool up) in si_pmu_bt_ldo_pu() argument
8638 si_pmu_regcontrol(sih, PMU_VREG_6, PMU_28NM_VREG6_BTLDO3P3_PU, in si_pmu_bt_ldo_pu()
8643 int si_pmu_ldo3p3_soft_start_wl_get(si_t *sih, osl_t *osh, int *res) in si_pmu_ldo3p3_soft_start_wl_get() argument
8646 return si_pmu_ldo3p3_soft_start_get(sih, osh, bt_or_wl, res); in si_pmu_ldo3p3_soft_start_wl_get()
8649 int si_pmu_ldo3p3_soft_start_bt_get(si_t *sih, osl_t *osh, int *res) in si_pmu_ldo3p3_soft_start_bt_get() argument
8652 return si_pmu_ldo3p3_soft_start_get(sih, osh, bt_or_wl, res); in si_pmu_ldo3p3_soft_start_bt_get()
8656 si_pmu_soft_start_params(si_t *sih, uint32 bt_or_wl, uint *en_reg, uint32 *en_shift, in si_pmu_soft_start_params() argument
8659 switch (CHIPID(sih->chip)) { in si_pmu_soft_start_params()
8678 if (BCM4378_CHIP(sih->chip) && PMUREV(sih->pmurev) == 37) { in si_pmu_soft_start_params()
8702 static int si_pmu_ldo3p3_soft_start_get(si_t *sih, osl_t *osh, uint32 bt_or_wl, int *res) in si_pmu_ldo3p3_soft_start_get() argument
8707 int ret = si_pmu_soft_start_params(sih, bt_or_wl, &en_reg, &en_shift, &en_mask, &en_val, in si_pmu_ldo3p3_soft_start_get()
8713 soft_start_en = (si_pmu_vreg_control(sih, en_reg, 0, 0) >> en_shift); in si_pmu_ldo3p3_soft_start_get()
8719 slew_rate = (si_pmu_vreg_control(sih, val_reg, 0, 0) >> val_shift); in si_pmu_ldo3p3_soft_start_get()
8728 int si_pmu_ldo3p3_soft_start_wl_set(si_t *sih, osl_t *osh, uint32 slew_rate) in si_pmu_ldo3p3_soft_start_wl_set() argument
8731 return si_pmu_ldo3p3_soft_start_set(sih, osh, bt_or_wl, slew_rate); in si_pmu_ldo3p3_soft_start_wl_set()
8734 int si_pmu_ldo3p3_soft_start_bt_set(si_t *sih, osl_t *osh, uint32 slew_rate) in si_pmu_ldo3p3_soft_start_bt_set() argument
8737 return si_pmu_ldo3p3_soft_start_set(sih, osh, bt_or_wl, slew_rate); in si_pmu_ldo3p3_soft_start_bt_set()
8740 static int si_pmu_ldo3p3_soft_start_set(si_t *sih, osl_t *osh, uint32 bt_or_wl, uint32 slew_rate) in si_pmu_ldo3p3_soft_start_set() argument
8744 int ret = si_pmu_soft_start_params(sih, bt_or_wl, &en_reg, &en_shift, &en_mask, &en_val, in si_pmu_ldo3p3_soft_start_set()
8760 si_pmu_vreg_control(sih, en_reg, (en_mask << en_shift), (dis_val << en_shift)); in si_pmu_ldo3p3_soft_start_set()
8763 si_pmu_vreg_control(sih, val_reg, (val_mask << val_shift), in si_pmu_ldo3p3_soft_start_set()
8767 si_pmu_vreg_control(sih, en_reg, (en_mask << en_shift), (en_val << en_shift)); in si_pmu_ldo3p3_soft_start_set()
8774 si_pmu_vreg_control(sih, en_reg, (en_mask << en_shift), (dis_val << en_shift)); in si_pmu_ldo3p3_soft_start_set()
8777 si_pmu_vreg_control(sih, val_reg, (val_mask << val_shift), 0u); in si_pmu_ldo3p3_soft_start_set()
8787 si_pmu_min_res_ldo3p3_set(si_t *sih, osl_t *osh, bool on) in si_pmu_min_res_ldo3p3_set() argument
8790 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0); in si_pmu_min_res_ldo3p3_set()
8792 switch (CHIPID(sih->chip)) { in si_pmu_min_res_ldo3p3_set()
8797 si_corereg(sih, coreidx, LHL_REG_OFF(lhl_lp_main_ctl1_adr), in si_pmu_min_res_ldo3p3_set()
8800 si_corereg(sih, coreidx, LHL_REG_OFF(lhl_lp_main_ctl1_adr), in si_pmu_min_res_ldo3p3_set()
8812 si_pmu_min_res_set(sih, osh, min_mask, on); in si_pmu_min_res_ldo3p3_set()
8819 si_pmu_min_res_ldo3p3_get(si_t *sih, osl_t *osh, int *res) in si_pmu_min_res_ldo3p3_get() argument
8826 si_pmu_min_res_otp_pu_set(si_t *sih, osl_t *osh, bool on) in si_pmu_min_res_otp_pu_set() argument
8831 rsc = si_pmu_get_rsc_positions(sih); in si_pmu_min_res_otp_pu_set()
8837 si_pmu_min_res_set(sih, osh, min_mask, on); in si_pmu_min_res_otp_pu_set()
8843 BCMPOSTTRAPFN(si_pmu_wake_bit_offset)(si_t *sih) in BCMPOSTTRAPFN()
8847 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
8874 void hnd_pmu_clr_int_sts_req_active(osl_t *hnd_osh, si_t *sih) in hnd_pmu_clr_int_sts_req_active() argument
8878 if (AOB_ENAB(sih)) { in hnd_pmu_clr_int_sts_req_active()
8879 pmu = si_setcore(sih, PMU_CORE_ID, 0); in hnd_pmu_clr_int_sts_req_active()
8881 pmu = si_setcoreidx(sih, SI_CC_IDX); in hnd_pmu_clr_int_sts_req_active()
8894 void si_pmu_set_min_res_mask(si_t *sih, osl_t *osh, uint min_res_mask) in si_pmu_set_min_res_mask() argument
8900 origidx = si_coreidx(sih); in si_pmu_set_min_res_mask()
8901 if (AOB_ENAB(sih)) { in si_pmu_set_min_res_mask()
8902 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_min_res_mask()
8905 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmu_set_min_res_mask()
8913 si_setcoreidx(sih, origidx); in si_pmu_set_min_res_mask()
8917 si_pmu_cap_fast_lpo(si_t *sih) in si_pmu_cap_fast_lpo() argument
8919 return (PMU_REG(sih, core_cap_ext, 0, 0) & PCAP_EXT_USE_MUXED_ILP_CLK_MASK) ? TRUE : FALSE; in si_pmu_cap_fast_lpo()
8923 si_pmu_fast_lpo_disable(si_t *sih) in si_pmu_fast_lpo_disable() argument
8925 if (!si_pmu_cap_fast_lpo(sih)) { in si_pmu_fast_lpo_disable()
8930 PMU_REG(sih, pmucontrol_ext, in si_pmu_fast_lpo_disable()
8947 si_pmu_dmn1_perst_wakeup(si_t *sih, bool set) in si_pmu_dmn1_perst_wakeup() argument
8949 if (PMUREV(sih->pmurev) == 40) { in si_pmu_dmn1_perst_wakeup()
8951 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in si_pmu_dmn1_perst_wakeup()
8957 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, in si_pmu_dmn1_perst_wakeup()
9008 BCMATTACHFN(si_pmu_chipcontrol_xtal_settings_4369)(si_t *sih) in BCMATTACHFN()
9028 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, u32Mask, u32Val); in BCMATTACHFN()
9032 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, u32Mask, u32Val); in BCMATTACHFN()
9042 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, u32Mask, u32Val); in BCMATTACHFN()
9047 BCMATTACHFN(si_pmu_chipcontrol_xtal_settings_4362)(si_t *sih) in BCMATTACHFN()
9066 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, u32Mask, u32Val); in BCMATTACHFN()
9070 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, u32Mask, u32Val); in BCMATTACHFN()
9080 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, u32Mask, u32Val); in BCMATTACHFN()
9093 BCMATTACHFN(si_pmu_chipcontrol_xtal_settings_4378)(si_t *sih) in BCMATTACHFN()
9102 si_pmu_chipcontrol_xtal_bias_from_otp(sih, &xtal_bias_cal_otp_done, &xtal_bias_adj_otp); in BCMATTACHFN()
9118 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, u32Mask, u32Val); in BCMATTACHFN()
9122 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, u32Mask, u32Val); in BCMATTACHFN()
9132 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, u32Mask, u32Val); in BCMATTACHFN()
9138 BCMATTACHFN(si_pmu_chipcontrol_xtal_bias_from_otp)(si_t *sih, uint8* flag, uint8* val) in BCMATTACHFN()
9152 otp_read_8b_field(sih, BCM_OTP_FLD_XTAL_BIAS_FLAG, &xtal_bias_cal_otp_done); in BCMATTACHFN()
9154 otp_read_8b_field(sih, BCM_OTP_FLD_XTAL_BIAS_ADJ, &xtal_bias_adj); in BCMATTACHFN()
9157 si_pmu_chipcontrol_xtal_bias_cal_done_offsets(sih, &offset, &shift, &mask); in BCMATTACHFN()
9158 if (!otp_read_word(sih, offset, &datum)) { in BCMATTACHFN()
9162 si_pmu_chipcontrol_xtal_bias_val_offsets(sih, &offset, &shift, &mask); in BCMATTACHFN()
9163 if (xtal_bias_cal_otp_done && (!otp_read_word(sih, offset, &datum))) in BCMATTACHFN()
9174 BCMATTACHFN(si_pmu_chipcontrol_xtal_bias_cal_done_offsets)(si_t *sih, uint16* wrd_offset, in BCMATTACHFN()
9182 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9196 BCMATTACHFN(si_pmu_chipcontrol_xtal_bias_val_offsets)(si_t *sih, uint16* wrd_offset, in BCMATTACHFN()
9204 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9264 si_pmustatstimer_int_enable(si_t *sih) in si_pmustatstimer_int_enable() argument
9268 osl_t *osh = si_osh(sih); in si_pmustatstimer_int_enable()
9271 origidx = si_coreidx(sih); in si_pmustatstimer_int_enable()
9272 if (AOB_ENAB(sih)) { in si_pmustatstimer_int_enable()
9273 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_int_enable()
9275 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_int_enable()
9282 si_setcoreidx(sih, origidx); in si_pmustatstimer_int_enable()
9286 si_pmustatstimer_int_disable(si_t *sih) in si_pmustatstimer_int_disable() argument
9290 osl_t *osh = si_osh(sih); in si_pmustatstimer_int_disable()
9293 origidx = si_coreidx(sih); in si_pmustatstimer_int_disable()
9294 if (AOB_ENAB(sih)) { in si_pmustatstimer_int_disable()
9295 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_int_disable()
9297 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_int_disable()
9304 si_setcoreidx(sih, origidx); in si_pmustatstimer_int_disable()
9308 si_pmustatstimer_init(si_t *sih) in si_pmustatstimer_init() argument
9312 osl_t *osh = si_osh(sih); in si_pmustatstimer_init()
9318 origidx = si_coreidx(sih); in si_pmustatstimer_init()
9319 if (AOB_ENAB(sih)) { in si_pmustatstimer_init()
9320 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_init()
9322 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_init()
9337 si_setcoreidx(sih, origidx); in si_pmustatstimer_init()
9341 si_pmustatstimer_dump(si_t *sih) in si_pmustatstimer_dump() argument
9345 osl_t *osh = si_osh(sih); in si_pmustatstimer_dump()
9353 origidx = si_coreidx(sih); in si_pmustatstimer_dump()
9354 if (AOB_ENAB(sih)) { in si_pmustatstimer_dump()
9355 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_dump()
9357 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_dump()
9381 pmuintmask0, pmuintstatus, PMUREV(sih->pmurev))); in si_pmustatstimer_dump()
9392 si_setcoreidx(sih, origidx); in si_pmustatstimer_dump()
9396 si_pmustatstimer_start(si_t *sih, uint8 timerid) in si_pmustatstimer_start() argument
9400 osl_t *osh = si_osh(sih); in si_pmustatstimer_start()
9403 origidx = si_coreidx(sih); in si_pmustatstimer_start()
9404 if (AOB_ENAB(sih)) { in si_pmustatstimer_start()
9405 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_start()
9407 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_start()
9417 si_setcoreidx(sih, origidx); in si_pmustatstimer_start()
9421 si_pmustatstimer_stop(si_t *sih, uint8 timerid) in si_pmustatstimer_stop() argument
9425 osl_t *osh = si_osh(sih); in si_pmustatstimer_stop()
9428 origidx = si_coreidx(sih); in si_pmustatstimer_stop()
9429 if (AOB_ENAB(sih)) { in si_pmustatstimer_stop()
9430 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_stop()
9432 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_stop()
9442 si_setcoreidx(sih, origidx); in si_pmustatstimer_stop()
9446 si_pmustatstimer_clear(si_t *sih, uint8 timerid) in si_pmustatstimer_clear() argument
9450 osl_t *osh = si_osh(sih); in si_pmustatstimer_clear()
9453 origidx = si_coreidx(sih); in si_pmustatstimer_clear()
9454 if (AOB_ENAB(sih)) { in si_pmustatstimer_clear()
9455 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_clear()
9457 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_clear()
9465 si_setcoreidx(sih, origidx); in si_pmustatstimer_clear()
9469 si_pmustatstimer_clear_overflow(si_t *sih) in si_pmustatstimer_clear_overflow() argument
9477 osl_t *osh = si_osh(sih); in si_pmustatstimer_clear_overflow()
9480 origidx = si_coreidx(sih); in si_pmustatstimer_clear_overflow()
9481 if (AOB_ENAB(sih)) { in si_pmustatstimer_clear_overflow()
9482 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_clear_overflow()
9484 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_clear_overflow()
9496 si_pmustatstimer_clear(sih, i); in si_pmustatstimer_clear_overflow()
9501 si_setcoreidx(sih, origidx); in si_pmustatstimer_clear_overflow()
9505 si_pmustatstimer_read(si_t *sih, uint8 timerid) in si_pmustatstimer_read() argument
9509 osl_t *osh = si_osh(sih); in si_pmustatstimer_read()
9513 origidx = si_coreidx(sih); in si_pmustatstimer_read()
9514 if (AOB_ENAB(sih)) { in si_pmustatstimer_read()
9515 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_read()
9517 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_read()
9525 si_setcoreidx(sih, origidx); in si_pmustatstimer_read()
9531 si_pmustatstimer_cfg_src_num(si_t *sih, uint8 src_num, uint8 timerid) in si_pmustatstimer_cfg_src_num() argument
9535 osl_t *osh = si_osh(sih); in si_pmustatstimer_cfg_src_num()
9538 origidx = si_coreidx(sih); in si_pmustatstimer_cfg_src_num()
9539 if (AOB_ENAB(sih)) { in si_pmustatstimer_cfg_src_num()
9540 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_cfg_src_num()
9542 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_cfg_src_num()
9550 si_setcoreidx(sih, origidx); in si_pmustatstimer_cfg_src_num()
9554 si_pmustatstimer_cfg_cnt_mode(si_t *sih, uint8 cnt_mode, uint8 timerid) in si_pmustatstimer_cfg_cnt_mode() argument
9558 osl_t *osh = si_osh(sih); in si_pmustatstimer_cfg_cnt_mode()
9561 origidx = si_coreidx(sih); in si_pmustatstimer_cfg_cnt_mode()
9562 if (AOB_ENAB(sih)) { in si_pmustatstimer_cfg_cnt_mode()
9563 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_cfg_cnt_mode()
9565 pmu = si_setcoreidx(sih, SI_CC_IDX); in si_pmustatstimer_cfg_cnt_mode()
9573 si_setcoreidx(sih, origidx); in si_pmustatstimer_cfg_cnt_mode()
9590 BCMPOSTTRAPFN(si_pmu_regs_in_rodata_dump)(void *sih, void *arg2, in BCMPOSTTRAPFN()
9610 if (si_pmu_get_mac_rsrc_req_tmr_cnt(sih) > 1) { in BCMPOSTTRAPFN()
9613 if (si_pmu_get_mac_rsrc_req_tmr_cnt(sih) > 2) { in BCMPOSTTRAPFN()
9616 if (si_pmu_get_pmu_interrupt_rcv_cnt(sih) > 1) { in BCMPOSTTRAPFN()
9641 BCMPOSTTRAPFN(si_pmu_get_mac_rsrc_req_tmr_cnt)(si_t *sih) in BCMPOSTTRAPFN()
9643 if (PMUREV(sih->pmurev) >= 26) { in BCMPOSTTRAPFN()
9644 uint32 core_cap_ext = PMU_REG(sih, core_cap_ext, 0, 0); in BCMPOSTTRAPFN()
9651 return si_numd11coreunits(sih); in BCMPOSTTRAPFN()
9656 BCMPOSTTRAPFN(si_pmu_get_pmu_interrupt_rcv_cnt)(si_t *sih) in BCMPOSTTRAPFN()
9658 if (PMUREV(sih->pmurev) >= 26) { in BCMPOSTTRAPFN()
9659 uint32 core_cap_ext = PMU_REG(sih, core_cap_ext, 0, 0); in BCMPOSTTRAPFN()
9666 return si_numd11coreunits(sih); in BCMPOSTTRAPFN()
9671 si_pmu_mem_pwr_off(si_t *sih, int core_idx) in si_pmu_mem_pwr_off() argument
9675 if (si_setcore(sih, D11_CORE_ID, core_idx) == NULL) { in si_pmu_mem_pwr_off()
9680 switch (CHIPID(sih->chip)) { in si_pmu_mem_pwr_off()
9684 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in si_pmu_mem_pwr_off()
9691 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in si_pmu_mem_pwr_off()
9702 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_25, in si_pmu_mem_pwr_off()
9705 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, in si_pmu_mem_pwr_off()
9712 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in si_pmu_mem_pwr_off()
9722 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in si_pmu_mem_pwr_off()
9727 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in si_pmu_mem_pwr_off()
9746 BCMPOSTTRAPFN(si_pmu_mem_pwr_on)(si_t *sih) in BCMPOSTTRAPFN()
9750 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
9753 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMPOSTTRAPFN()
9759 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, in BCMPOSTTRAPFN()
9765 si_pmu_chipcontrol(sih, PMU_CHIPCTL17, in BCMPOSTTRAPFN()
9772 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_25, in BCMPOSTTRAPFN()
9785 BCMPOSTTRAPFN(si_pmu_disable_intr_pwrreq)(si_t *sih) in BCMPOSTTRAPFN()
9787 if (MULTIBP_CAP(sih)) { in BCMPOSTTRAPFN()
9788 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
9796 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU_CC2_CB2WL_INTR_PWRREQ_EN, 0); in BCMPOSTTRAPFN()
9797 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, PMU_CC6_ENABLE_DMN1_WAKEUP, 0); in BCMPOSTTRAPFN()
9808 BCMPOSTTRAPFN(si_pmu_clear_intmask)(si_t *sih) in BCMPOSTTRAPFN()
9812 osl_t *osh = si_osh(sih); in BCMPOSTTRAPFN()
9816 origidx = si_coreidx(sih); in BCMPOSTTRAPFN()
9817 if (AOB_ENAB(sih)) { in BCMPOSTTRAPFN()
9818 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
9820 pmu = si_setcoreidx(sih, SI_CC_IDX); in BCMPOSTTRAPFN()
9834 si_setcoreidx(sih, origidx); in BCMPOSTTRAPFN()
9839 si_pmu_res_state_pwrsw_main_wait(si_t *sih) in si_pmu_res_state_pwrsw_main_wait() argument
9843 switch (CHIPID(sih->chip)) { in si_pmu_res_state_pwrsw_main_wait()
9845 if (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) { in si_pmu_res_state_pwrsw_main_wait()
9846 SPINWAIT((PMU_REG(sih, res_state, 0, 0) & in si_pmu_res_state_pwrsw_main_wait()
9850 ret = (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) ? in si_pmu_res_state_pwrsw_main_wait()
9863 si_pmu_lvm_csr_update(si_t *sih, bool lvm) in si_pmu_lvm_csr_update() argument
9867 if (BCMDVFS_ENAB() && si_dvfs_enable_status(sih)) { in si_pmu_lvm_csr_update()
9869 si_dvfs_set_ndv_voltage(sih, ndv_volt); in si_pmu_lvm_csr_update()
9874 si_pmu_vreg_control(sih, PMU_VREG_0, in si_pmu_lvm_csr_update()
9883 si_pmu_reg_on_war_ext_wake_perst_set(si_t *sih) in si_pmu_reg_on_war_ext_wake_perst_set() argument
9885 uint origidx = si_coreidx(sih); in si_pmu_reg_on_war_ext_wake_perst_set()
9886 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_reg_on_war_ext_wake_perst_set()
9887 osl_t *osh = si_osh(sih); in si_pmu_reg_on_war_ext_wake_perst_set()
9889 if (PMUREV(sih->pmurev) == 40) { in si_pmu_reg_on_war_ext_wake_perst_set()
9903 si_setcoreidx(sih, origidx); in si_pmu_reg_on_war_ext_wake_perst_set()
9907 si_pmu_reg_on_war_ext_wake_perst_clear(si_t *sih) in si_pmu_reg_on_war_ext_wake_perst_clear() argument
9910 uint origidx = si_coreidx(sih); in si_pmu_reg_on_war_ext_wake_perst_clear()
9911 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_reg_on_war_ext_wake_perst_clear()
9912 osl_t *osh = si_osh(sih); in si_pmu_reg_on_war_ext_wake_perst_clear()
9914 if (PMUREV(sih->pmurev) == 40) { in si_pmu_reg_on_war_ext_wake_perst_clear()
9920 si_setcoreidx(sih, origidx); in si_pmu_reg_on_war_ext_wake_perst_clear()
9925 si_pmu_res_state_wait(si_t *sih, uint rsrc) in si_pmu_res_state_wait() argument
9927 SPINWAIT(!(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)), PMU_MAX_TRANSITION_DLY); in si_pmu_res_state_wait()
9928 ASSERT(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)); in si_pmu_res_state_wait()