Lines Matching refs:pllctrlreg_update
3317 uint8 spur_mode, const pllctrl_data_t *pllctrlreg_update, uint32 array_size, in si_pmu_pllctrlreg_update() argument
3323 ASSERT(pllctrlreg_update); in si_pmu_pllctrlreg_update()
3334 if (!((pllctrlreg_update[indx].clock == (uint16)xtal) && in si_pmu_pllctrlreg_update()
3335 (pllctrlreg_update[indx].mode == spur_mode))) in si_pmu_pllctrlreg_update()
3354 xf = pllctrlreg_update[indx].xf; in si_pmu_pllctrlreg_update()
3508 const pllctrl_data_t *pllctrlreg_update = NULL; in BCMATTACHFN() local
3550 pllctrlreg_update = pmu1_xtaltab0_43012; in BCMATTACHFN()
3555 pllctrlreg_update = pmu1_xtaltab0_4369; in BCMATTACHFN()
3562 pllctrlreg_update = pmu1_xtaltab0_4362; in BCMATTACHFN()
3573 pllctrlreg_update = NULL; in BCMATTACHFN()
3580 pllctrlreg_update = NULL; in BCMATTACHFN()
3586 pllctrlreg_update = pmu1_xtaltab0_4389; in BCMATTACHFN()
3612 if (!update_required && pllctrlreg_update) { in BCMATTACHFN()
3617 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update, in BCMATTACHFN()
3646 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 0, pllctrlreg_update, array_size, in BCMATTACHFN()
7980 const pllctrl_data_t *pllctrlreg_update; in si_pmu_openloop_cal_43012() local
8011 pllctrlreg_update = pmu1_xtaltab0_43012; in si_pmu_openloop_cal_43012()
8015 pllctrlreg_update, array_size, pllctrlreg_val); in si_pmu_openloop_cal_43012()
8061 pllctrlreg_update = pmu1_xtaltab0_43012; in si_pmu_openloop_cal_43012()
8065 pllctrlreg_update, array_size, pllctrlreg_val); in si_pmu_openloop_cal_43012()