148 static void si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask,
150 static void si_pmu_pll_on(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 min_mask,
1697 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_avbtimer_enable()  local
1715 			min_mask = R_REG(osh, &pmu->min_res_mask);  in si_pmu_avbtimer_enable()
1720 				min_mask |= PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU);  in si_pmu_avbtimer_enable()
1721 				min_mask |= PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL);  in si_pmu_avbtimer_enable()
1722 				W_REG(osh, &pmu->min_res_mask, min_mask);  in si_pmu_avbtimer_enable()
1750 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_res_masks()  local
1757 			min_mask = 0x103;  in si_pmu_res_masks()
1772 		min_mask = PMURES_BIT(RES43602_LPLDO_PU)  | PMURES_BIT(RES43602_REGULATOR)      |  in si_pmu_res_masks()
1784 			min_mask &= ~PMURES_BIT(RES43602_LPLDO_PU);  in si_pmu_res_masks()
1786 		max_mask = (1<<3) | min_mask          | PMURES_BIT(RES43602_RADIO_PU)        |  in si_pmu_res_masks()
1794 			min_mask = PMURES_BIT(RES43602_LPLDO_PU);  in si_pmu_res_masks()
1806 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1810 				min_mask = 0x0000011;  in si_pmu_res_masks()
1812 				min_mask = 0x0000001;  in si_pmu_res_masks()
1820 		min_mask = 0x064fffff;  in si_pmu_res_masks()
1824 				min_mask = 0x064fffff;  in si_pmu_res_masks()
1826 				min_mask = PMURES_BIT(RES4378_DUMMY);  in si_pmu_res_masks()
1834 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1838 				min_mask = PMURES_BIT(RES4387_DUMMY);  in si_pmu_res_masks()
1840 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
1842 					min_mask |= PMURES_BIT(RES4387_FAST_LPO_AVAIL) |  in si_pmu_res_masks()
1853 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1857 				min_mask = PMURES_BIT(RES4388_DUMMY);  in si_pmu_res_masks()
1859 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
1861 					min_mask |= PMURES_BIT(RES4388_FAST_LPO_AVAIL) |  in si_pmu_res_masks()
1875 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1879 				min_mask = PMURES_BIT(RES4389_DUMMY);  in si_pmu_res_masks()
1881 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
1883 					min_mask |= PMURES_BIT(RES4389_FAST_LPO_AVAIL) |  in si_pmu_res_masks()
1893 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1898 		min_mask = 0x64fffff;  in si_pmu_res_masks()
1901 			min_mask = (PMURES_BIT(RES4362_DUMMY));  in si_pmu_res_masks()
1914 		si_nvram_res_masks(sih, &min_mask, &max_mask);  in si_pmu_res_masks()
1917 	*pmin = min_mask;  in si_pmu_res_masks()
2068 	uint32 min_mask = 0, max_mask = 0;  in BCMATTACHFN()  local
2427 	si_pmu_res_masks(sih, &min_mask, &max_mask);  in BCMATTACHFN()
2429 	min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, FALSE);  in BCMATTACHFN()
2441 		min_mask = (uint32)bcm_strtoul(val, NULL, 0);  in BCMATTACHFN()
2478 		max_mask |= min_mask;  in BCMATTACHFN()
2494 		if (min_mask)  in BCMATTACHFN()
2495 			OR_REG(osh, &pmu->max_res_mask, min_mask);  in BCMATTACHFN()
2499 	if (min_mask) {  in BCMATTACHFN()
2500 		PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));  in BCMATTACHFN()
2501 		W_REG(osh, &pmu->min_res_mask, min_mask);  in BCMATTACHFN()
4095 si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask,  in si_pmu_pll_off()  argument
4101 	*min_mask = R_REG(osh, &pmu->min_res_mask);  in si_pmu_pll_off()
4156 si_pmu_pll_off_PARR(si_t *sih, osl_t *osh, uint32 *min_mask,  in si_pmu_pll_off_PARR()  argument
4175 	*min_mask = R_REG(osh, &pmu->min_res_mask);  in si_pmu_pll_off_PARR()
4271 	uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;  in BCMATTACHFN()  local
4333 			si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4350 			si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4367 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4382 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4457 	uint32 max_mask = 0, min_mask = 0, clk_ctl_st = 0;  in si_pmu_update_backplane_clock()  local
4471 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in si_pmu_update_backplane_clock()
4482 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in si_pmu_update_backplane_clock()
5901 	uint32 min_mask = 0;  in BCMINITFN()  local
5923 	si_pmu_res_masks(sih, &min_mask, &max_mask);  in BCMINITFN()
5926 	min_mask = R_REG(osh, &pmu->min_res_mask);  in BCMINITFN()
5928 	deps &= ~min_mask;  in BCMINITFN()
6076 		uint32 min_mask = 0;  in si_pmu_otp_power()  local
6080 			min_mask = R_REG(osh, &pmu->min_res_mask);  in si_pmu_otp_power()
6081 			*min_res_mask = min_mask;  in si_pmu_otp_power()
6083 			min_mask |= rsrcs;  in si_pmu_otp_power()
6084 			min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE);  in si_pmu_otp_power()
6087 			PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", min_mask));  in si_pmu_otp_power()
6088 			W_REG(osh, &pmu->min_res_mask, min_mask);  in si_pmu_otp_power()
6100 				min_mask = *min_res_mask;  in si_pmu_otp_power()
6102 				min_mask = R_REG(osh, &pmu->min_res_mask);  in si_pmu_otp_power()
6104 			min_mask &= ~rsrcs;  in si_pmu_otp_power()
6109 			min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE);  in si_pmu_otp_power()
6110 			on_check = ((min_mask & rsrcs) != 0);  in si_pmu_otp_power()
6112 			PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", min_mask));  in si_pmu_otp_power()
6113 			W_REG(osh, &pmu->min_res_mask, min_mask);  in si_pmu_otp_power()
7586 		uint32 min_mask;  in BCMATTACHFN()  local
7594 			min_mask = R_REG(osh, &pmu->min_res_mask) |  in BCMATTACHFN()
7597 			W_REG(osh, &pmu->min_res_mask, min_mask);  in BCMATTACHFN()
7786 		uint32 min_mask;  in BCMATTACHFN()  local
7789 			min_mask = R_REG(osh, &pmu->min_res_mask) |  in BCMATTACHFN()
7792 			W_REG(osh, &pmu->min_res_mask, min_mask);  in BCMATTACHFN()
8271 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_res_minmax_update()  local
8294 		min_mask = RES43012_PMU_SLEEP;  in si_pmu_res_minmax_update()
8305 		si_pmu_res_masks(sih, &min_mask, &max_mask);  in si_pmu_res_minmax_update()
8311 	if (min_mask) {  in si_pmu_res_minmax_update()
8313 		min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, FALSE);  in si_pmu_res_minmax_update()
8314 		W_REG(osh, &pmu->min_res_mask, min_mask);  in si_pmu_res_minmax_update()
8593 si_pmu_min_res_set(si_t *sih, osl_t *osh, uint min_mask, bool set)  in si_pmu_min_res_set()  argument
8613 	min_mask |= si_pmu_res_deps(sih, osh, pmu, min_mask, TRUE);  in si_pmu_min_res_set()
8620 		OR_REG(osh, &pmu->min_res_mask, min_mask);  in si_pmu_min_res_set()
8622 		min_mask &= ~min_res;  in si_pmu_min_res_set()
8623 		AND_REG(osh, &pmu->min_res_mask, ~min_mask);  in si_pmu_min_res_set()
8632 	return min_mask;  in si_pmu_min_res_set()
8789 	uint32 min_mask = 0;  in si_pmu_min_res_ldo3p3_set()  local
8795 			min_mask = PMURES_BIT(RES4369_LDO3P3_PU);  in si_pmu_min_res_ldo3p3_set()
8806 			min_mask = PMURES_BIT(RES4378_LDO3P3_PU);  in si_pmu_min_res_ldo3p3_set()
8812 	si_pmu_min_res_set(sih, osh, min_mask, on);  in si_pmu_min_res_ldo3p3_set()
8828 	uint32 min_mask = 0;  in si_pmu_min_res_otp_pu_set()  local
8833 		min_mask = PMURES_BIT(rsc->otp_pu);  in si_pmu_min_res_otp_pu_set()
8837 	si_pmu_min_res_set(sih, osh, min_mask, on);  in si_pmu_min_res_otp_pu_set()