1716 			max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_avbtimer_enable()
1723 				W_REG(osh, &pmu->max_res_mask, max_mask);  in si_pmu_avbtimer_enable()
1729 				AND_REG(osh, &pmu->max_res_mask,  in si_pmu_avbtimer_enable()
1731 				AND_REG(osh, &pmu->max_res_mask,  in si_pmu_avbtimer_enable()
2486 		OR_REG(osh, &pmu->max_res_mask, max_mask);  in BCMATTACHFN()
2495 			OR_REG(osh, &pmu->max_res_mask, min_mask);  in BCMATTACHFN()
2507 		W_REG(osh, &pmu->max_res_mask, max_mask);  in BCMATTACHFN()
4102 	*max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_pll_off()
4129 		OR_REG(osh,  &pmu->max_res_mask, ht_req);  in si_pmu_pll_off()
4143 		AND_REG(osh, &pmu->max_res_mask, ~ht_req);  in si_pmu_pll_off()
4176 	*max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_pll_off_PARR()
4208 		OR_REG(osh, &pmu->max_res_mask, ht_req);  in si_pmu_pll_off_PARR()
4217 	AND_REG(osh, &pmu->max_res_mask, ~ht_req);  in si_pmu_pll_off_PARR()
4239 		OR_REG(osh, &pmu->max_res_mask, max_mask_mask);  in si_pmu_pll_on()
4893 		mask = R_REG(osh, &pmu->max_res_mask) | PMURES_BIT(RES43602_PARLDO_PU);  in si_pmu_switch_on_PARLDO()
4894 		W_REG(osh, &pmu->max_res_mask, mask);  in si_pmu_switch_on_PARLDO()
4925 		mask = R_REG(osh, &pmu->max_res_mask) & ~PMURES_BIT(RES43602_PARLDO_PU);  in si_pmu_switch_off_PARLDO()
4926 		W_REG(osh, &pmu->max_res_mask, mask);  in si_pmu_switch_off_PARLDO()
7117 		val = R_REG(osh, &pmu->max_res_mask);  in BCMATTACHFN()
7128 		val = R_REG(osh, &pmu->max_res_mask);  in BCMATTACHFN()
7139 		val = R_REG(osh, &pmu->max_res_mask);  in BCMATTACHFN()
8318 		W_REG(osh, &pmu->max_res_mask, max_mask);  in si_pmu_res_minmax_update()
8348 		OFFSETOF(pmuregs_t, max_res_mask),