149 	uint32 *max_mask, uint32 *clk_ctl_st);
151 	uint32 max_mask, uint32 clk_ctl_st);
1697 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_avbtimer_enable()  local
1716 			max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_avbtimer_enable()
1718 				max_mask |= PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU);  in si_pmu_avbtimer_enable()
1719 				max_mask |= PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL);  in si_pmu_avbtimer_enable()
1723 				W_REG(osh, &pmu->max_res_mask, max_mask);  in si_pmu_avbtimer_enable()
1750 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_res_masks()  local
1766 				max_mask = 0x1ff;  in si_pmu_res_masks()
1786 		max_mask = (1<<3) | min_mask          | PMURES_BIT(RES43602_RADIO_PU)        |  in si_pmu_res_masks()
1803 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1816 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1830 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1849 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1867 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1889 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1894 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1904 		max_mask = 0x7FFFFFFF;  in si_pmu_res_masks()
1914 		si_nvram_res_masks(sih, &min_mask, &max_mask);  in si_pmu_res_masks()
1918 	*pmax = max_mask;  in si_pmu_res_masks()
2068 	uint32 min_mask = 0, max_mask = 0;  in BCMATTACHFN()  local
2427 	si_pmu_res_masks(sih, &min_mask, &max_mask);  in BCMATTACHFN()
2435 		max_mask = (uint32)bcm_strtoul(val, NULL, 0);  in BCMATTACHFN()
2476 	if (max_mask) {  in BCMATTACHFN()
2478 		max_mask |= min_mask;  in BCMATTACHFN()
2486 		OR_REG(osh, &pmu->max_res_mask, max_mask);  in BCMATTACHFN()
2505 	if (max_mask) {  in BCMATTACHFN()
2506 		PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));  in BCMATTACHFN()
2507 		W_REG(osh, &pmu->max_res_mask, max_mask);  in BCMATTACHFN()
4096 	uint32 *max_mask, uint32 *clk_ctl_st)  in si_pmu_pll_off()  argument
4102 	*max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_pll_off()
4157 uint32 *max_mask, uint32 *clk_ctl_st)  in si_pmu_pll_off_PARR()  argument
4176 	*max_mask = R_REG(osh, &pmu->max_res_mask);  in si_pmu_pll_off_PARR()
4271 	uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;  in BCMATTACHFN()  local
4333 			si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4350 			si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4367 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4382 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4457 	uint32 max_mask = 0, min_mask = 0, clk_ctl_st = 0;  in si_pmu_update_backplane_clock()  local
4471 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in si_pmu_update_backplane_clock()
4482 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in si_pmu_update_backplane_clock()
5903 	uint32 max_mask = 0;  in BCMINITFN()  local
5923 	si_pmu_res_masks(sih, &min_mask, &max_mask);  in BCMINITFN()
8271 	uint32 min_mask = 0, max_mask = 0;  in si_pmu_res_minmax_update()  local
8289 		max_mask = 0; /* Only care about min_mask for now */  in si_pmu_res_minmax_update()
8305 		si_pmu_res_masks(sih, &min_mask, &max_mask);  in si_pmu_res_minmax_update()
8306 		max_mask = 0; /* Don't need to update max */  in si_pmu_res_minmax_update()
8316 	if (max_mask) {  in si_pmu_res_minmax_update()
8317 		max_mask |= si_pmu_res_deps(sih, osh, pmu, max_mask, FALSE);  in si_pmu_res_minmax_update()
8318 		W_REG(osh, &pmu->max_res_mask, max_mask);  in si_pmu_res_minmax_update()