149 	uint32 *max_mask, uint32 *clk_ctl_st);
151 	uint32 max_mask, uint32 clk_ctl_st);
4096 	uint32 *max_mask, uint32 *clk_ctl_st)  in si_pmu_pll_off()  argument
4103 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off()
4125 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4131 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4133 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4145 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4147 		ASSERT(!(si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4157 uint32 *max_mask, uint32 *clk_ctl_st)  in si_pmu_pll_off_PARR()  argument
4177 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off_PARR()
4203 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4210 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4212 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4246 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4248 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4271 	uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0;  in BCMATTACHFN()  local
4333 			si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4350 			si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4367 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in BCMATTACHFN()
4382 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in BCMATTACHFN()
4457 	uint32 max_mask = 0, min_mask = 0, clk_ctl_st = 0;  in si_pmu_update_backplane_clock()  local
4471 	si_pmu_pll_off(sih, osh, pmu, &min_mask, &max_mask, &clk_ctl_st);  in si_pmu_update_backplane_clock()
4482 	si_pmu_pll_on(sih, osh, pmu, min_mask, max_mask, clk_ctl_st);  in si_pmu_update_backplane_clock()
4953 		if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in BCMATTACHFN()
5191 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, CCS_FORCEHT)  in BCMATTACHFN()
5483 	fastclk = ((R_REG(osh, ARMREG(regs, clk_ctl_st)) & CCS_ARMFASTCLOCKREQ) != 0);  in si_pmu_mem_ca7clock()
7242 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);  in BCMATTACHFN()
8000 			OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_openloop_cal_43012()
8002 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_openloop_cal_43012()
8336 	OFFSETOF(chipcregs_t, clk_ctl_st),